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path: root/PinLock.sch-bak
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2019-11-21Begin renamingLeonard Kugis-22/+33
2019-11-20UARTLeonard Kugis-1864/+1885
Changed UART from 2 to 4 pin connector, connecting GND and VCC additionally.
2019-11-19GeneralLeonard Kugis-1864/+1864
Removed too many test points.
2019-11-13.Leonard Kugis-1/+55
2019-11-13Schematic, generalLeonard Kugis-219/+748
Added test points everywhere neccessary. Added missing pull resistors to guarantee a defined state everywhere.
2019-11-13Schematic, UARTLeonard Kugis-454/+937
Added connectors for UART access.
2019-11-13Schematic, mainLeonard Kugis-30/+59
Added pull resistors to every pin of uC. Restructured main schematic. Added ISP interface.
2019-11-13Schematic, mainLeonard Kugis-35/+281
Added capacitor in parallel to reset switch to reduce sensitivity and oscillations.
2019-11-13Schematic, main, generalLeonard Kugis-43/+183
Added pull resistors to all ports. Added capacitors for all components to prevent high switching currents. Reordered status LEDs and transistors.
2019-11-07Schematic, StatusLeonard Kugis-64/+106
Separated logic IO from power with transistors.
2019-11-07Schematic, JTAGLeonard Kugis-341/+341
Added JTAG interface.
2019-11-04LayoutLeonard Kugis-266/+78
Minor layout fix.
2019-11-04structure, buttons, statusLeonard Kugis-113/+453
Implemented hierarchy. Added button interface. Added status interface.
2019-11-03SchematicLeonard Kugis-0/+173
Added Power wirings and connectors. Added 7-segment display output components and wiring to schematic. Added shift registers for button inputs.
2019-11-01Initial commitLeonard Kugis-0/+16