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path: root/PinLock.sch
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2019-11-25Schematic, LayoutLeonard Kugis-1936/+1932
Changed Barrel Jack pinout. Layout components placed.
2019-11-24Layout not fitting yet, needs improvementLeonard Kugis-96/+96
2019-11-24Begin associationsLeonard Kugis-46/+86
2019-11-24GeneralLeonard Kugis-459/+459
Added references to all elements.
2019-11-21Begin renamingLeonard Kugis-38/+49
2019-11-20UARTLeonard Kugis-1864/+1885
Changed UART from 2 to 4 pin connector, connecting GND and VCC additionally.
2019-11-19GeneralLeonard Kugis-1864/+1864
Removed too many test points.
2019-11-13Schematic, mainLeonard Kugis-1/+55
Added capacitors for subschematics.
2019-11-13Schematic, generalLeonard Kugis-203/+715
Added test points everywhere neccessary. Added missing pull resistors to guarantee a defined state everywhere.
2019-11-13Schematic, UARTLeonard Kugis-24/+41
Added connectors for UART access.
2019-11-13Schematic, mainLeonard Kugis-454/+937
Added pull resistors to every pin of uC. Restructured main schematic. Added ISP interface.
2019-11-13Schematic, mainLeonard Kugis-30/+59
Added capacitor in parallel to reset switch to reduce sensitivity and oscillations.
2019-11-13Schematic, main, generalLeonard Kugis-72/+458
Added pull resistors to all ports. Added capacitors for all components to prevent high switching currents. Reordered status LEDs and transistors.
2019-11-07Schematic, JTAGLeonard Kugis-64/+106
Added JTAG interface.
2019-11-07Schematic, PinoutLeonard Kugis-341/+341
Moved buttons and status interface to Port D to prepare Port C as JTAG interface.
2019-11-04structure, buttons, statusLeonard Kugis-462/+147
Implemented hierarchy. Added button interface. Added status interface.
2019-11-03SchematicLeonard Kugis-90/+595
Added Power wirings and connectors. Added 7-segment display output components and wiring to schematic. Added shift registers for button inputs.
2019-11-01Initial commitLeonard Kugis-0/+151