TurboSwap

FPGA-based SDIO Interface Memory Expansion Module for Smartphones

TurboSwap is a flexible PCB module that connects to smartphones via the SDIO interface, providing memory expansion through switchable access to either external Micro-SD cards or high-speed PSRAM (LPDDR4X). At its core is a Lattice iCE40UP3K FPGA that routes SDIO commands dynamically between the two memory types based on memory map.

Currently only XZ2C is supported.

Installation

1. Flex PCB Soldering:
2. Align the 14-pin Micro-SD edge connector with your smartphone's SDIO interface
3. Use low-temperature solder (SAC305 recommended) to prevent damage to the flexible PCB substrate
4. Apply gentle, even pressure during soldering to ensure proper pin alignment

5. Connect the Micro-SD edge connector pins: CLK, CMD, DAT0-DAT3, VCC, VSS, WP, and reserved pins

6. Power Connection:

7. The module draws power directly from the smartphone's SDIO interface (3.3V VCC)
8. Internal AP2112K LDO regulators generate stable 1.2V for the FPGA core

9. No external power supply needed - operates entirely from SDIO bus power

10. Memory Configuration:

11. Insert Micro-SD card into the external card reader slot
12. For PSRAM-only operation, ensure SD card is either removed or disabled via FPGA configuration

Structure

Hardware Architecture

• FPGA: Lattice iCE40UP3K (SG48 package) - Memory routing controller
• Memory Subsystem: Kingston 32EM16-M4CTX29-8AD11 (32GB eMMC + 16Gb LPDDR4X)
• eMMC interface for block storage (like SD card)
• LPDDR4X interface for high-speed RAM-like operations
• Connectors:
• J1: Micro-SD Edge Connector (14-pin SDIO to smartphone)
• J2: µSD Card Reader (external storage expansion)
• J3: Debug/Programming Header (2×4 pins for FPGA configuration)
• Power Management: AP2112K LDO regulators for clean 3.3V→1.2V conversion
• Signal Integrity: 10kΩ pull-ups on SDIO data lines, 22Ω series termination on high-speed traces

FPGA Design (Verilog HDL)

Core modules implementing memory routing: - turbo_top.v: Main switching fabric and control logic - sdio_to_spi.v: SDIO protocol to SPI command translation - memory_router.v: Dynamic routing between eMMC and LPDDR4X interfaces - cache_controller.v: 32KB direct-mapped cache with LRU replacement - clock_divider.v: Clock domain crossing and timing optimization - fifo_buffer.v: Dual-clock FIFOs for rate matching between interfaces

Performance

Memory Specifications

Latency Comparison

License

TurboSwap is open-source hardware released under the CERN Open Hardware License Version 2 - Strongly Reciprocal (CERN-OHL-S).