`timescale 1ns / 1ps

module turbo_top (
    input wire SD_CLK,
    inout wire SD_CMD,
    inout wire [3:0] SD_DAT,
    
    output wire SPI0_SCK,
    output wire SPI0_MOSI,
    input  wire SPI0_MISO,
    output wire SPI0_CS,
    
    output wire SPI1_SCK,
    output wire SPI1_MOSI,
    input  wire SPI1_MISO,
    output wire SPI1_CS,
    
    output wire UART_TX,
    input  wire UART_RX,
    
    output wire LED0,
    output wire LED1,
    output wire LED2,
    output wire LED3,
    
    input  wire CRESET_B,
    output wire CDONE,
    
    input wire CLK_12MHZ,
    
    output wire PWR_EN,
    input  wire PWR_GOOD
);

    wire clk_12mhz;
    wire clk_50mhz;
    wire clk_sdio;
    wire clk_spi;
    
    wire rst_n;
    wire sdio_cmd_dir;
    wire [3:0] sdio_dat_dir;
    
    wire [7:0] cmd_opcode;
    wire [31:0] cmd_address;
    wire [15:0] cmd_length;
    wire cmd_valid;
    wire cmd_ready;
    
    wire [7:0] data_in;
    wire data_in_valid;
    wire data_in_ready;
    
    wire [7:0] data_out;
    wire data_out_valid;
    wire data_out_ready;
    
    wire [3:0] sdio_state;
    wire [3:0] spi_state;
    wire [3:0] flash_select;
    
    wire [7:0] status_reg;
    
    clock_divider clock_div (
        .clk_in(CLK_12MHZ),
        .rst_n(CRESET_B),
        .clk_12mhz(clk_12mhz),
        .clk_50mhz(clk_50mhz),
        .clk_sdio(clk_sdio),
        .clk_spi(clk_spi)
    );
    
    sdio_to_spi sdio_converter (
        .sd_clk(SD_CLK),
        .sd_cmd(SD_CMD),
        .sd_dat(SD_DAT),
        .sd_cmd_dir(sdio_cmd_dir),
        .sd_dat_dir(sdio_dat_dir),
        .clk_sys(clk_50mhz),
        .rst_n(rst_n),
        .cmd_opcode(cmd_opcode),
        .cmd_address(cmd_address),
        .cmd_length(cmd_length),
        .cmd_valid(cmd_valid),
        .cmd_ready(cmd_ready),
        .data_out(data_out),
        .data_out_valid(data_out_valid),
        .data_out_ready(data_out_ready),
        .data_in(data_in),
        .data_in_valid(data_in_valid),
        .data_in_ready(data_in_ready),
        .sdio_state(sdio_state),
        .status_reg(status_reg[3:0])
    );
    
    spi_controller spi_ctrl (
        .clk(clk_spi),
        .rst_n(rst_n),
        .cmd_opcode(cmd_opcode),
        .cmd_address(cmd_address),
        .cmd_length(cmd_length),
        .cmd_valid(cmd_valid),
        .cmd_ready(cmd_ready),
        .data_in(data_in),
        .data_in_valid(data_in_valid),
        .data_in_ready(data_in_ready),
        .data_out(data_out),
        .data_out_valid(data_out_valid),
        .data_out_ready(data_out_ready),
        .spi0_sck(SPI0_SCK),
        .spi0_mosi(SPI0_MOSI),
        .spi0_miso(SPI0_MISO),
        .spi0_cs(SPI0_CS),
        .spi1_sck(SPI1_SCK),
        .spi1_mosi(SPI1_MOSI),
        .spi1_miso(SPI1_MISO),
        .spi1_cs(SPI1_CS),
        .flash_select(flash_select),
        .spi_state(spi_state),
        .status_reg(status_reg[7:4])
    );
    
    fifo_buffer data_fifo (
        .wr_clk(clk_sdio),
        .rd_clk(clk_spi),
        .rst_n(rst_n),
        .wr_data(data_out),
        .wr_valid(data_out_valid),
        .wr_ready(data_out_ready),
        .rd_data(data_in),
        .rd_valid(data_in_valid),
        .rd_ready(data_in_ready),
        .fifo_empty(),
        .fifo_full(),
        .fifo_level()
    );
    
    assign rst_n = CRESET_B & PWR_GOOD;
    
    assign SD_CMD = sdio_cmd_dir ? 1'bz : 1'b0;
    generate
        genvar i;
        for (i = 0; i < 4; i = i + 1) begin : dat_dir_gen
            assign SD_DAT[i] = sdio_dat_dir[i] ? 1'bz : 1'b0;
        end
    endgenerate
    
    assign LED0 = ~rst_n;
    assign LED1 = |sdio_state;
    assign LED2 = |spi_state;
    assign LED3 = |flash_select;
    
    assign UART_TX = UART_RX;
    
    assign PWR_EN = 1'b1;
    
    assign CDONE = 1'b1;
    
endmodule