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authorAtaberk <olgunataberk@gmail.com>2022-09-25 17:22:03 +0200
committerAtaberk <olgunataberk@gmail.com>2022-09-25 17:22:03 +0200
commitdc0b3db1b4f1895a07e5fe280ee3790e87f97b9f (patch)
treeb47203aa281bdd959def4451c84d310cd9cf2e12 /prebuilt
downloaddram-bender-dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f.tar.gz
Initial commit
Diffstat (limited to 'prebuilt')
-rw-r--r--prebuilt/.gitignore4
-rw-r--r--prebuilt/XCU200/XCU200_C1_RDIMM_1R_x4.bitbin0 -> 80159222 bytes
-rw-r--r--prebuilt/XCU200/XCU200_C1_RDIMM_1R_x4.ltx32
-rw-r--r--prebuilt/XCU200/XCU200_C1_RDIMM_1R_x8.bitbin0 -> 80159222 bytes
-rw-r--r--prebuilt/XCU200/XCU200_C1_RDIMM_1R_x8.ltx32
-rw-r--r--prebuilt/XCU200/XCU200_C1_RDIMM_2R_x4.bitbin0 -> 80159222 bytes
-rw-r--r--prebuilt/XCU200/XCU200_C1_RDIMM_2R_x4.ltx32
-rw-r--r--prebuilt/XCU200/XCU200_C1_RDIMM_2R_x8.bitbin0 -> 80159222 bytes
-rw-r--r--prebuilt/XCU200/XCU200_C1_RDIMM_2R_x8.ltx32
-rw-r--r--prebuilt/XCU200/XCU200_C1_UDIMM_1R_x8.bitbin0 -> 80159222 bytes
-rw-r--r--prebuilt/XCU200/XCU200_C1_UDIMM_1R_x8.ltx32
-rw-r--r--prebuilt/XCU200/XCU200_C1_UDIMM_2R_x8.bitbin0 -> 80159222 bytes
-rw-r--r--prebuilt/XCU200/XCU200_C1_UDIMM_2R_x8.ltx32
-rw-r--r--prebuilt/XCU200/XCU200_C2_RDIMM_1R_x4.bitbin0 -> 80159222 bytes
-rw-r--r--prebuilt/XCU200/XCU200_C2_RDIMM_1R_x4.ltx32
-rw-r--r--prebuilt/XCU200/XCU200_C3_RDIMM_1R_x4.bitbin0 -> 80159222 bytes
-rw-r--r--prebuilt/XCU200/XCU200_C3_RDIMM_1R_x4.ltx32
-rw-r--r--prebuilt/XUPP3R/XUPP3R_C1_RDIMM_1R_x4.bitbin0 -> 18669640 bytes
-rw-r--r--prebuilt/XUPP3R/XUPP3R_C1_RDIMM_1R_x4.ltx4
-rw-r--r--prebuilt/XUPP3R/XUPP3R_C1_RDIMM_2R_x8.bitbin0 -> 18958556 bytes
-rw-r--r--prebuilt/XUPP3R/XUPP3R_C1_RDIMM_2R_x8.ltx4
-rw-r--r--prebuilt/XUPP3R/XUPP3R_C1_UDIMM_1R_x8.bitbin0 -> 18946148 bytes
-rw-r--r--prebuilt/XUPP3R/XUPP3R_C1_UDIMM_1R_x8.ltx4
-rw-r--r--prebuilt/XUPVVH/XUPVVH_C1_RDIMM_1R_x4.bitbin0 -> 28489729 bytes
-rw-r--r--prebuilt/XUPVVH/XUPVVH_C1_RDIMM_1R_x4.ltx32
-rw-r--r--prebuilt/XUSP3S/XUSP3S_C1_SODIMM_1R_x8.bitbin0 -> 10051057 bytes
-rw-r--r--prebuilt/XUSP3S/XUSP3S_C1_SODIMM_1R_x8.ltx20
-rw-r--r--prebuilt/XUSP3S/XUSP3S_C2_SODIMM_1R_x8.bitbin0 -> 11028045 bytes
-rw-r--r--prebuilt/XUSP3S/XUSP3S_C2_SODIMM_1R_x8.ltx20
-rwxr-xr-xprebuilt/programFPGA.sh65
-rw-r--r--prebuilt/programFPGA.tcl31
31 files changed, 440 insertions, 0 deletions
diff --git a/prebuilt/.gitignore b/prebuilt/.gitignore
new file mode 100644
index 0000000..e534e56
--- /dev/null
+++ b/prebuilt/.gitignore
@@ -0,0 +1,4 @@
+webtalk.jou
+webtalk.log
+webtalk_*.backup.jou
+webtalk_*.backup.log
diff --git a/prebuilt/XCU200/XCU200_C1_RDIMM_1R_x4.bit b/prebuilt/XCU200/XCU200_C1_RDIMM_1R_x4.bit
new file mode 100644
index 0000000..a9e16e8
--- /dev/null
+++ b/prebuilt/XCU200/XCU200_C1_RDIMM_1R_x4.bit
Binary files differ
diff --git a/prebuilt/XCU200/XCU200_C1_RDIMM_1R_x4.ltx b/prebuilt/XCU200/XCU200_C1_RDIMM_1R_x4.ltx
new file mode 100644
index 0000000..1366ec4
--- /dev/null
+++ b/prebuilt/XCU200/XCU200_C1_RDIMM_1R_x4.ltx
@@ -0,0 +1,32 @@
+{
+ "ltx_root": {
+ "version": 4,
+ "minor": 0,
+ "ltx_data": [
+ {
+ "name": "EDA_PROBESET",
+ "active": true,
+ "debug_cores": [
+ {
+ "type": "XSDB_V3",
+ "name": "dbg_hub",
+ "spec": "labtools_xsdbm_v3",
+ "clk_input_freq_hz": "41670836"
+ },
+ {
+ "type": "XSDBS_V2",
+ "name": "phy_ddr4_i",
+ "spec": "labtools_xsdbslavelib_v2",
+ "ipName": "DDR4_SDRAM",
+ "core_location": {
+ "user_chain": 1,
+ "slave_index": 0,
+ "bscan_switch_index": 0
+ },
+ "uuid": "A4798F5A1DC8569B9C8CB73395566903"
+ }
+ ]
+ }
+ ]
+ }
+} \ No newline at end of file
diff --git a/prebuilt/XCU200/XCU200_C1_RDIMM_1R_x8.bit b/prebuilt/XCU200/XCU200_C1_RDIMM_1R_x8.bit
new file mode 100644
index 0000000..40dc4f4
--- /dev/null
+++ b/prebuilt/XCU200/XCU200_C1_RDIMM_1R_x8.bit
Binary files differ
diff --git a/prebuilt/XCU200/XCU200_C1_RDIMM_1R_x8.ltx b/prebuilt/XCU200/XCU200_C1_RDIMM_1R_x8.ltx
new file mode 100644
index 0000000..1366ec4
--- /dev/null
+++ b/prebuilt/XCU200/XCU200_C1_RDIMM_1R_x8.ltx
@@ -0,0 +1,32 @@
+{
+ "ltx_root": {
+ "version": 4,
+ "minor": 0,
+ "ltx_data": [
+ {
+ "name": "EDA_PROBESET",
+ "active": true,
+ "debug_cores": [
+ {
+ "type": "XSDB_V3",
+ "name": "dbg_hub",
+ "spec": "labtools_xsdbm_v3",
+ "clk_input_freq_hz": "41670836"
+ },
+ {
+ "type": "XSDBS_V2",
+ "name": "phy_ddr4_i",
+ "spec": "labtools_xsdbslavelib_v2",
+ "ipName": "DDR4_SDRAM",
+ "core_location": {
+ "user_chain": 1,
+ "slave_index": 0,
+ "bscan_switch_index": 0
+ },
+ "uuid": "A4798F5A1DC8569B9C8CB73395566903"
+ }
+ ]
+ }
+ ]
+ }
+} \ No newline at end of file
diff --git a/prebuilt/XCU200/XCU200_C1_RDIMM_2R_x4.bit b/prebuilt/XCU200/XCU200_C1_RDIMM_2R_x4.bit
new file mode 100644
index 0000000..a9e16e8
--- /dev/null
+++ b/prebuilt/XCU200/XCU200_C1_RDIMM_2R_x4.bit
Binary files differ
diff --git a/prebuilt/XCU200/XCU200_C1_RDIMM_2R_x4.ltx b/prebuilt/XCU200/XCU200_C1_RDIMM_2R_x4.ltx
new file mode 100644
index 0000000..1366ec4
--- /dev/null
+++ b/prebuilt/XCU200/XCU200_C1_RDIMM_2R_x4.ltx
@@ -0,0 +1,32 @@
+{
+ "ltx_root": {
+ "version": 4,
+ "minor": 0,
+ "ltx_data": [
+ {
+ "name": "EDA_PROBESET",
+ "active": true,
+ "debug_cores": [
+ {
+ "type": "XSDB_V3",
+ "name": "dbg_hub",
+ "spec": "labtools_xsdbm_v3",
+ "clk_input_freq_hz": "41670836"
+ },
+ {
+ "type": "XSDBS_V2",
+ "name": "phy_ddr4_i",
+ "spec": "labtools_xsdbslavelib_v2",
+ "ipName": "DDR4_SDRAM",
+ "core_location": {
+ "user_chain": 1,
+ "slave_index": 0,
+ "bscan_switch_index": 0
+ },
+ "uuid": "A4798F5A1DC8569B9C8CB73395566903"
+ }
+ ]
+ }
+ ]
+ }
+} \ No newline at end of file
diff --git a/prebuilt/XCU200/XCU200_C1_RDIMM_2R_x8.bit b/prebuilt/XCU200/XCU200_C1_RDIMM_2R_x8.bit
new file mode 100644
index 0000000..40dc4f4
--- /dev/null
+++ b/prebuilt/XCU200/XCU200_C1_RDIMM_2R_x8.bit
Binary files differ
diff --git a/prebuilt/XCU200/XCU200_C1_RDIMM_2R_x8.ltx b/prebuilt/XCU200/XCU200_C1_RDIMM_2R_x8.ltx
new file mode 100644
index 0000000..1366ec4
--- /dev/null
+++ b/prebuilt/XCU200/XCU200_C1_RDIMM_2R_x8.ltx
@@ -0,0 +1,32 @@
+{
+ "ltx_root": {
+ "version": 4,
+ "minor": 0,
+ "ltx_data": [
+ {
+ "name": "EDA_PROBESET",
+ "active": true,
+ "debug_cores": [
+ {
+ "type": "XSDB_V3",
+ "name": "dbg_hub",
+ "spec": "labtools_xsdbm_v3",
+ "clk_input_freq_hz": "41670836"
+ },
+ {
+ "type": "XSDBS_V2",
+ "name": "phy_ddr4_i",
+ "spec": "labtools_xsdbslavelib_v2",
+ "ipName": "DDR4_SDRAM",
+ "core_location": {
+ "user_chain": 1,
+ "slave_index": 0,
+ "bscan_switch_index": 0
+ },
+ "uuid": "A4798F5A1DC8569B9C8CB73395566903"
+ }
+ ]
+ }
+ ]
+ }
+} \ No newline at end of file
diff --git a/prebuilt/XCU200/XCU200_C1_UDIMM_1R_x8.bit b/prebuilt/XCU200/XCU200_C1_UDIMM_1R_x8.bit
new file mode 100644
index 0000000..2a1c951
--- /dev/null
+++ b/prebuilt/XCU200/XCU200_C1_UDIMM_1R_x8.bit
Binary files differ
diff --git a/prebuilt/XCU200/XCU200_C1_UDIMM_1R_x8.ltx b/prebuilt/XCU200/XCU200_C1_UDIMM_1R_x8.ltx
new file mode 100644
index 0000000..1366ec4
--- /dev/null
+++ b/prebuilt/XCU200/XCU200_C1_UDIMM_1R_x8.ltx
@@ -0,0 +1,32 @@
+{
+ "ltx_root": {
+ "version": 4,
+ "minor": 0,
+ "ltx_data": [
+ {
+ "name": "EDA_PROBESET",
+ "active": true,
+ "debug_cores": [
+ {
+ "type": "XSDB_V3",
+ "name": "dbg_hub",
+ "spec": "labtools_xsdbm_v3",
+ "clk_input_freq_hz": "41670836"
+ },
+ {
+ "type": "XSDBS_V2",
+ "name": "phy_ddr4_i",
+ "spec": "labtools_xsdbslavelib_v2",
+ "ipName": "DDR4_SDRAM",
+ "core_location": {
+ "user_chain": 1,
+ "slave_index": 0,
+ "bscan_switch_index": 0
+ },
+ "uuid": "A4798F5A1DC8569B9C8CB73395566903"
+ }
+ ]
+ }
+ ]
+ }
+} \ No newline at end of file
diff --git a/prebuilt/XCU200/XCU200_C1_UDIMM_2R_x8.bit b/prebuilt/XCU200/XCU200_C1_UDIMM_2R_x8.bit
new file mode 100644
index 0000000..f5c9747
--- /dev/null
+++ b/prebuilt/XCU200/XCU200_C1_UDIMM_2R_x8.bit
Binary files differ
diff --git a/prebuilt/XCU200/XCU200_C1_UDIMM_2R_x8.ltx b/prebuilt/XCU200/XCU200_C1_UDIMM_2R_x8.ltx
new file mode 100644
index 0000000..1366ec4
--- /dev/null
+++ b/prebuilt/XCU200/XCU200_C1_UDIMM_2R_x8.ltx
@@ -0,0 +1,32 @@
+{
+ "ltx_root": {
+ "version": 4,
+ "minor": 0,
+ "ltx_data": [
+ {
+ "name": "EDA_PROBESET",
+ "active": true,
+ "debug_cores": [
+ {
+ "type": "XSDB_V3",
+ "name": "dbg_hub",
+ "spec": "labtools_xsdbm_v3",
+ "clk_input_freq_hz": "41670836"
+ },
+ {
+ "type": "XSDBS_V2",
+ "name": "phy_ddr4_i",
+ "spec": "labtools_xsdbslavelib_v2",
+ "ipName": "DDR4_SDRAM",
+ "core_location": {
+ "user_chain": 1,
+ "slave_index": 0,
+ "bscan_switch_index": 0
+ },
+ "uuid": "A4798F5A1DC8569B9C8CB73395566903"
+ }
+ ]
+ }
+ ]
+ }
+} \ No newline at end of file
diff --git a/prebuilt/XCU200/XCU200_C2_RDIMM_1R_x4.bit b/prebuilt/XCU200/XCU200_C2_RDIMM_1R_x4.bit
new file mode 100644
index 0000000..7735816
--- /dev/null
+++ b/prebuilt/XCU200/XCU200_C2_RDIMM_1R_x4.bit
Binary files differ
diff --git a/prebuilt/XCU200/XCU200_C2_RDIMM_1R_x4.ltx b/prebuilt/XCU200/XCU200_C2_RDIMM_1R_x4.ltx
new file mode 100644
index 0000000..1366ec4
--- /dev/null
+++ b/prebuilt/XCU200/XCU200_C2_RDIMM_1R_x4.ltx
@@ -0,0 +1,32 @@
+{
+ "ltx_root": {
+ "version": 4,
+ "minor": 0,
+ "ltx_data": [
+ {
+ "name": "EDA_PROBESET",
+ "active": true,
+ "debug_cores": [
+ {
+ "type": "XSDB_V3",
+ "name": "dbg_hub",
+ "spec": "labtools_xsdbm_v3",
+ "clk_input_freq_hz": "41670836"
+ },
+ {
+ "type": "XSDBS_V2",
+ "name": "phy_ddr4_i",
+ "spec": "labtools_xsdbslavelib_v2",
+ "ipName": "DDR4_SDRAM",
+ "core_location": {
+ "user_chain": 1,
+ "slave_index": 0,
+ "bscan_switch_index": 0
+ },
+ "uuid": "A4798F5A1DC8569B9C8CB73395566903"
+ }
+ ]
+ }
+ ]
+ }
+} \ No newline at end of file
diff --git a/prebuilt/XCU200/XCU200_C3_RDIMM_1R_x4.bit b/prebuilt/XCU200/XCU200_C3_RDIMM_1R_x4.bit
new file mode 100644
index 0000000..ea340ed
--- /dev/null
+++ b/prebuilt/XCU200/XCU200_C3_RDIMM_1R_x4.bit
Binary files differ
diff --git a/prebuilt/XCU200/XCU200_C3_RDIMM_1R_x4.ltx b/prebuilt/XCU200/XCU200_C3_RDIMM_1R_x4.ltx
new file mode 100644
index 0000000..1366ec4
--- /dev/null
+++ b/prebuilt/XCU200/XCU200_C3_RDIMM_1R_x4.ltx
@@ -0,0 +1,32 @@
+{
+ "ltx_root": {
+ "version": 4,
+ "minor": 0,
+ "ltx_data": [
+ {
+ "name": "EDA_PROBESET",
+ "active": true,
+ "debug_cores": [
+ {
+ "type": "XSDB_V3",
+ "name": "dbg_hub",
+ "spec": "labtools_xsdbm_v3",
+ "clk_input_freq_hz": "41670836"
+ },
+ {
+ "type": "XSDBS_V2",
+ "name": "phy_ddr4_i",
+ "spec": "labtools_xsdbslavelib_v2",
+ "ipName": "DDR4_SDRAM",
+ "core_location": {
+ "user_chain": 1,
+ "slave_index": 0,
+ "bscan_switch_index": 0
+ },
+ "uuid": "A4798F5A1DC8569B9C8CB73395566903"
+ }
+ ]
+ }
+ ]
+ }
+} \ No newline at end of file
diff --git a/prebuilt/XUPP3R/XUPP3R_C1_RDIMM_1R_x4.bit b/prebuilt/XUPP3R/XUPP3R_C1_RDIMM_1R_x4.bit
new file mode 100644
index 0000000..33a5c21
--- /dev/null
+++ b/prebuilt/XUPP3R/XUPP3R_C1_RDIMM_1R_x4.bit
Binary files differ
diff --git a/prebuilt/XUPP3R/XUPP3R_C1_RDIMM_1R_x4.ltx b/prebuilt/XUPP3R/XUPP3R_C1_RDIMM_1R_x4.ltx
new file mode 100644
index 0000000..8bd3f56
--- /dev/null
+++ b/prebuilt/XUPP3R/XUPP3R_C1_RDIMM_1R_x4.ltx
@@ -0,0 +1,4 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<probeData version="2" minor="2">
+ <probeset name="EDA_PROBESET" active="true"/>
+</probeData>
diff --git a/prebuilt/XUPP3R/XUPP3R_C1_RDIMM_2R_x8.bit b/prebuilt/XUPP3R/XUPP3R_C1_RDIMM_2R_x8.bit
new file mode 100644
index 0000000..d2ae932
--- /dev/null
+++ b/prebuilt/XUPP3R/XUPP3R_C1_RDIMM_2R_x8.bit
Binary files differ
diff --git a/prebuilt/XUPP3R/XUPP3R_C1_RDIMM_2R_x8.ltx b/prebuilt/XUPP3R/XUPP3R_C1_RDIMM_2R_x8.ltx
new file mode 100644
index 0000000..8bd3f56
--- /dev/null
+++ b/prebuilt/XUPP3R/XUPP3R_C1_RDIMM_2R_x8.ltx
@@ -0,0 +1,4 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<probeData version="2" minor="2">
+ <probeset name="EDA_PROBESET" active="true"/>
+</probeData>
diff --git a/prebuilt/XUPP3R/XUPP3R_C1_UDIMM_1R_x8.bit b/prebuilt/XUPP3R/XUPP3R_C1_UDIMM_1R_x8.bit
new file mode 100644
index 0000000..c9b2995
--- /dev/null
+++ b/prebuilt/XUPP3R/XUPP3R_C1_UDIMM_1R_x8.bit
Binary files differ
diff --git a/prebuilt/XUPP3R/XUPP3R_C1_UDIMM_1R_x8.ltx b/prebuilt/XUPP3R/XUPP3R_C1_UDIMM_1R_x8.ltx
new file mode 100644
index 0000000..8bd3f56
--- /dev/null
+++ b/prebuilt/XUPP3R/XUPP3R_C1_UDIMM_1R_x8.ltx
@@ -0,0 +1,4 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<probeData version="2" minor="2">
+ <probeset name="EDA_PROBESET" active="true"/>
+</probeData>
diff --git a/prebuilt/XUPVVH/XUPVVH_C1_RDIMM_1R_x4.bit b/prebuilt/XUPVVH/XUPVVH_C1_RDIMM_1R_x4.bit
new file mode 100644
index 0000000..390e631
--- /dev/null
+++ b/prebuilt/XUPVVH/XUPVVH_C1_RDIMM_1R_x4.bit
Binary files differ
diff --git a/prebuilt/XUPVVH/XUPVVH_C1_RDIMM_1R_x4.ltx b/prebuilt/XUPVVH/XUPVVH_C1_RDIMM_1R_x4.ltx
new file mode 100644
index 0000000..3afbade
--- /dev/null
+++ b/prebuilt/XUPVVH/XUPVVH_C1_RDIMM_1R_x4.ltx
@@ -0,0 +1,32 @@
+{
+ "ltx_root": {
+ "version": 4,
+ "minor": 0,
+ "ltx_data": [
+ {
+ "name": "EDA_PROBESET",
+ "active": true,
+ "debug_cores": [
+ {
+ "type": "XSDB_V3",
+ "name": "dbg_hub",
+ "spec": "labtools_xsdbm_v3",
+ "clk_input_freq_hz": "41666666"
+ },
+ {
+ "type": "XSDBS_V2",
+ "name": "phy_ddr4_i",
+ "spec": "labtools_xsdbslavelib_v2",
+ "ipName": "DDR4_SDRAM",
+ "core_location": {
+ "user_chain": 1,
+ "slave_index": 0,
+ "bscan_switch_index": 0
+ },
+ "uuid": "A4798F5A1DC8569B9C8CB73395566903"
+ }
+ ]
+ }
+ ]
+ }
+} \ No newline at end of file
diff --git a/prebuilt/XUSP3S/XUSP3S_C1_SODIMM_1R_x8.bit b/prebuilt/XUSP3S/XUSP3S_C1_SODIMM_1R_x8.bit
new file mode 100644
index 0000000..0e7541e
--- /dev/null
+++ b/prebuilt/XUSP3S/XUSP3S_C1_SODIMM_1R_x8.bit
Binary files differ
diff --git a/prebuilt/XUSP3S/XUSP3S_C1_SODIMM_1R_x8.ltx b/prebuilt/XUSP3S/XUSP3S_C1_SODIMM_1R_x8.ltx
new file mode 100644
index 0000000..6e1ee5f
--- /dev/null
+++ b/prebuilt/XUSP3S/XUSP3S_C1_SODIMM_1R_x8.ltx
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<probeData version="2" minor="2">
+ <probeset name="EDA_PROBESET" active="true">
+ <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+ <probeOptions Id="DebugProbeParams">
+ <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+ <Option Id="CORE_LOCATION" value="1:1"/>
+ <Option Id="CORE_UUID" value="00000000000000000000000000000000"/>
+ <Option Id="HUB_CLK_INPUT_FREQ_HZ" value="41666666"/>
+ <Option Id="HW_ILA" value="u_ila_0"/>
+ <Option Id="PROBE_PORT" value="0"/>
+ <Option Id="PROBE_PORT_BITS" value="0"/>
+ <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+ </probeOptions>
+ <nets>
+ <net name="frontend/maint_ctrl/aref_switch_r"/>
+ </nets>
+ </probe>
+ </probeset>
+</probeData>
diff --git a/prebuilt/XUSP3S/XUSP3S_C2_SODIMM_1R_x8.bit b/prebuilt/XUSP3S/XUSP3S_C2_SODIMM_1R_x8.bit
new file mode 100644
index 0000000..6c9750a
--- /dev/null
+++ b/prebuilt/XUSP3S/XUSP3S_C2_SODIMM_1R_x8.bit
Binary files differ
diff --git a/prebuilt/XUSP3S/XUSP3S_C2_SODIMM_1R_x8.ltx b/prebuilt/XUSP3S/XUSP3S_C2_SODIMM_1R_x8.ltx
new file mode 100644
index 0000000..6e1ee5f
--- /dev/null
+++ b/prebuilt/XUSP3S/XUSP3S_C2_SODIMM_1R_x8.ltx
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<probeData version="2" minor="2">
+ <probeset name="EDA_PROBESET" active="true">
+ <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+ <probeOptions Id="DebugProbeParams">
+ <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+ <Option Id="CORE_LOCATION" value="1:1"/>
+ <Option Id="CORE_UUID" value="00000000000000000000000000000000"/>
+ <Option Id="HUB_CLK_INPUT_FREQ_HZ" value="41666666"/>
+ <Option Id="HW_ILA" value="u_ila_0"/>
+ <Option Id="PROBE_PORT" value="0"/>
+ <Option Id="PROBE_PORT_BITS" value="0"/>
+ <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+ </probeOptions>
+ <nets>
+ <net name="frontend/maint_ctrl/aref_switch_r"/>
+ </nets>
+ </probe>
+ </probeset>
+</probeData>
diff --git a/prebuilt/programFPGA.sh b/prebuilt/programFPGA.sh
new file mode 100755
index 0000000..f3785e3
--- /dev/null
+++ b/prebuilt/programFPGA.sh
@@ -0,0 +1,65 @@
+#!/bin/bash
+
+params_list="board slot dimm_type rank DQ"
+
+allowed_board="XCU200 XUSP3S XUPP3R XUPVVH"
+allowed_slot="C1 C2 C3 C4"
+allowed_dimm_type="UDIMM RDIMM SODIMM"
+allowed_rank="1R 2R"
+allowed_DQ="x4 x8 x16"
+
+board=${1}
+slot=${2}
+dimm_type=${3}
+rank=${4}
+DQ=${5}
+
+# x16 and x8 bitstreams are interchangeable
+if [[ ${DQ} == "x16" ]];
+then
+ DQ="x8"
+fi
+
+function contains()
+{
+ token=${1}
+ list=${2}
+ for _token in ${list};
+ do
+ if [ "${_token}" == "${token}" ];
+ then
+ return 1
+ fi
+ done
+ return 0
+}
+
+input_OK=true
+for param in ${params_list};
+do
+ list_name=allowed_${param}
+
+ if contains ${!param} "${!list_name}";
+ then
+ echo "Unrecognized ${param} \"${!param}\", supported values: ${!list_name}"
+ input_OK=false
+ fi
+done
+if ! ${input_OK};
+then
+ exit -1
+fi
+
+board_id=0
+
+bitfile_name=${board}/${board}_${slot}_${dimm_type}_${rank}_${DQ}.bit
+probesfile_name=${board}/${board}_${slot}_${dimm_type}_${rank}_${DQ}.ltx
+
+if [ -z "$VIVADO_EXEC" ]
+then
+ echo "Please assign vivado executable's path to VIVADO_EXEC variable first!"
+else
+ echo "Trying to program the board with the prebuilt files ${bitfile_name}..."
+ $VIVADO_EXEC -mode tcl -source $( dirname "${BASH_SOURCE[0]}")/programFPGA.tcl -nolog -nojournal -tclargs ${bitfile_name} ${probesfile_name}
+ echo "Done programming the board!"
+fi
diff --git a/prebuilt/programFPGA.tcl b/prebuilt/programFPGA.tcl
new file mode 100644
index 0000000..4aa35a4
--- /dev/null
+++ b/prebuilt/programFPGA.tcl
@@ -0,0 +1,31 @@
+if { $argc != 2 } {
+ puts "Incorrect number of arguments. Expected BIT_FILE and PROBES_FILE."
+ exit 0
+}
+
+set BIT_FILE [lindex $argv 0]
+set PROBES_FILE [lindex $argv 1]
+
+open_hw
+connect_hw_server -url localhost:3121
+current_hw_target [get_hw_targets *]
+set_property PARAM.FREQUENCY 15000000 [get_hw_targets *]
+open_hw_target
+
+set script_path [ file dirname [ file normalize [ info script ] ] ]
+puts $script_path
+
+set_property PROGRAM.FILE "${BIT_FILE}" [get_hw_devices *]
+set_property PROBES.FILE "${PROBES_FILE}" [get_hw_devices *]
+
+program_hw_devices [lindex [get_hw_devices] 0]
+#get_property REGISTER.IR.BIT5_DONE [lindex [get_hw_devices] 0]
+
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices *] 0]
+refresh_hw_mig [lindex [get_hw_migs]]
+report_hw_mig [lindex [get_hw_migs]]
+
+close_hw_target
+disconnect_hw_server
+close_hw
+exit