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| author | Ataberk <olgunataberk@gmail.com> | 2022-09-25 17:22:03 +0200 |
|---|---|---|
| committer | Ataberk <olgunataberk@gmail.com> | 2022-09-25 17:22:03 +0200 |
| commit | dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f (patch) | |
| tree | b47203aa281bdd959def4451c84d310cd9cf2e12 /projects/U200/U200.ip_user_files/sim_scripts | |
| download | dram-bender-dc0b3db1b4f1895a07e5fe280ee3790e87f97b9f.tar.gz | |
Initial commit
Diffstat (limited to 'projects/U200/U200.ip_user_files/sim_scripts')
904 files changed, 69709 insertions, 0 deletions
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/README.txt new file mode 100644 index 0000000..5acdd2f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/README.txt new file mode 100644 index 0000000..e96a5fb --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:22:43 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./axis_clock_converter.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './axis_clock_converter.sh' script. + +./axis_clock_converter.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./axis_clock_converter.sh -noclean_files + +For more information on the script, please type './axis_clock_converter.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/axis_clock_converter.sh b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/axis_clock_converter.sh new file mode 100755 index 0000000..1693801 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/axis_clock_converter.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : axis_clock_converter.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:22:43 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: axis_clock_converter.sh [-help] +# usage: axis_clock_converter.sh [-lib_map_path] +# usage: axis_clock_converter.sh [-noclean_files] +# usage: axis_clock_converter.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'axis_clock_converter.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: axis_clock_converter.sh [-help]\n\ +Usage: axis_clock_converter.sh [-lib_map_path]\n\ +Usage: axis_clock_converter.sh [-reset_run]\n\ +Usage: axis_clock_converter.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/axis_clock_converter.udo b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/axis_clock_converter.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/axis_clock_converter.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/compile.do new file mode 100644 index 0000000..0b13d95 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/compile.do @@ -0,0 +1,46 @@ +vlib work +vlib activehdl + +vlib activehdl/xilinx_vip +vlib activehdl/xpm +vlib activehdl/axis_infrastructure_v1_1_0 +vlib activehdl/axis_clock_converter_v1_1_23 +vlib activehdl/xil_defaultlib + +vmap xilinx_vip activehdl/xilinx_vip +vmap xpm activehdl/xpm +vmap axis_infrastructure_v1_1_0 activehdl/axis_infrastructure_v1_1_0 +vmap axis_clock_converter_v1_1_23 activehdl/axis_clock_converter_v1_1_23 +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work axis_infrastructure_v1_1_0 -v2k5 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \ + +vlog -work axis_clock_converter_v1_1_23 -v2k5 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/file_info.txt new file mode 100644 index 0000000..4607b03 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/file_info.txt @@ -0,0 +1,17 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +clk_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +rst_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_23,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/simulate.do new file mode 100644 index 0000000..8144d45 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+axis_clock_converter -L xilinx_vip -L xpm -L axis_infrastructure_v1_1_0 -L axis_clock_converter_v1_1_23 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.axis_clock_converter xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {axis_clock_converter.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/README.txt new file mode 100644 index 0000000..348b315 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:22:43 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./axis_clock_converter.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './axis_clock_converter.sh' script. + +./axis_clock_converter.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./axis_clock_converter.sh -noclean_files + +For more information on the script, please type './axis_clock_converter.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/axis_clock_converter.sh b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/axis_clock_converter.sh new file mode 100755 index 0000000..634ad59 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/axis_clock_converter.sh @@ -0,0 +1,178 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : axis_clock_converter.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:22:43 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: axis_clock_converter.sh [-help] +# usage: axis_clock_converter.sh [-lib_map_path] +# usage: axis_clock_converter.sh [-noclean_files] +# usage: axis_clock_converter.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'axis_clock_converter.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm axis_infrastructure_v1_1_0 axis_clock_converter_v1_1_23 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.axis_clock_converter \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../ipstatic/hdl" \ + +incdir+"../../../ipstatic/hdl" \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: axis_clock_converter.sh [-help]\n\ +Usage: axis_clock_converter.sh [-lib_map_path]\n\ +Usage: axis_clock_converter.sh [-reset_run]\n\ +Usage: axis_clock_converter.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/file_info.txt new file mode 100644 index 0000000..9f6127d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/file_info.txt @@ -0,0 +1,17 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +clk_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +rst_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_23,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/run.f new file mode 100644 index 0000000..234ef29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/ies/run.f @@ -0,0 +1,32 @@ +-makelib ies_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/axis_infrastructure_v1_1_0 \ + "../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \ +-endlib +-makelib ies_lib/axis_clock_converter_v1_1_23 \ + "../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/README.txt new file mode 100644 index 0000000..e96a5fb --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:22:43 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./axis_clock_converter.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './axis_clock_converter.sh' script. + +./axis_clock_converter.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./axis_clock_converter.sh -noclean_files + +For more information on the script, please type './axis_clock_converter.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/axis_clock_converter.sh b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/axis_clock_converter.sh new file mode 100755 index 0000000..5e3eaa9 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/axis_clock_converter.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : axis_clock_converter.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:22:43 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: axis_clock_converter.sh [-help] +# usage: axis_clock_converter.sh [-lib_map_path] +# usage: axis_clock_converter.sh [-noclean_files] +# usage: axis_clock_converter.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'axis_clock_converter.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: axis_clock_converter.sh [-help]\n\ +Usage: axis_clock_converter.sh [-lib_map_path]\n\ +Usage: axis_clock_converter.sh [-reset_run]\n\ +Usage: axis_clock_converter.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/axis_clock_converter.udo b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/axis_clock_converter.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/axis_clock_converter.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/compile.do new file mode 100644 index 0000000..b58f682 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/compile.do @@ -0,0 +1,46 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xilinx_vip +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/axis_infrastructure_v1_1_0 +vlib modelsim_lib/msim/axis_clock_converter_v1_1_23 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xilinx_vip modelsim_lib/msim/xilinx_vip +vmap xpm modelsim_lib/msim/xpm +vmap axis_infrastructure_v1_1_0 modelsim_lib/msim/axis_infrastructure_v1_1_0 +vmap axis_clock_converter_v1_1_23 modelsim_lib/msim/axis_clock_converter_v1_1_23 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work axis_infrastructure_v1_1_0 -64 -incr "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \ + +vlog -work axis_clock_converter_v1_1_23 -64 -incr "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/file_info.txt new file mode 100644 index 0000000..4607b03 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/file_info.txt @@ -0,0 +1,17 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +clk_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +rst_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_23,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/simulate.do new file mode 100644 index 0000000..7b1f2ad --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -L xilinx_vip -L xpm -L axis_infrastructure_v1_1_0 -L axis_clock_converter_v1_1_23 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.axis_clock_converter xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {axis_clock_converter.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/README.txt new file mode 100644 index 0000000..e96a5fb --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:22:43 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./axis_clock_converter.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './axis_clock_converter.sh' script. + +./axis_clock_converter.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./axis_clock_converter.sh -noclean_files + +For more information on the script, please type './axis_clock_converter.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/axis_clock_converter.sh b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/axis_clock_converter.sh new file mode 100755 index 0000000..5e727c4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/axis_clock_converter.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : axis_clock_converter.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:22:43 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: axis_clock_converter.sh [-help] +# usage: axis_clock_converter.sh [-lib_map_path] +# usage: axis_clock_converter.sh [-noclean_files] +# usage: axis_clock_converter.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'axis_clock_converter.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: axis_clock_converter.sh [-help]\n\ +Usage: axis_clock_converter.sh [-lib_map_path]\n\ +Usage: axis_clock_converter.sh [-reset_run]\n\ +Usage: axis_clock_converter.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/axis_clock_converter.udo b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/axis_clock_converter.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/axis_clock_converter.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/compile.do new file mode 100644 index 0000000..99047ec --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/compile.do @@ -0,0 +1,46 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xilinx_vip +vlib questa_lib/msim/xpm +vlib questa_lib/msim/axis_infrastructure_v1_1_0 +vlib questa_lib/msim/axis_clock_converter_v1_1_23 +vlib questa_lib/msim/xil_defaultlib + +vmap xilinx_vip questa_lib/msim/xilinx_vip +vmap xpm questa_lib/msim/xpm +vmap axis_infrastructure_v1_1_0 questa_lib/msim/axis_infrastructure_v1_1_0 +vmap axis_clock_converter_v1_1_23 questa_lib/msim/axis_clock_converter_v1_1_23 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work axis_infrastructure_v1_1_0 -64 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \ + +vlog -work axis_clock_converter_v1_1_23 -64 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/elaborate.do new file mode 100644 index 0000000..4f6cea8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L axis_infrastructure_v1_1_0 -L axis_clock_converter_v1_1_23 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.axis_clock_converter xil_defaultlib.glbl -o axis_clock_converter_opt diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/file_info.txt new file mode 100644 index 0000000..4607b03 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/file_info.txt @@ -0,0 +1,17 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +clk_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +rst_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_23,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/simulate.do new file mode 100644 index 0000000..744838d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -lib xil_defaultlib axis_clock_converter_opt + +do {wave.do} + +view wave +view structure +view signals + +do {axis_clock_converter.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/README.txt new file mode 100644 index 0000000..e96a5fb --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:22:43 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./axis_clock_converter.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './axis_clock_converter.sh' script. + +./axis_clock_converter.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./axis_clock_converter.sh -noclean_files + +For more information on the script, please type './axis_clock_converter.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/axis_clock_converter.sh b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/axis_clock_converter.sh new file mode 100755 index 0000000..9e8c90c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/axis_clock_converter.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : axis_clock_converter.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:22:43 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: axis_clock_converter.sh [-help] +# usage: axis_clock_converter.sh [-lib_map_path] +# usage: axis_clock_converter.sh [-noclean_files] +# usage: axis_clock_converter.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'axis_clock_converter.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: axis_clock_converter.sh [-help]\n\ +Usage: axis_clock_converter.sh [-lib_map_path]\n\ +Usage: axis_clock_converter.sh [-reset_run]\n\ +Usage: axis_clock_converter.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/axis_clock_converter.udo b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/axis_clock_converter.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/axis_clock_converter.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/compile.do new file mode 100644 index 0000000..96d4454 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/compile.do @@ -0,0 +1,46 @@ +vlib work +vlib riviera + +vlib riviera/xilinx_vip +vlib riviera/xpm +vlib riviera/axis_infrastructure_v1_1_0 +vlib riviera/axis_clock_converter_v1_1_23 +vlib riviera/xil_defaultlib + +vmap xilinx_vip riviera/xilinx_vip +vmap xpm riviera/xpm +vmap axis_infrastructure_v1_1_0 riviera/axis_infrastructure_v1_1_0 +vmap axis_clock_converter_v1_1_23 riviera/axis_clock_converter_v1_1_23 +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work axis_infrastructure_v1_1_0 -v2k5 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \ + +vlog -work axis_clock_converter_v1_1_23 -v2k5 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/hdl" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/file_info.txt new file mode 100644 index 0000000..4607b03 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/file_info.txt @@ -0,0 +1,17 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +clk_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +rst_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_23,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v,incdir="../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/simulate.do new file mode 100644 index 0000000..8144d45 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+axis_clock_converter -L xilinx_vip -L xpm -L axis_infrastructure_v1_1_0 -L axis_clock_converter_v1_1_23 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.axis_clock_converter xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {axis_clock_converter.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/README.txt new file mode 100644 index 0000000..e96a5fb --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:22:43 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./axis_clock_converter.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './axis_clock_converter.sh' script. + +./axis_clock_converter.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./axis_clock_converter.sh -noclean_files + +For more information on the script, please type './axis_clock_converter.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/axis_clock_converter.sh b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/axis_clock_converter.sh new file mode 100755 index 0000000..d4759a2 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/axis_clock_converter.sh @@ -0,0 +1,251 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : axis_clock_converter.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:22:43 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: axis_clock_converter.sh [-help] +# usage: axis_clock_converter.sh [-lib_map_path] +# usage: axis_clock_converter.sh [-noclean_files] +# usage: axis_clock_converter.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'axis_clock_converter.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xilinx_vip xpm axis_infrastructure_v1_1_0 axis_clock_converter_v1_1_23 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ipstatic/hdl" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ipstatic/hdl" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work axis_infrastructure_v1_1_0 $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/hdl" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work axis_clock_converter_v1_1_23 $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/hdl" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/hdl" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.axis_clock_converter xil_defaultlib.glbl -o axis_clock_converter_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./axis_clock_converter_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key axis_clock_converter_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc axis_clock_converter_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: axis_clock_converter.sh [-help]\n\ +Usage: axis_clock_converter.sh [-lib_map_path]\n\ +Usage: axis_clock_converter.sh [-reset_run]\n\ +Usage: axis_clock_converter.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/file_info.txt new file mode 100644 index 0000000..9f6127d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/file_info.txt @@ -0,0 +1,17 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +clk_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +rst_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_23,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/README.txt new file mode 100644 index 0000000..348b315 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:22:43 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./axis_clock_converter.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './axis_clock_converter.sh' script. + +./axis_clock_converter.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./axis_clock_converter.sh -noclean_files + +For more information on the script, please type './axis_clock_converter.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/axis_clock_converter.sh b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/axis_clock_converter.sh new file mode 100755 index 0000000..f0d0536 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/axis_clock_converter.sh @@ -0,0 +1,178 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : axis_clock_converter.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:22:43 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: axis_clock_converter.sh [-help] +# usage: axis_clock_converter.sh [-lib_map_path] +# usage: axis_clock_converter.sh [-noclean_files] +# usage: axis_clock_converter.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'axis_clock_converter.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm axis_infrastructure_v1_1_0 axis_clock_converter_v1_1_23 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.axis_clock_converter \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../ipstatic/hdl" \ + +incdir+"../../../ipstatic/hdl" \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: axis_clock_converter.sh [-help]\n\ +Usage: axis_clock_converter.sh [-lib_map_path]\n\ +Usage: axis_clock_converter.sh [-reset_run]\n\ +Usage: axis_clock_converter.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/file_info.txt new file mode 100644 index 0000000..9f6127d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/file_info.txt @@ -0,0 +1,17 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axi_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +clk_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +rst_vip_if.sv,systemverilog,xilinx_vip,../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_cdc.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_fifo.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_memory.sv,systemverilog,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_infrastructure_v1_1_vl_rfs.v,verilog,axis_infrastructure_v1_1_0,../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter_v1_1_vl_rfs.v,verilog,axis_clock_converter_v1_1_23,../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +axis_clock_converter.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/run.f new file mode 100644 index 0000000..d38b4ff --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xcelium/run.f @@ -0,0 +1,32 @@ +-makelib xcelium_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/axis_infrastructure_v1_1_0 \ + "../../../ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v" \ +-endlib +-makelib xcelium_lib/axis_clock_converter_v1_1_23 \ + "../../../ipstatic/hdl/axis_clock_converter_v1_1_vl_rfs.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/README.txt new file mode 100644 index 0000000..e96a5fb --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:22:43 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./axis_clock_converter.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './axis_clock_converter.sh' script. + +./axis_clock_converter.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./axis_clock_converter.sh -noclean_files + +For more information on the script, please type './axis_clock_converter.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/U200.smi new file mode 100644 index 0000000..f20b0a8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/U200.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2020.2 (64-bit) --> +<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 --> +<!-- --> +<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 18 2020 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcu200-fsgd2104-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/axis_clock_converter.sh b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/axis_clock_converter.sh new file mode 100755 index 0000000..181c27e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/axis_clock_converter.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : axis_clock_converter.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:22:43 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: axis_clock_converter.sh [-help] +# usage: axis_clock_converter.sh [-lib_map_path] +# usage: axis_clock_converter.sh [-noclean_files] +# usage: axis_clock_converter.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0 +xvlog_opts="--relax -L xdma_v4_1_8" + + +# Script info +echo -e "axis_clock_converter.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L axis_infrastructure_v1_1_0 -L axis_clock_converter_v1_1_23 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot axis_clock_converter xil_defaultlib.axis_clock_converter xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim axis_clock_converter -key {Behavioral:sim_1:Functional:axis_clock_converter} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=(xil_defaultlib) + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb axis_clock_converter.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./axis_clock_converter.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: axis_clock_converter.sh [-help]\n\ +Usage: axis_clock_converter.sh [-lib_map_path]\n\ +Usage: axis_clock_converter.sh [-reset_run]\n\ +Usage: axis_clock_converter.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/file_info.txt new file mode 100644 index 0000000..7914184 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/file_info.txt @@ -0,0 +1,2 @@ +axis_clock_converter.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v,incdir="$ref_dir/../../../ipstatic/hdl"incdir="../../../ipstatic/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_afa8.protoinst new file mode 100644 index 0000000..a0656b6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_afa8.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_afa8": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_ba6a.protoinst new file mode 100644 index 0000000..c42e1c4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/protoinst_files/bd_ba6a.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_ba6a": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/vlog.prj new file mode 100644 index 0000000..c8e0879 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/axis_clock_converter_1/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ipstatic/hdl" \ +"../../../../U200.srcs/sources_1/ip/axis_clock_converter_1/sim/axis_clock_converter.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/README.txt new file mode 100644 index 0000000..5acdd2f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/README.txt new file mode 100644 index 0000000..cbe0c3d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:22:57 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem.sh' script. + +./instr_blk_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem.sh -noclean_files + +For more information on the script, please type './instr_blk_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/compile.do new file mode 100644 index 0000000..b14c2e3 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/compile.do @@ -0,0 +1,41 @@ +vlib work +vlib activehdl + +vlib activehdl/xilinx_vip +vlib activehdl/xpm +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/xil_defaultlib + +vmap xilinx_vip activehdl/xilinx_vip +vmap xpm activehdl/xpm +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/file_info.txt new file mode 100644 index 0000000..9ed9f5f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/instr_blk_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/instr_blk_mem.sh new file mode 100755 index 0000000..d39e0a1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/instr_blk_mem.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : instr_blk_mem.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:22:57 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem.sh [-help] +# usage: instr_blk_mem.sh [-lib_map_path] +# usage: instr_blk_mem.sh [-noclean_files] +# usage: instr_blk_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem.sh [-help]\n\ +Usage: instr_blk_mem.sh [-lib_map_path]\n\ +Usage: instr_blk_mem.sh [-reset_run]\n\ +Usage: instr_blk_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/instr_blk_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/instr_blk_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/instr_blk_mem.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/simulate.do new file mode 100644 index 0000000..1602422 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+instr_blk_mem -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.instr_blk_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {instr_blk_mem.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/summary.log new file mode 100755 index 0000000..5094079 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [2048] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [4] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 7.524303 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/README.txt new file mode 100644 index 0000000..26d8f67 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:22:57 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem.sh' script. + +./instr_blk_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem.sh -noclean_files + +For more information on the script, please type './instr_blk_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/file_info.txt new file mode 100644 index 0000000..9ed9f5f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/instr_blk_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/instr_blk_mem.sh new file mode 100755 index 0000000..d7f5271 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/instr_blk_mem.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : instr_blk_mem.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:22:57 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem.sh [-help] +# usage: instr_blk_mem.sh [-lib_map_path] +# usage: instr_blk_mem.sh [-noclean_files] +# usage: instr_blk_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.instr_blk_mem \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem.sh [-help]\n\ +Usage: instr_blk_mem.sh [-lib_map_path]\n\ +Usage: instr_blk_mem.sh [-reset_run]\n\ +Usage: instr_blk_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/run.f new file mode 100644 index 0000000..377bea5 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/run.f @@ -0,0 +1,29 @@ +-makelib ies_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/summary.log new file mode 100755 index 0000000..5094079 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/ies/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [2048] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [4] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 7.524303 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/README.txt new file mode 100644 index 0000000..cbe0c3d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:22:57 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem.sh' script. + +./instr_blk_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem.sh -noclean_files + +For more information on the script, please type './instr_blk_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/compile.do new file mode 100644 index 0000000..41f1286 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/compile.do @@ -0,0 +1,41 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xilinx_vip +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xilinx_vip modelsim_lib/msim/xilinx_vip +vmap xpm modelsim_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/file_info.txt new file mode 100644 index 0000000..9ed9f5f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/instr_blk_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/instr_blk_mem.sh new file mode 100755 index 0000000..88dd8f6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/instr_blk_mem.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : instr_blk_mem.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:22:57 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem.sh [-help] +# usage: instr_blk_mem.sh [-lib_map_path] +# usage: instr_blk_mem.sh [-noclean_files] +# usage: instr_blk_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem.sh [-help]\n\ +Usage: instr_blk_mem.sh [-lib_map_path]\n\ +Usage: instr_blk_mem.sh [-reset_run]\n\ +Usage: instr_blk_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/instr_blk_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/instr_blk_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/instr_blk_mem.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/simulate.do new file mode 100644 index 0000000..9a42a0c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.instr_blk_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {instr_blk_mem.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/summary.log new file mode 100755 index 0000000..5094079 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [2048] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [4] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 7.524303 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/README.txt new file mode 100644 index 0000000..cbe0c3d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:22:57 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem.sh' script. + +./instr_blk_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem.sh -noclean_files + +For more information on the script, please type './instr_blk_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/compile.do new file mode 100644 index 0000000..94def16 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/compile.do @@ -0,0 +1,41 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xilinx_vip +vlib questa_lib/msim/xpm +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/xil_defaultlib + +vmap xilinx_vip questa_lib/msim/xilinx_vip +vmap xpm questa_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/elaborate.do new file mode 100644 index 0000000..417eabc --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.instr_blk_mem xil_defaultlib.glbl -o instr_blk_mem_opt diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/file_info.txt new file mode 100644 index 0000000..9ed9f5f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/instr_blk_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/instr_blk_mem.sh new file mode 100755 index 0000000..817277e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/instr_blk_mem.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : instr_blk_mem.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:22:57 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem.sh [-help] +# usage: instr_blk_mem.sh [-lib_map_path] +# usage: instr_blk_mem.sh [-noclean_files] +# usage: instr_blk_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem.sh [-help]\n\ +Usage: instr_blk_mem.sh [-lib_map_path]\n\ +Usage: instr_blk_mem.sh [-reset_run]\n\ +Usage: instr_blk_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/instr_blk_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/instr_blk_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/instr_blk_mem.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/simulate.do new file mode 100644 index 0000000..5832b28 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -lib xil_defaultlib instr_blk_mem_opt + +do {wave.do} + +view wave +view structure +view signals + +do {instr_blk_mem.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/summary.log new file mode 100755 index 0000000..5094079 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [2048] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [4] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 7.524303 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/README.txt new file mode 100644 index 0000000..cbe0c3d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:22:57 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem.sh' script. + +./instr_blk_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem.sh -noclean_files + +For more information on the script, please type './instr_blk_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/compile.do new file mode 100644 index 0000000..35e9fea --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/compile.do @@ -0,0 +1,41 @@ +vlib work +vlib riviera + +vlib riviera/xilinx_vip +vlib riviera/xpm +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/xil_defaultlib + +vmap xilinx_vip riviera/xilinx_vip +vmap xpm riviera/xpm +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/file_info.txt new file mode 100644 index 0000000..9ed9f5f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/instr_blk_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/instr_blk_mem.sh new file mode 100755 index 0000000..63c4a88 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/instr_blk_mem.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : instr_blk_mem.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:22:57 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem.sh [-help] +# usage: instr_blk_mem.sh [-lib_map_path] +# usage: instr_blk_mem.sh [-noclean_files] +# usage: instr_blk_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem.sh [-help]\n\ +Usage: instr_blk_mem.sh [-lib_map_path]\n\ +Usage: instr_blk_mem.sh [-reset_run]\n\ +Usage: instr_blk_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/instr_blk_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/instr_blk_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/instr_blk_mem.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/simulate.do new file mode 100644 index 0000000..1602422 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+instr_blk_mem -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.instr_blk_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {instr_blk_mem.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/summary.log new file mode 100755 index 0000000..5094079 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [2048] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [4] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 7.524303 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/README.txt new file mode 100644 index 0000000..cbe0c3d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:22:57 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem.sh' script. + +./instr_blk_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem.sh -noclean_files + +For more information on the script, please type './instr_blk_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/file_info.txt new file mode 100644 index 0000000..9ed9f5f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/instr_blk_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/instr_blk_mem.sh new file mode 100755 index 0000000..f0524d8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/instr_blk_mem.sh @@ -0,0 +1,247 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : instr_blk_mem.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:22:57 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem.sh [-help] +# usage: instr_blk_mem.sh [-lib_map_path] +# usage: instr_blk_mem.sh [-noclean_files] +# usage: instr_blk_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xpm $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.instr_blk_mem xil_defaultlib.glbl -o instr_blk_mem_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./instr_blk_mem_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key instr_blk_mem_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc instr_blk_mem_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem.sh [-help]\n\ +Usage: instr_blk_mem.sh [-lib_map_path]\n\ +Usage: instr_blk_mem.sh [-reset_run]\n\ +Usage: instr_blk_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/summary.log new file mode 100755 index 0000000..5094079 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/vcs/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [2048] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [4] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 7.524303 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/README.txt new file mode 100644 index 0000000..26d8f67 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:22:57 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem.sh' script. + +./instr_blk_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem.sh -noclean_files + +For more information on the script, please type './instr_blk_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/file_info.txt new file mode 100644 index 0000000..9ed9f5f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/instr_blk_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/instr_blk_mem.sh new file mode 100755 index 0000000..6863d0d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/instr_blk_mem.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : instr_blk_mem.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:22:57 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem.sh [-help] +# usage: instr_blk_mem.sh [-lib_map_path] +# usage: instr_blk_mem.sh [-noclean_files] +# usage: instr_blk_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.instr_blk_mem \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem.sh [-help]\n\ +Usage: instr_blk_mem.sh [-lib_map_path]\n\ +Usage: instr_blk_mem.sh [-reset_run]\n\ +Usage: instr_blk_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/run.f new file mode 100644 index 0000000..071771d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/run.f @@ -0,0 +1,29 @@ +-makelib xcelium_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/summary.log new file mode 100755 index 0000000..5094079 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xcelium/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [2048] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [4] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 7.524303 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/README.txt new file mode 100644 index 0000000..cbe0c3d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:22:57 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem.sh' script. + +./instr_blk_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem.sh -noclean_files + +For more information on the script, please type './instr_blk_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/U200.smi new file mode 100644 index 0000000..f20b0a8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/U200.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2020.2 (64-bit) --> +<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 --> +<!-- --> +<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 18 2020 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcu200-fsgd2104-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/file_info.txt new file mode 100644 index 0000000..0fd4037 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/file_info.txt @@ -0,0 +1,2 @@ +instr_blk_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/instr_blk_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/instr_blk_mem.sh new file mode 100755 index 0000000..aab8ed7 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/instr_blk_mem.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : instr_blk_mem.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:22:57 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem.sh [-help] +# usage: instr_blk_mem.sh [-lib_map_path] +# usage: instr_blk_mem.sh [-noclean_files] +# usage: instr_blk_mem.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0 +xvlog_opts="--relax -L xdma_v4_1_8" + + +# Script info +echo -e "instr_blk_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot instr_blk_mem xil_defaultlib.instr_blk_mem xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim instr_blk_mem -key {Behavioral:sim_1:Functional:instr_blk_mem} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb instr_blk_mem.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem.sh [-help]\n\ +Usage: instr_blk_mem.sh [-lib_map_path]\n\ +Usage: instr_blk_mem.sh [-reset_run]\n\ +Usage: instr_blk_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_afa8.protoinst new file mode 100644 index 0000000..a0656b6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_afa8.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_afa8": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_ba6a.protoinst new file mode 100644 index 0000000..c42e1c4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/protoinst_files/bd_ba6a.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_ba6a": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/summary.log new file mode 100755 index 0000000..5094079 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [2048] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [4] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 7.524303 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/vlog.prj new file mode 100644 index 0000000..6207c87 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../../U200.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/README.txt new file mode 100644 index 0000000..5acdd2f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/README.txt new file mode 100644 index 0000000..dc30976 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:09 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem_sim.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem_sim.sh' script. + +./instr_blk_mem_sim.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem_sim.sh -noclean_files + +For more information on the script, please type './instr_blk_mem_sim.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/compile.do new file mode 100644 index 0000000..6dccd0b --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/compile.do @@ -0,0 +1,41 @@ +vlib work +vlib activehdl + +vlib activehdl/xilinx_vip +vlib activehdl/xpm +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/xil_defaultlib + +vmap xilinx_vip activehdl/xilinx_vip +vmap xpm activehdl/xpm +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/file_info.txt new file mode 100644 index 0000000..cd1d040 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.mif 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b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : instr_blk_mem_sim.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:09 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem_sim.sh [-help] +# usage: instr_blk_mem_sim.sh [-lib_map_path] +# usage: instr_blk_mem_sim.sh [-noclean_files] +# usage: instr_blk_mem_sim.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem_sim.sh [-help]\n\ +Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\ +Usage: instr_blk_mem_sim.sh [-reset_run]\n\ +Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.udo b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/instr_blk_mem_sim.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simmem.coe b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simmem.coe new file mode 100755 index 0000000..90d215f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simmem.coe @@ -0,0 +1,398 @@ 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\ No newline at end of file diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simulate.do new file mode 100644 index 0000000..3af7c4b --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+instr_blk_mem_sim -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {instr_blk_mem_sim.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/summary.log new file mode 100755 index 0000000..db51362 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [2] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 4.238151 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/README.txt new file mode 100644 index 0000000..e9e84f9 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:09 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem_sim.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem_sim.sh' script. + +./instr_blk_mem_sim.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem_sim.sh -noclean_files + +For more information on the script, please type './instr_blk_mem_sim.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/file_info.txt new file mode 100644 index 0000000..cd1d040 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/instr_blk_mem_sim.mif b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/instr_blk_mem_sim.mif new file mode 100755 index 0000000..e9bd6fc --- /dev/null +++ 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+#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : instr_blk_mem_sim.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:09 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem_sim.sh [-help] +# usage: instr_blk_mem_sim.sh [-lib_map_path] +# usage: instr_blk_mem_sim.sh [-noclean_files] +# usage: instr_blk_mem_sim.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.instr_blk_mem_sim \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem_sim.sh [-help]\n\ +Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\ +Usage: instr_blk_mem_sim.sh [-reset_run]\n\ +Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/run.f new file mode 100644 index 0000000..a0a3c78 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/run.f @@ -0,0 +1,29 @@ +-makelib ies_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git 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\ No newline at end of file diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/summary.log new file mode 100755 index 0000000..db51362 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/ies/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [2] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 4.238151 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/README.txt new file mode 100644 index 0000000..dc30976 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:09 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem_sim.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem_sim.sh' script. + +./instr_blk_mem_sim.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem_sim.sh -noclean_files + +For more information on the script, please type './instr_blk_mem_sim.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/compile.do new file mode 100644 index 0000000..ae902a8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/compile.do @@ -0,0 +1,41 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xilinx_vip +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xilinx_vip modelsim_lib/msim/xilinx_vip +vmap xpm modelsim_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/file_info.txt new file mode 100644 index 0000000..cd1d040 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git 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file mode 100755 index 0000000..43115ec --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : instr_blk_mem_sim.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:09 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem_sim.sh [-help] +# usage: instr_blk_mem_sim.sh [-lib_map_path] +# usage: instr_blk_mem_sim.sh [-noclean_files] +# usage: instr_blk_mem_sim.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem_sim.sh [-help]\n\ +Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\ +Usage: instr_blk_mem_sim.sh [-reset_run]\n\ +Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.udo b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/instr_blk_mem_sim.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simmem.coe b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simmem.coe new file mode 100755 index 0000000..90d215f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simmem.coe @@ -0,0 +1,398 @@ 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\ No newline at end of file diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simulate.do new file mode 100644 index 0000000..aff26ea --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {instr_blk_mem_sim.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/summary.log new file mode 100755 index 0000000..db51362 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [2] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 4.238151 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/README.txt new file mode 100644 index 0000000..dc30976 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:09 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem_sim.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem_sim.sh' script. + +./instr_blk_mem_sim.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem_sim.sh -noclean_files + +For more information on the script, please type './instr_blk_mem_sim.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/compile.do new file mode 100644 index 0000000..57c64ef --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/compile.do @@ -0,0 +1,41 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xilinx_vip +vlib questa_lib/msim/xpm +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/xil_defaultlib + +vmap xilinx_vip questa_lib/msim/xilinx_vip +vmap xpm questa_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/elaborate.do new file mode 100644 index 0000000..8c66a9a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl -o instr_blk_mem_sim_opt diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/file_info.txt new file mode 100644 index 0000000..cd1d040 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.mif b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.mif new file mode 100755 index 0000000..e9bd6fc --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.mif @@ -0,0 +1,396 @@ +0000000000000110000000000000000000000000100010000000000000000000 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elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:09 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem_sim.sh [-help] +# usage: instr_blk_mem_sim.sh [-lib_map_path] +# usage: instr_blk_mem_sim.sh [-noclean_files] +# usage: instr_blk_mem_sim.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem_sim.sh [-help]\n\ +Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\ +Usage: instr_blk_mem_sim.sh [-reset_run]\n\ +Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.udo b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/instr_blk_mem_sim.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simmem.coe b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simmem.coe new file mode 100755 index 0000000..90d215f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simmem.coe @@ -0,0 +1,398 @@ +memory_initialization_radix=2; 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\ No newline at end of file diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simulate.do new file mode 100644 index 0000000..1966060 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -lib xil_defaultlib instr_blk_mem_sim_opt + +do {wave.do} + +view wave +view structure +view signals + +do {instr_blk_mem_sim.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/summary.log new file mode 100755 index 0000000..db51362 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [2] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 4.238151 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/README.txt new file mode 100644 index 0000000..dc30976 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:09 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem_sim.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem_sim.sh' script. + +./instr_blk_mem_sim.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem_sim.sh -noclean_files + +For more information on the script, please type './instr_blk_mem_sim.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/compile.do new file mode 100644 index 0000000..983f077 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/compile.do @@ -0,0 +1,41 @@ +vlib work +vlib riviera + +vlib riviera/xilinx_vip +vlib riviera/xpm +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/xil_defaultlib + +vmap xilinx_vip riviera/xilinx_vip +vmap xpm riviera/xpm +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/file_info.txt new file mode 100644 index 0000000..cd1d040 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.mif b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.mif 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+#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : instr_blk_mem_sim.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:09 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem_sim.sh [-help] +# usage: instr_blk_mem_sim.sh [-lib_map_path] +# usage: instr_blk_mem_sim.sh [-noclean_files] +# usage: instr_blk_mem_sim.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem_sim.sh [-help]\n\ +Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\ +Usage: instr_blk_mem_sim.sh [-reset_run]\n\ +Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.udo b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/instr_blk_mem_sim.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simmem.coe b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simmem.coe new file mode 100755 index 0000000..90d215f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simmem.coe @@ -0,0 +1,398 @@ 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\ No newline at end of file diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simulate.do new file mode 100644 index 0000000..3af7c4b --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+instr_blk_mem_sim -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {instr_blk_mem_sim.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/summary.log new file mode 100755 index 0000000..db51362 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [2] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 4.238151 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/README.txt new file mode 100644 index 0000000..dc30976 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:09 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem_sim.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem_sim.sh' script. + +./instr_blk_mem_sim.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem_sim.sh -noclean_files + +For more information on the script, please type './instr_blk_mem_sim.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/file_info.txt new file mode 100644 index 0000000..cd1d040 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/instr_blk_mem_sim.mif b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/instr_blk_mem_sim.mif new file mode 100755 index 0000000..e9bd6fc --- /dev/null +++ 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+#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : instr_blk_mem_sim.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:09 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem_sim.sh [-help] +# usage: instr_blk_mem_sim.sh [-lib_map_path] +# usage: instr_blk_mem_sim.sh [-noclean_files] +# usage: instr_blk_mem_sim.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xpm $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl -o instr_blk_mem_sim_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./instr_blk_mem_sim_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key instr_blk_mem_sim_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc instr_blk_mem_sim_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem_sim.sh [-help]\n\ +Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\ +Usage: instr_blk_mem_sim.sh [-reset_run]\n\ +Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simmem.coe b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simmem.coe new file mode 100755 index 0000000..90d215f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simmem.coe @@ -0,0 +1,398 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0000000000000110000000000000000000000000100010000000000000000000, +0000000000000110000000000000000000000000101100000000000100000000, +0000000000000110000000000000000000000000000000000000000010000000, +0000000000000110000000000000000000000000000100000000000000010000, +0000000000000110000000000000000000000000001000000000000000010000, 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\ No newline at end of file diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/summary.log new file mode 100755 index 0000000..db51362 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/vcs/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [2] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 4.238151 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/README.txt new file mode 100644 index 0000000..e9e84f9 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:09 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem_sim.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem_sim.sh' script. + +./instr_blk_mem_sim.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem_sim.sh -noclean_files + +For more information on the script, please type './instr_blk_mem_sim.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/file_info.txt new file mode 100644 index 0000000..cd1d040 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/instr_blk_mem_sim.mif b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/instr_blk_mem_sim.mif new file mode 100755 index 0000000..e9bd6fc --- /dev/null +++ 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+#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : instr_blk_mem_sim.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:09 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem_sim.sh [-help] +# usage: instr_blk_mem_sim.sh [-lib_map_path] +# usage: instr_blk_mem_sim.sh [-noclean_files] +# usage: instr_blk_mem_sim.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'instr_blk_mem_sim.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.instr_blk_mem_sim \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem_sim.sh [-help]\n\ +Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\ +Usage: instr_blk_mem_sim.sh [-reset_run]\n\ +Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/run.f new file mode 100644 index 0000000..42c442c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/run.f @@ -0,0 +1,29 @@ +-makelib xcelium_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/simmem.coe b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/simmem.coe new file mode 100755 index 0000000..90d215f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/simmem.coe @@ -0,0 +1,398 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0000000000000110000000000000000000000000100010000000000000000000, +0000000000000110000000000000000000000000101100000000000100000000, +0000000000000110000000000000000000000000000000000000000010000000, +0000000000000110000000000000000000000000000100000000000000010000, +0000000000000110000000000000000000000000001000000000000000010000, +0001000000000000000000000000000000000000101000000000000000110000, +0100000000000011000000000000000000000000000000000000000000000011, +0001000000000001000000000000000000000000000100000000000000110000, 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\ No newline at end of file diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/summary.log new file mode 100755 index 0000000..db51362 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xcelium/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [2] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 4.238151 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/README.txt new file mode 100644 index 0000000..dc30976 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:09 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./instr_blk_mem_sim.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './instr_blk_mem_sim.sh' script. + +./instr_blk_mem_sim.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./instr_blk_mem_sim.sh -noclean_files + +For more information on the script, please type './instr_blk_mem_sim.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/U200.smi new file mode 100644 index 0000000..f20b0a8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/U200.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2020.2 (64-bit) --> +<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 --> +<!-- --> +<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 18 2020 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcu200-fsgd2104-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/file_info.txt new file mode 100644 index 0000000..2ecac04 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/file_info.txt @@ -0,0 +1,2 @@ +instr_blk_mem_sim.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/instr_blk_mem_sim.mif b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/instr_blk_mem_sim.mif new file mode 100755 index 0000000..e9bd6fc --- /dev/null +++ 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+#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : instr_blk_mem_sim.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:09 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: instr_blk_mem_sim.sh [-help] +# usage: instr_blk_mem_sim.sh [-lib_map_path] +# usage: instr_blk_mem_sim.sh [-noclean_files] +# usage: instr_blk_mem_sim.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0 +xvlog_opts="--relax -L xdma_v4_1_8" + + +# Script info +echo -e "instr_blk_mem_sim.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot instr_blk_mem_sim xil_defaultlib.instr_blk_mem_sim xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim instr_blk_mem_sim -key {Behavioral:sim_1:Functional:instr_blk_mem_sim} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb instr_blk_mem_sim.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./instr_blk_mem_sim.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: instr_blk_mem_sim.sh [-help]\n\ +Usage: instr_blk_mem_sim.sh [-lib_map_path]\n\ +Usage: instr_blk_mem_sim.sh [-reset_run]\n\ +Usage: instr_blk_mem_sim.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_afa8.protoinst new file mode 100644 index 0000000..a0656b6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_afa8.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_afa8": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_ba6a.protoinst new file mode 100644 index 0000000..c42e1c4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/protoinst_files/bd_ba6a.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_ba6a": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/simmem.coe b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/simmem.coe new file mode 100755 index 0000000..90d215f --- /dev/null +++ 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\ No newline at end of file diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/summary.log new file mode 100755 index 0000000..db51362 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [2] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 4.238151 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/vlog.prj new file mode 100644 index 0000000..e315bbf --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/instr_blk_mem_sim/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../../U200.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/README.txt new file mode 100644 index 0000000..5acdd2f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/README.txt new file mode 100644 index 0000000..67e5cc5 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:24 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4.sh' script. + +./phy_ddr4.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4.sh -noclean_files + +For more information on the script, please type './phy_ddr4.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/compile.do new file mode 100644 index 0000000..066ff39 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/compile.do @@ -0,0 +1,137 @@ +vlib work +vlib activehdl + +vlib activehdl/xilinx_vip +vlib activehdl/xpm +vlib activehdl/microblaze_v11_0_4 +vlib activehdl/xil_defaultlib +vlib activehdl/lib_cdc_v1_0_2 +vlib activehdl/proc_sys_reset_v5_0_13 +vlib activehdl/lmb_v10_v3_0_11 +vlib activehdl/lmb_bram_if_cntlr_v4_0_19 +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/iomodule_v3_1_6 + +vmap xilinx_vip activehdl/xilinx_vip +vmap xpm activehdl/xpm +vmap microblaze_v11_0_4 activehdl/microblaze_v11_0_4 +vmap xil_defaultlib activehdl/xil_defaultlib +vmap lib_cdc_v1_0_2 activehdl/lib_cdc_v1_0_2 +vmap proc_sys_reset_v5_0_13 activehdl/proc_sys_reset_v5_0_13 +vmap lmb_v10_v3_0_11 activehdl/lmb_v10_v3_0_11 +vmap lmb_bram_if_cntlr_v4_0_19 activehdl/lmb_bram_if_cntlr_v4_0_19 +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap iomodule_v3_1_6 activehdl/iomodule_v3_1_6 + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work microblaze_v11_0_4 -93 \ +"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \ + +vcom -work lib_cdc_v1_0_2 -93 \ +"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work proc_sys_reset_v5_0_13 -93 \ +"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \ + +vcom -work lmb_v10_v3_0_11 -93 \ +"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \ + +vcom -work lmb_bram_if_cntlr_v4_0_19 -93 \ +"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \ + +vcom -work iomodule_v3_1_6 -93 \ +"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \ + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/custom_parts_ddr4_2016_4_and_above.csv new file mode 100755 index 0000000..0e96b29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/custom_parts_ddr4_2016_4_and_above.csv @@ -0,0 +1,9 @@ +Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/file_info.txt new file mode 100644 index 0000000..a852294 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.h new file mode 100755 index 0000000..d82087e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.h @@ -0,0 +1,472 @@ +#ifndef IP_PHY_DDR4_H_ +#define IP_PHY_DDR4_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.sh new file mode 100755 index 0000000..bec5b04 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_ddr4.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:24 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4.sh [-help] +# usage: phy_ddr4.sh [-lib_map_path] +# usage: phy_ddr4.sh [-noclean_files] +# usage: phy_ddr4.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4.sh [-help]\n\ +Usage: phy_ddr4.sh [-lib_map_path]\n\ +Usage: phy_ddr4.sh [-reset_run]\n\ +Usage: phy_ddr4.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4_sc.h new file mode 100755 index 0000000..036743e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/phy_ddr4_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_SC_H_ +#define IP_PHY_DDR4_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_sc(const phy_ddr4_sc&); + const phy_ddr4_sc& operator=(const phy_ddr4_sc&); + +}; + +#endif // IP_PHY_DDR4_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/simulate.do new file mode 100644 index 0000000..98bfe9c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+phy_ddr4 -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.phy_ddr4 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {phy_ddr4.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/README.txt new file mode 100644 index 0000000..8eae52e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:24 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4.sh' script. + +./phy_ddr4.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4.sh -noclean_files + +For more information on the script, please type './phy_ddr4.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/custom_parts_ddr4_2016_4_and_above.csv new file mode 100755 index 0000000..0e96b29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/custom_parts_ddr4_2016_4_and_above.csv @@ -0,0 +1,9 @@ +Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/file_info.txt new file mode 100644 index 0000000..c7c8650 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.h new file mode 100755 index 0000000..d82087e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.h @@ -0,0 +1,472 @@ +#ifndef IP_PHY_DDR4_H_ +#define IP_PHY_DDR4_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.sh new file mode 100755 index 0000000..ba1c4b6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.sh @@ -0,0 +1,182 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_ddr4.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:24 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4.sh [-help] +# usage: phy_ddr4.sh [-lib_map_path] +# usage: phy_ddr4.sh [-noclean_files] +# usage: phy_ddr4.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.phy_ddr4 \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4.sh [-help]\n\ +Usage: phy_ddr4.sh [-lib_map_path]\n\ +Usage: phy_ddr4.sh [-reset_run]\n\ +Usage: phy_ddr4.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4_sc.h new file mode 100755 index 0000000..036743e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_SC_H_ +#define IP_PHY_DDR4_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_sc(const phy_ddr4_sc&); + const phy_ddr4_sc& operator=(const phy_ddr4_sc&); + +}; + +#endif // IP_PHY_DDR4_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/run.f new file mode 100644 index 0000000..6ddac70 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/run.f @@ -0,0 +1,113 @@ +-makelib ies_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/microblaze_v11_0_4 \ + "../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \ +-endlib +-makelib ies_lib/lib_cdc_v1_0_2 \ + "../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ +-endlib +-makelib ies_lib/proc_sys_reset_v5_0_13 \ + "../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \ +-endlib +-makelib ies_lib/lmb_v10_v3_0_11 \ + "../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \ +-endlib +-makelib ies_lib/lmb_bram_if_cntlr_v4_0_19 \ + "../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \ +-endlib +-makelib ies_lib/iomodule_v3_1_6 \ + "../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \ +-endlib +-makelib ies_lib/xil_defaultlib -sv \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/ies/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/README.txt new file mode 100644 index 0000000..67e5cc5 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:24 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4.sh' script. + +./phy_ddr4.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4.sh -noclean_files + +For more information on the script, please type './phy_ddr4.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/compile.do new file mode 100644 index 0000000..e566929 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/compile.do @@ -0,0 +1,137 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xilinx_vip +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/microblaze_v11_0_4 +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/lib_cdc_v1_0_2 +vlib modelsim_lib/msim/proc_sys_reset_v5_0_13 +vlib modelsim_lib/msim/lmb_v10_v3_0_11 +vlib modelsim_lib/msim/lmb_bram_if_cntlr_v4_0_19 +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/iomodule_v3_1_6 + +vmap xilinx_vip modelsim_lib/msim/xilinx_vip +vmap xpm modelsim_lib/msim/xpm +vmap microblaze_v11_0_4 modelsim_lib/msim/microblaze_v11_0_4 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap lib_cdc_v1_0_2 modelsim_lib/msim/lib_cdc_v1_0_2 +vmap proc_sys_reset_v5_0_13 modelsim_lib/msim/proc_sys_reset_v5_0_13 +vmap lmb_v10_v3_0_11 modelsim_lib/msim/lmb_v10_v3_0_11 +vmap lmb_bram_if_cntlr_v4_0_19 modelsim_lib/msim/lmb_bram_if_cntlr_v4_0_19 +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap iomodule_v3_1_6 modelsim_lib/msim/iomodule_v3_1_6 + +vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work microblaze_v11_0_4 -64 -93 \ +"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \ + +vcom -work lib_cdc_v1_0_2 -64 -93 \ +"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work proc_sys_reset_v5_0_13 -64 -93 \ +"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \ + +vcom -work lmb_v10_v3_0_11 -64 -93 \ +"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \ + +vcom -work lmb_bram_if_cntlr_v4_0_19 -64 -93 \ +"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \ + +vcom -work iomodule_v3_1_6 -64 -93 \ +"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \ + +vlog -work xil_defaultlib -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/custom_parts_ddr4_2016_4_and_above.csv new file mode 100755 index 0000000..0e96b29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/custom_parts_ddr4_2016_4_and_above.csv @@ -0,0 +1,9 @@ +Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/file_info.txt new file mode 100644 index 0000000..a852294 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.h new file mode 100755 index 0000000..d82087e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.h @@ -0,0 +1,472 @@ +#ifndef IP_PHY_DDR4_H_ +#define IP_PHY_DDR4_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.sh new file mode 100755 index 0000000..7bc25d8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_ddr4.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:24 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4.sh [-help] +# usage: phy_ddr4.sh [-lib_map_path] +# usage: phy_ddr4.sh [-noclean_files] +# usage: phy_ddr4.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4.sh [-help]\n\ +Usage: phy_ddr4.sh [-lib_map_path]\n\ +Usage: phy_ddr4.sh [-reset_run]\n\ +Usage: phy_ddr4.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4_sc.h new file mode 100755 index 0000000..036743e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/phy_ddr4_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_SC_H_ +#define IP_PHY_DDR4_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_sc(const phy_ddr4_sc&); + const phy_ddr4_sc& operator=(const phy_ddr4_sc&); + +}; + +#endif // IP_PHY_DDR4_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/simulate.do new file mode 100644 index 0000000..7a40dbd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.phy_ddr4 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {phy_ddr4.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/README.txt new file mode 100644 index 0000000..67e5cc5 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:24 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4.sh' script. + +./phy_ddr4.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4.sh -noclean_files + +For more information on the script, please type './phy_ddr4.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/compile.do new file mode 100644 index 0000000..2ef7694 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/compile.do @@ -0,0 +1,137 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xilinx_vip +vlib questa_lib/msim/xpm +vlib questa_lib/msim/microblaze_v11_0_4 +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/lib_cdc_v1_0_2 +vlib questa_lib/msim/proc_sys_reset_v5_0_13 +vlib questa_lib/msim/lmb_v10_v3_0_11 +vlib questa_lib/msim/lmb_bram_if_cntlr_v4_0_19 +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/iomodule_v3_1_6 + +vmap xilinx_vip questa_lib/msim/xilinx_vip +vmap xpm questa_lib/msim/xpm +vmap microblaze_v11_0_4 questa_lib/msim/microblaze_v11_0_4 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap lib_cdc_v1_0_2 questa_lib/msim/lib_cdc_v1_0_2 +vmap proc_sys_reset_v5_0_13 questa_lib/msim/proc_sys_reset_v5_0_13 +vmap lmb_v10_v3_0_11 questa_lib/msim/lmb_v10_v3_0_11 +vmap lmb_bram_if_cntlr_v4_0_19 questa_lib/msim/lmb_bram_if_cntlr_v4_0_19 +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap iomodule_v3_1_6 questa_lib/msim/iomodule_v3_1_6 + +vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work microblaze_v11_0_4 -64 -93 \ +"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \ + +vcom -work lib_cdc_v1_0_2 -64 -93 \ +"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work proc_sys_reset_v5_0_13 -64 -93 \ +"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \ + +vcom -work lmb_v10_v3_0_11 -64 -93 \ +"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \ + +vcom -work lmb_bram_if_cntlr_v4_0_19 -64 -93 \ +"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \ + +vcom -work iomodule_v3_1_6 -64 -93 \ +"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \ + +vlog -work xil_defaultlib -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/custom_parts_ddr4_2016_4_and_above.csv new file mode 100755 index 0000000..0e96b29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/custom_parts_ddr4_2016_4_and_above.csv @@ -0,0 +1,9 @@ +Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/elaborate.do new file mode 100644 index 0000000..ecdddc7 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.phy_ddr4 xil_defaultlib.glbl -o phy_ddr4_opt diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/file_info.txt new file mode 100644 index 0000000..a852294 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.h new file mode 100755 index 0000000..d82087e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.h @@ -0,0 +1,472 @@ +#ifndef IP_PHY_DDR4_H_ +#define IP_PHY_DDR4_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.sh new file mode 100755 index 0000000..9f0acc7 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_ddr4.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:24 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4.sh [-help] +# usage: phy_ddr4.sh [-lib_map_path] +# usage: phy_ddr4.sh [-noclean_files] +# usage: phy_ddr4.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4.sh [-help]\n\ +Usage: phy_ddr4.sh [-lib_map_path]\n\ +Usage: phy_ddr4.sh [-reset_run]\n\ +Usage: phy_ddr4.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4_sc.h new file mode 100755 index 0000000..036743e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/phy_ddr4_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_SC_H_ +#define IP_PHY_DDR4_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_sc(const phy_ddr4_sc&); + const phy_ddr4_sc& operator=(const phy_ddr4_sc&); + +}; + +#endif // IP_PHY_DDR4_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/simulate.do new file mode 100644 index 0000000..a04d2c1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -lib xil_defaultlib phy_ddr4_opt + +do {wave.do} + +view wave +view structure +view signals + +do {phy_ddr4.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/README.txt new file mode 100644 index 0000000..67e5cc5 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:24 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4.sh' script. + +./phy_ddr4.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4.sh -noclean_files + +For more information on the script, please type './phy_ddr4.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/compile.do new file mode 100644 index 0000000..3598ac3 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/compile.do @@ -0,0 +1,137 @@ +vlib work +vlib riviera + +vlib riviera/xilinx_vip +vlib riviera/xpm +vlib riviera/microblaze_v11_0_4 +vlib riviera/xil_defaultlib +vlib riviera/lib_cdc_v1_0_2 +vlib riviera/proc_sys_reset_v5_0_13 +vlib riviera/lmb_v10_v3_0_11 +vlib riviera/lmb_bram_if_cntlr_v4_0_19 +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/iomodule_v3_1_6 + +vmap xilinx_vip riviera/xilinx_vip +vmap xpm riviera/xpm +vmap microblaze_v11_0_4 riviera/microblaze_v11_0_4 +vmap xil_defaultlib riviera/xil_defaultlib +vmap lib_cdc_v1_0_2 riviera/lib_cdc_v1_0_2 +vmap proc_sys_reset_v5_0_13 riviera/proc_sys_reset_v5_0_13 +vmap lmb_v10_v3_0_11 riviera/lmb_v10_v3_0_11 +vmap lmb_bram_if_cntlr_v4_0_19 riviera/lmb_bram_if_cntlr_v4_0_19 +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap iomodule_v3_1_6 riviera/iomodule_v3_1_6 + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work microblaze_v11_0_4 -93 \ +"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \ + +vcom -work lib_cdc_v1_0_2 -93 \ +"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work proc_sys_reset_v5_0_13 -93 \ +"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \ + +vcom -work lmb_v10_v3_0_11 -93 \ +"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \ + +vcom -work lmb_bram_if_cntlr_v4_0_19 -93 \ +"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \ + +vcom -work iomodule_v3_1_6 -93 \ +"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \ + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/custom_parts_ddr4_2016_4_and_above.csv new file mode 100755 index 0000000..0e96b29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/custom_parts_ddr4_2016_4_and_above.csv @@ -0,0 +1,9 @@ +Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/file_info.txt new file mode 100644 index 0000000..a852294 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.h new file mode 100755 index 0000000..d82087e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.h @@ -0,0 +1,472 @@ +#ifndef IP_PHY_DDR4_H_ +#define IP_PHY_DDR4_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.sh new file mode 100755 index 0000000..a649ee0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_ddr4.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:24 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4.sh [-help] +# usage: phy_ddr4.sh [-lib_map_path] +# usage: phy_ddr4.sh [-noclean_files] +# usage: phy_ddr4.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4.sh [-help]\n\ +Usage: phy_ddr4.sh [-lib_map_path]\n\ +Usage: phy_ddr4.sh [-reset_run]\n\ +Usage: phy_ddr4.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4_sc.h new file mode 100755 index 0000000..036743e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/phy_ddr4_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_SC_H_ +#define IP_PHY_DDR4_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_sc(const phy_ddr4_sc&); + const phy_ddr4_sc& operator=(const phy_ddr4_sc&); + +}; + +#endif // IP_PHY_DDR4_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/simulate.do new file mode 100644 index 0000000..98bfe9c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+phy_ddr4 -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.phy_ddr4 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {phy_ddr4.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/README.txt new file mode 100644 index 0000000..67e5cc5 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:24 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4.sh' script. + +./phy_ddr4.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4.sh -noclean_files + +For more information on the script, please type './phy_ddr4.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/custom_parts_ddr4_2016_4_and_above.csv new file mode 100755 index 0000000..0e96b29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/custom_parts_ddr4_2016_4_and_above.csv @@ -0,0 +1,9 @@ +Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/file_info.txt new file mode 100644 index 0000000..c7c8650 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4.h new file mode 100755 index 0000000..d82087e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4.h @@ -0,0 +1,472 @@ +#ifndef IP_PHY_DDR4_H_ +#define IP_PHY_DDR4_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4.sh new file mode 100755 index 0000000..dd806cb --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4.sh @@ -0,0 +1,346 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_ddr4.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:24 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4.sh [-help] +# usage: phy_ddr4.sh [-lib_map_path] +# usage: phy_ddr4.sh [-noclean_files] +# usage: phy_ddr4.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work microblaze_v11_0_4 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work lib_cdc_v1_0_2 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work proc_sys_reset_v5_0_13 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work lmb_v10_v3_0_11 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work lmb_bram_if_cntlr_v4_0_19 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work iomodule_v3_1_6 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.phy_ddr4 xil_defaultlib.glbl -o phy_ddr4_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./phy_ddr4_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key phy_ddr4_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc phy_ddr4_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4.sh [-help]\n\ +Usage: phy_ddr4.sh [-lib_map_path]\n\ +Usage: phy_ddr4.sh [-reset_run]\n\ +Usage: phy_ddr4.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4_sc.h new file mode 100755 index 0000000..036743e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/phy_ddr4_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_SC_H_ +#define IP_PHY_DDR4_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_sc(const phy_ddr4_sc&); + const phy_ddr4_sc& operator=(const phy_ddr4_sc&); + +}; + +#endif // IP_PHY_DDR4_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/README.txt new file mode 100644 index 0000000..8eae52e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:24 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4.sh' script. + +./phy_ddr4.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4.sh -noclean_files + +For more information on the script, please type './phy_ddr4.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/custom_parts_ddr4_2016_4_and_above.csv new file mode 100755 index 0000000..0e96b29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/custom_parts_ddr4_2016_4_and_above.csv @@ -0,0 +1,9 @@ +Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/file_info.txt new file mode 100644 index 0000000..c7c8650 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4.h new file mode 100755 index 0000000..d82087e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4.h @@ -0,0 +1,472 @@ +#ifndef IP_PHY_DDR4_H_ +#define IP_PHY_DDR4_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4.sh new file mode 100755 index 0000000..d794dd7 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4.sh @@ -0,0 +1,182 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_ddr4.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:24 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4.sh [-help] +# usage: phy_ddr4.sh [-lib_map_path] +# usage: phy_ddr4.sh [-noclean_files] +# usage: phy_ddr4.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.phy_ddr4 \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4.sh [-help]\n\ +Usage: phy_ddr4.sh [-lib_map_path]\n\ +Usage: phy_ddr4.sh [-reset_run]\n\ +Usage: phy_ddr4.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4_sc.h new file mode 100755 index 0000000..036743e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/phy_ddr4_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_SC_H_ +#define IP_PHY_DDR4_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_sc(const phy_ddr4_sc&); + const phy_ddr4_sc& operator=(const phy_ddr4_sc&); + +}; + +#endif // IP_PHY_DDR4_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/run.f new file mode 100644 index 0000000..f7914cf --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/run.f @@ -0,0 +1,113 @@ +-makelib xcelium_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/microblaze_v11_0_4 \ + "../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \ +-endlib +-makelib xcelium_lib/lib_cdc_v1_0_2 \ + "../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ +-endlib +-makelib xcelium_lib/proc_sys_reset_v5_0_13 \ + "../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \ +-endlib +-makelib xcelium_lib/lmb_v10_v3_0_11 \ + "../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \ +-endlib +-makelib xcelium_lib/lmb_bram_if_cntlr_v4_0_19 \ + "../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \ +-endlib +-makelib xcelium_lib/iomodule_v3_1_6 \ + "../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib -sv \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xcelium/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/README.txt new file mode 100644 index 0000000..67e5cc5 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:24 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4.sh' script. + +./phy_ddr4.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4.sh -noclean_files + +For more information on the script, please type './phy_ddr4.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/U200.smi new file mode 100644 index 0000000..f20b0a8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/U200.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2020.2 (64-bit) --> +<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 --> +<!-- --> +<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 18 2020 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcu200-fsgd2104-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/custom_parts_ddr4_2016_4_and_above.csv b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/custom_parts_ddr4_2016_4_and_above.csv new file mode 100755 index 0000000..0e96b29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/custom_parts_ddr4_2016_4_and_above.csv @@ -0,0 +1,9 @@ +Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length
+Components,DDR4_CUSTOM,1,1,0,1,17,15,10,2,1,1,1,1,1,107E,4Gb,4Gb,16,16,8,1.2V,"8,16,24,32,40,48,56,64,72,80",1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,13,12,8
+UDIMMs,DDR4_CUSTOM1,2,1,1,1,17,15,10,2,2,2,2,2,2,2G1,8GB,1Gb,72,8,8,1.2V,72,1250,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,12,9,8
+SODIMMs,DDR4_CUSTOM2,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,64,8,8,1.2V,64,1071,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,14,12,8
+RDIMMs,DDR4_CUSTOM3,1,1,0,1,17,15,10,2,2,1,1,1,1,2G1,4GB,512Mb,72,8,8,1.2V,72,938,1600,5000 ps,30000 ps,0,8 tck,34000 ps,13920 ps,7800000 ps,260000 ps,0,13920 ps,5300 ps,6400 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,270 ns,128 tck,1024 tck,0,15,11,8
+RDIMMs,DDR4_CUSTOM4,2,2,1,1,17,15,10,2,2,2,2,2,1,83,8GB,4Gb,72,8,8,1.2V,72,833,1600,5000 ps,21000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,100000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,4 tck,16,14,8
+RDIMMs,DDR4_CUSTOM5,2,4,1,0,17,16,10,2,2,2,2,2,1,83,16GB,4Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+RDIMMs,64GB,1,1,0,0,18,18,10,2,2,1,1,1,1,83,64GB,16Gb,72,4,4,1.2V,72,833,1600,5000 ps,13000 ps,16 tck,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,110000 ps,14160 ps,3300 ps,4900 ps,4 tck,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,5 tck,16,14,8
+LRDIMMs,DDR4_CUSTOM6,4,1,1,0,17,16,10,2,2,4,2,2,2,093E,32GB,8Gb,72,4,4,1.2V,72,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/file_info.txt new file mode 100644 index 0000000..b5599f5 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/file_info.txt @@ -0,0 +1,50 @@ +bd_9f2c_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +bd_9f2c_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" 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+ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4.h new file mode 100755 index 0000000..d82087e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4.h @@ -0,0 +1,472 @@ +#ifndef IP_PHY_DDR4_H_ +#define IP_PHY_DDR4_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4 : public phy_ddr4_sc +{ +public: + + phy_ddr4(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_out< bool > addn_ui_clkout1; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<144> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<18> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4.sh new file mode 100755 index 0000000..7fce527 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4.sh @@ -0,0 +1,214 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_ddr4.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:24 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4.sh [-help] +# usage: phy_ddr4.sh [-lib_map_path] +# usage: phy_ddr4.sh [-noclean_files] +# usage: phy_ddr4.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0 +xvlog_opts="--relax -L xdma_v4_1_8" +xvhdl_opts="--relax" + + +# Script info +echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot phy_ddr4 xil_defaultlib.phy_ddr4 xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim phy_ddr4 -key {Behavioral:sim_1:Functional:phy_ddr4} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb phy_ddr4.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4.sh [-help]\n\ +Usage: phy_ddr4.sh [-lib_map_path]\n\ +Usage: phy_ddr4.sh [-reset_run]\n\ +Usage: phy_ddr4.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4_sc.h new file mode 100755 index 0000000..036743e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/phy_ddr4_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_SC_H_ +#define IP_PHY_DDR4_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_sc(const phy_ddr4_sc&); + const phy_ddr4_sc& operator=(const phy_ddr4_sc&); + +}; + +#endif // IP_PHY_DDR4_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_afa8.protoinst new file mode 100644 index 0000000..a0656b6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_afa8.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_afa8": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_ba6a.protoinst new file mode 100644 index 0000000..c42e1c4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/protoinst_files/bd_ba6a.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_ba6a": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/vhdl.prj b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/vhdl.prj new file mode 100644 index 0000000..fe85343 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/vhdl.prj @@ -0,0 +1,12 @@ +vhdl xil_defaultlib \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \ + +nosort diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/vlog.prj new file mode 100644 index 0000000..29c5593 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4/xsim/vlog.prj @@ -0,0 +1,47 @@ +verilog xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \ + +sv xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/README.txt new file mode 100644 index 0000000..5acdd2f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/README.txt new file mode 100644 index 0000000..06ceb3a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4_udimm.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4_udimm.sh' script. + +./phy_ddr4_udimm.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4_udimm.sh -noclean_files + +For more information on the script, please type './phy_ddr4_udimm.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/compile.do new file mode 100644 index 0000000..60fc190 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/compile.do @@ -0,0 +1,137 @@ +vlib work +vlib activehdl + +vlib activehdl/xilinx_vip +vlib activehdl/xpm +vlib activehdl/microblaze_v11_0_4 +vlib activehdl/xil_defaultlib +vlib activehdl/lib_cdc_v1_0_2 +vlib activehdl/proc_sys_reset_v5_0_13 +vlib activehdl/lmb_v10_v3_0_11 +vlib activehdl/lmb_bram_if_cntlr_v4_0_19 +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/iomodule_v3_1_6 + +vmap xilinx_vip activehdl/xilinx_vip +vmap xpm activehdl/xpm +vmap microblaze_v11_0_4 activehdl/microblaze_v11_0_4 +vmap xil_defaultlib activehdl/xil_defaultlib +vmap lib_cdc_v1_0_2 activehdl/lib_cdc_v1_0_2 +vmap proc_sys_reset_v5_0_13 activehdl/proc_sys_reset_v5_0_13 +vmap lmb_v10_v3_0_11 activehdl/lmb_v10_v3_0_11 +vmap lmb_bram_if_cntlr_v4_0_19 activehdl/lmb_bram_if_cntlr_v4_0_19 +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap iomodule_v3_1_6 activehdl/iomodule_v3_1_6 + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work microblaze_v11_0_4 -93 \ +"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd" \ + +vcom -work lib_cdc_v1_0_2 -93 \ +"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work proc_sys_reset_v5_0_13 -93 \ +"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd" \ + +vcom -work lmb_v10_v3_0_11 -93 \ +"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd" \ + +vcom -work lmb_bram_if_cntlr_v4_0_19 -93 \ +"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v" \ + +vcom -work iomodule_v3_1_6 -93 \ +"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v" \ + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/file_info.txt new file mode 100644 index 0000000..c6f10bd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" 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+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm.h new file mode 100755 index 0000000..ec2d0cd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm.h @@ -0,0 +1,467 @@ +#ifndef IP_PHY_DDR4_UDIMM_H_ +#define IP_PHY_DDR4_UDIMM_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_udimm_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_UDIMM_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm.sh new file mode 100755 index 0000000..5f61c2c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_ddr4_udimm.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4_udimm.sh [-help] +# usage: phy_ddr4_udimm.sh [-lib_map_path] +# usage: phy_ddr4_udimm.sh [-noclean_files] +# usage: phy_ddr4_udimm.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4_udimm.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "phy_ddr4_udimm.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4_udimm.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4_udimm.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4_udimm.sh [-help]\n\ +Usage: phy_ddr4_udimm.sh [-lib_map_path]\n\ +Usage: phy_ddr4_udimm.sh [-reset_run]\n\ +Usage: phy_ddr4_udimm.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm_sc.h new file mode 100755 index 0000000..e31f3a2 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/phy_ddr4_udimm_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_UDIMM_SC_H_ +#define IP_PHY_DDR4_UDIMM_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&); + const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&); + +}; + +#endif // IP_PHY_DDR4_UDIMM_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/simulate.do new file mode 100644 index 0000000..2451173 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+phy_ddr4_udimm -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.phy_ddr4_udimm xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {phy_ddr4_udimm.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/README.txt new file mode 100644 index 0000000..7905ff1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4_udimm.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4_udimm.sh' script. + +./phy_ddr4_udimm.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4_udimm.sh -noclean_files + +For more information on the script, please type './phy_ddr4_udimm.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/file_info.txt new file mode 100644 index 0000000..af33135 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" 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+phy_ddr4_udimm_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm.h new file mode 100755 index 0000000..ec2d0cd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm.h @@ -0,0 +1,467 @@ +#ifndef IP_PHY_DDR4_UDIMM_H_ +#define IP_PHY_DDR4_UDIMM_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_udimm_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_UDIMM_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm.sh new file mode 100755 index 0000000..cb90c3a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm.sh @@ -0,0 +1,182 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_ddr4_udimm.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4_udimm.sh [-help] +# usage: phy_ddr4_udimm.sh [-lib_map_path] +# usage: phy_ddr4_udimm.sh [-noclean_files] +# usage: phy_ddr4_udimm.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4_udimm.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "phy_ddr4_udimm.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.phy_ddr4_udimm \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4_udimm.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4_udimm.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4_udimm.sh [-help]\n\ +Usage: phy_ddr4_udimm.sh [-lib_map_path]\n\ +Usage: phy_ddr4_udimm.sh [-reset_run]\n\ +Usage: phy_ddr4_udimm.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm_sc.h new file mode 100755 index 0000000..e31f3a2 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/phy_ddr4_udimm_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_UDIMM_SC_H_ +#define IP_PHY_DDR4_UDIMM_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&); + const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&); + +}; + +#endif // IP_PHY_DDR4_UDIMM_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/run.f new file mode 100644 index 0000000..bee9b75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/run.f @@ -0,0 +1,113 @@ +-makelib ies_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/microblaze_v11_0_4 \ + "../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd" \ +-endlib +-makelib ies_lib/lib_cdc_v1_0_2 \ + "../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ +-endlib +-makelib ies_lib/proc_sys_reset_v5_0_13 \ + "../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd" \ +-endlib +-makelib ies_lib/lmb_v10_v3_0_11 \ + "../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd" \ +-endlib +-makelib ies_lib/lmb_bram_if_cntlr_v4_0_19 \ + "../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v" \ +-endlib +-makelib ies_lib/iomodule_v3_1_6 \ + "../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v" \ +-endlib +-makelib ies_lib/xil_defaultlib -sv \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/ies/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/README.txt new file mode 100644 index 0000000..06ceb3a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4_udimm.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4_udimm.sh' script. + +./phy_ddr4_udimm.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4_udimm.sh -noclean_files + +For more information on the script, please type './phy_ddr4_udimm.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/compile.do new file mode 100644 index 0000000..b8f3428 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/compile.do @@ -0,0 +1,137 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xilinx_vip +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/microblaze_v11_0_4 +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/lib_cdc_v1_0_2 +vlib modelsim_lib/msim/proc_sys_reset_v5_0_13 +vlib modelsim_lib/msim/lmb_v10_v3_0_11 +vlib modelsim_lib/msim/lmb_bram_if_cntlr_v4_0_19 +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/iomodule_v3_1_6 + +vmap xilinx_vip modelsim_lib/msim/xilinx_vip +vmap xpm modelsim_lib/msim/xpm +vmap microblaze_v11_0_4 modelsim_lib/msim/microblaze_v11_0_4 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap lib_cdc_v1_0_2 modelsim_lib/msim/lib_cdc_v1_0_2 +vmap proc_sys_reset_v5_0_13 modelsim_lib/msim/proc_sys_reset_v5_0_13 +vmap lmb_v10_v3_0_11 modelsim_lib/msim/lmb_v10_v3_0_11 +vmap lmb_bram_if_cntlr_v4_0_19 modelsim_lib/msim/lmb_bram_if_cntlr_v4_0_19 +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap iomodule_v3_1_6 modelsim_lib/msim/iomodule_v3_1_6 + +vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work microblaze_v11_0_4 -64 -93 \ +"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd" \ + +vcom -work lib_cdc_v1_0_2 -64 -93 \ +"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work proc_sys_reset_v5_0_13 -64 -93 \ +"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd" \ + +vcom -work lmb_v10_v3_0_11 -64 -93 \ +"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd" \ + +vcom -work lmb_bram_if_cntlr_v4_0_19 -64 -93 \ +"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v" \ + +vcom -work iomodule_v3_1_6 -64 -93 \ +"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v" \ + +vlog -work xil_defaultlib -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/file_info.txt new file mode 100644 index 0000000..c6f10bd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" 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+ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm.h new file mode 100755 index 0000000..ec2d0cd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm.h @@ -0,0 +1,467 @@ +#ifndef IP_PHY_DDR4_UDIMM_H_ +#define IP_PHY_DDR4_UDIMM_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_udimm_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_UDIMM_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm.sh new file mode 100755 index 0000000..b88c0a8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_ddr4_udimm.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4_udimm.sh [-help] +# usage: phy_ddr4_udimm.sh [-lib_map_path] +# usage: phy_ddr4_udimm.sh [-noclean_files] +# usage: phy_ddr4_udimm.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4_udimm.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "phy_ddr4_udimm.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4_udimm.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4_udimm.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4_udimm.sh [-help]\n\ +Usage: phy_ddr4_udimm.sh [-lib_map_path]\n\ +Usage: phy_ddr4_udimm.sh [-reset_run]\n\ +Usage: phy_ddr4_udimm.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm_sc.h new file mode 100755 index 0000000..e31f3a2 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/phy_ddr4_udimm_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_UDIMM_SC_H_ +#define IP_PHY_DDR4_UDIMM_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&); + const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&); + +}; + +#endif // IP_PHY_DDR4_UDIMM_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/simulate.do new file mode 100644 index 0000000..316c990 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.phy_ddr4_udimm xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {phy_ddr4_udimm.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/README.txt new file mode 100644 index 0000000..06ceb3a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4_udimm.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4_udimm.sh' script. + +./phy_ddr4_udimm.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4_udimm.sh -noclean_files + +For more information on the script, please type './phy_ddr4_udimm.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/compile.do new file mode 100644 index 0000000..e5a9152 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/compile.do @@ -0,0 +1,137 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xilinx_vip +vlib questa_lib/msim/xpm +vlib questa_lib/msim/microblaze_v11_0_4 +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/lib_cdc_v1_0_2 +vlib questa_lib/msim/proc_sys_reset_v5_0_13 +vlib questa_lib/msim/lmb_v10_v3_0_11 +vlib questa_lib/msim/lmb_bram_if_cntlr_v4_0_19 +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/iomodule_v3_1_6 + +vmap xilinx_vip questa_lib/msim/xilinx_vip +vmap xpm questa_lib/msim/xpm +vmap microblaze_v11_0_4 questa_lib/msim/microblaze_v11_0_4 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap lib_cdc_v1_0_2 questa_lib/msim/lib_cdc_v1_0_2 +vmap proc_sys_reset_v5_0_13 questa_lib/msim/proc_sys_reset_v5_0_13 +vmap lmb_v10_v3_0_11 questa_lib/msim/lmb_v10_v3_0_11 +vmap lmb_bram_if_cntlr_v4_0_19 questa_lib/msim/lmb_bram_if_cntlr_v4_0_19 +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap iomodule_v3_1_6 questa_lib/msim/iomodule_v3_1_6 + +vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work microblaze_v11_0_4 -64 -93 \ +"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd" \ + +vcom -work lib_cdc_v1_0_2 -64 -93 \ +"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work proc_sys_reset_v5_0_13 -64 -93 \ +"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd" \ + +vcom -work lmb_v10_v3_0_11 -64 -93 \ +"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd" \ + +vcom -work lmb_bram_if_cntlr_v4_0_19 -64 -93 \ +"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v" \ + +vcom -work iomodule_v3_1_6 -64 -93 \ +"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v" \ + +vlog -work xil_defaultlib -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/elaborate.do new file mode 100644 index 0000000..96e5ee3 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.phy_ddr4_udimm xil_defaultlib.glbl -o phy_ddr4_udimm_opt diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/file_info.txt new file mode 100644 index 0000000..c6f10bd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" 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+bd_ba6a_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" 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+lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_19,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" 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+ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm.h new file mode 100755 index 0000000..ec2d0cd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm.h @@ -0,0 +1,467 @@ +#ifndef IP_PHY_DDR4_UDIMM_H_ +#define IP_PHY_DDR4_UDIMM_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_udimm_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_UDIMM_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm.sh new file mode 100755 index 0000000..407b1e6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_ddr4_udimm.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4_udimm.sh [-help] +# usage: phy_ddr4_udimm.sh [-lib_map_path] +# usage: phy_ddr4_udimm.sh [-noclean_files] +# usage: phy_ddr4_udimm.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4_udimm.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "phy_ddr4_udimm.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4_udimm.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4_udimm.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4_udimm.sh [-help]\n\ +Usage: phy_ddr4_udimm.sh [-lib_map_path]\n\ +Usage: phy_ddr4_udimm.sh [-reset_run]\n\ +Usage: phy_ddr4_udimm.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm_sc.h new file mode 100755 index 0000000..e31f3a2 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/phy_ddr4_udimm_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_UDIMM_SC_H_ +#define IP_PHY_DDR4_UDIMM_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&); + const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&); + +}; + +#endif // IP_PHY_DDR4_UDIMM_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/simulate.do new file mode 100644 index 0000000..3ef7865 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -lib xil_defaultlib phy_ddr4_udimm_opt + +do {wave.do} + +view wave +view structure +view signals + +do {phy_ddr4_udimm.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/README.txt new file mode 100644 index 0000000..06ceb3a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4_udimm.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4_udimm.sh' script. + +./phy_ddr4_udimm.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4_udimm.sh -noclean_files + +For more information on the script, please type './phy_ddr4_udimm.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/compile.do new file mode 100644 index 0000000..c67c0c9 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/compile.do @@ -0,0 +1,137 @@ +vlib work +vlib riviera + +vlib riviera/xilinx_vip +vlib riviera/xpm +vlib riviera/microblaze_v11_0_4 +vlib riviera/xil_defaultlib +vlib riviera/lib_cdc_v1_0_2 +vlib riviera/proc_sys_reset_v5_0_13 +vlib riviera/lmb_v10_v3_0_11 +vlib riviera/lmb_bram_if_cntlr_v4_0_19 +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/iomodule_v3_1_6 + +vmap xilinx_vip riviera/xilinx_vip +vmap xpm riviera/xpm +vmap microblaze_v11_0_4 riviera/microblaze_v11_0_4 +vmap xil_defaultlib riviera/xil_defaultlib +vmap lib_cdc_v1_0_2 riviera/lib_cdc_v1_0_2 +vmap proc_sys_reset_v5_0_13 riviera/proc_sys_reset_v5_0_13 +vmap lmb_v10_v3_0_11 riviera/lmb_v10_v3_0_11 +vmap lmb_bram_if_cntlr_v4_0_19 riviera/lmb_bram_if_cntlr_v4_0_19 +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap iomodule_v3_1_6 riviera/iomodule_v3_1_6 + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work microblaze_v11_0_4 -93 \ +"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd" \ + +vcom -work lib_cdc_v1_0_2 -93 \ +"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work proc_sys_reset_v5_0_13 -93 \ +"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd" \ + +vcom -work lmb_v10_v3_0_11 -93 \ +"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd" \ + +vcom -work lmb_bram_if_cntlr_v4_0_19 -93 \ +"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v" \ + +vcom -work iomodule_v3_1_6 -93 \ +"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v" \ + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/file_info.txt new file mode 100644 index 0000000..c6f10bd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" 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+ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm.h new file mode 100755 index 0000000..ec2d0cd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm.h @@ -0,0 +1,467 @@ +#ifndef IP_PHY_DDR4_UDIMM_H_ +#define IP_PHY_DDR4_UDIMM_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_udimm_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_UDIMM_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm.sh new file mode 100755 index 0000000..b1f6870 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_ddr4_udimm.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4_udimm.sh [-help] +# usage: phy_ddr4_udimm.sh [-lib_map_path] +# usage: phy_ddr4_udimm.sh [-noclean_files] +# usage: phy_ddr4_udimm.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4_udimm.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "phy_ddr4_udimm.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4_udimm.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4_udimm.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4_udimm.sh [-help]\n\ +Usage: phy_ddr4_udimm.sh [-lib_map_path]\n\ +Usage: phy_ddr4_udimm.sh [-reset_run]\n\ +Usage: phy_ddr4_udimm.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm_sc.h new file mode 100755 index 0000000..e31f3a2 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/phy_ddr4_udimm_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_UDIMM_SC_H_ +#define IP_PHY_DDR4_UDIMM_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&); + const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&); + +}; + +#endif // IP_PHY_DDR4_UDIMM_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/simulate.do new file mode 100644 index 0000000..2451173 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+phy_ddr4_udimm -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.phy_ddr4_udimm xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {phy_ddr4_udimm.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/README.txt new file mode 100644 index 0000000..06ceb3a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4_udimm.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4_udimm.sh' script. + +./phy_ddr4_udimm.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4_udimm.sh -noclean_files + +For more information on the script, please type './phy_ddr4_udimm.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/file_info.txt new file mode 100644 index 0000000..af33135 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" 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+phy_ddr4_udimm_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm.h new file mode 100755 index 0000000..ec2d0cd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm.h @@ -0,0 +1,467 @@ +#ifndef IP_PHY_DDR4_UDIMM_H_ +#define IP_PHY_DDR4_UDIMM_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_udimm_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_UDIMM_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm.sh new file mode 100755 index 0000000..79d917c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm.sh @@ -0,0 +1,346 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_ddr4_udimm.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4_udimm.sh [-help] +# usage: phy_ddr4_udimm.sh [-lib_map_path] +# usage: phy_ddr4_udimm.sh [-noclean_files] +# usage: phy_ddr4_udimm.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4_udimm.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "phy_ddr4_udimm.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work microblaze_v11_0_4 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work lib_cdc_v1_0_2 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work proc_sys_reset_v5_0_13 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work lmb_v10_v3_0_11 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work lmb_bram_if_cntlr_v4_0_19 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work iomodule_v3_1_6 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.phy_ddr4_udimm xil_defaultlib.glbl -o phy_ddr4_udimm_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./phy_ddr4_udimm_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4_udimm.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key phy_ddr4_udimm_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc phy_ddr4_udimm_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4_udimm.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4_udimm.sh [-help]\n\ +Usage: phy_ddr4_udimm.sh [-lib_map_path]\n\ +Usage: phy_ddr4_udimm.sh [-reset_run]\n\ +Usage: phy_ddr4_udimm.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm_sc.h new file mode 100755 index 0000000..e31f3a2 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/phy_ddr4_udimm_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_UDIMM_SC_H_ +#define IP_PHY_DDR4_UDIMM_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&); + const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&); + +}; + +#endif // IP_PHY_DDR4_UDIMM_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/README.txt new file mode 100644 index 0000000..7905ff1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4_udimm.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4_udimm.sh' script. + +./phy_ddr4_udimm.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4_udimm.sh -noclean_files + +For more information on the script, please type './phy_ddr4_udimm.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/file_info.txt new file mode 100644 index 0000000..af33135 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_19,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_second_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" 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+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm.h new file mode 100755 index 0000000..ec2d0cd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm.h @@ -0,0 +1,467 @@ +#ifndef IP_PHY_DDR4_UDIMM_H_ +#define IP_PHY_DDR4_UDIMM_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_udimm_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_UDIMM_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm.sh new file mode 100755 index 0000000..0c3429e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm.sh @@ -0,0 +1,182 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_ddr4_udimm.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4_udimm.sh [-help] +# usage: phy_ddr4_udimm.sh [-lib_map_path] +# usage: phy_ddr4_udimm.sh [-noclean_files] +# usage: phy_ddr4_udimm.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_ddr4_udimm.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "phy_ddr4_udimm.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.phy_ddr4_udimm \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4_udimm.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4_udimm.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4_udimm.sh [-help]\n\ +Usage: phy_ddr4_udimm.sh [-lib_map_path]\n\ +Usage: phy_ddr4_udimm.sh [-reset_run]\n\ +Usage: phy_ddr4_udimm.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm_sc.h new file mode 100755 index 0000000..e31f3a2 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/phy_ddr4_udimm_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_UDIMM_SC_H_ +#define IP_PHY_DDR4_UDIMM_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&); + const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&); + +}; + +#endif // IP_PHY_DDR4_UDIMM_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/run.f new file mode 100644 index 0000000..e89fc29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/run.f @@ -0,0 +1,113 @@ +-makelib xcelium_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/microblaze_v11_0_4 \ + "../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd" \ +-endlib +-makelib xcelium_lib/lib_cdc_v1_0_2 \ + "../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ +-endlib +-makelib xcelium_lib/proc_sys_reset_v5_0_13 \ + "../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd" \ +-endlib +-makelib xcelium_lib/lmb_v10_v3_0_11 \ + "../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd" \ +-endlib +-makelib xcelium_lib/lmb_bram_if_cntlr_v4_0_19 \ + "../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v" \ +-endlib +-makelib xcelium_lib/iomodule_v3_1_6 \ + "../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib -sv \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xcelium/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/README.txt new file mode 100644 index 0000000..06ceb3a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:23:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_ddr4_udimm.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_ddr4_udimm.sh' script. + +./phy_ddr4_udimm.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_ddr4_udimm.sh -noclean_files + +For more information on the script, please type './phy_ddr4_udimm.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/U200.smi new file mode 100644 index 0000000..f20b0a8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/U200.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2020.2 (64-bit) --> +<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 --> +<!-- --> +<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 18 2020 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcu200-fsgd2104-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/file_info.txt new file mode 100644 index 0000000..1a16c3d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/file_info.txt @@ -0,0 +1,50 @@ +bd_ba6a_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_second_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a_iomodule_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +bd_ba6a.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_microblaze_mcs.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_phy_v2_2_xiphy_behav.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_phy_v2_2_xiphy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" 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+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +phy_ddr4_udimm.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm.h new file mode 100755 index 0000000..ec2d0cd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm.h @@ -0,0 +1,467 @@ +#ifndef IP_PHY_DDR4_UDIMM_H_ +#define IP_PHY_DDR4_UDIMM_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_ddr4_udimm_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_ddr4_udimm : public phy_ddr4_udimm_sc +{ +public: + + phy_ddr4_udimm(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<512> > wrData; + sc_core::sc_in< sc_dt::sc_bv<64> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<512> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<64> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<8> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_DDR4_UDIMM_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm.sh new file mode 100755 index 0000000..5d62690 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm.sh @@ -0,0 +1,214 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_ddr4_udimm.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:23:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_ddr4_udimm.sh [-help] +# usage: phy_ddr4_udimm.sh [-lib_map_path] +# usage: phy_ddr4_udimm.sh [-noclean_files] +# usage: phy_ddr4_udimm.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0 +xvlog_opts="--relax -L xdma_v4_1_8" +xvhdl_opts="--relax" + + +# Script info +echo -e "phy_ddr4_udimm.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot phy_ddr4_udimm xil_defaultlib.phy_ddr4_udimm xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim phy_ddr4_udimm -key {Behavioral:sim_1:Functional:phy_ddr4_udimm} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4_udimm.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb phy_ddr4_udimm.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4_udimm.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_ddr4_udimm.sh [-help]\n\ +Usage: phy_ddr4_udimm.sh [-lib_map_path]\n\ +Usage: phy_ddr4_udimm.sh [-reset_run]\n\ +Usage: phy_ddr4_udimm.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm_sc.h new file mode 100755 index 0000000..e31f3a2 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/phy_ddr4_udimm_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_DDR4_UDIMM_SC_H_ +#define IP_PHY_DDR4_UDIMM_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_ddr4_udimm_sc : public sc_core::sc_module +{ +public: + + phy_ddr4_udimm_sc(const sc_core::sc_module_name& nm); + virtual ~phy_ddr4_udimm_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_ddr4_udimm_sc(const phy_ddr4_udimm_sc&); + const phy_ddr4_udimm_sc& operator=(const phy_ddr4_udimm_sc&); + +}; + +#endif // IP_PHY_DDR4_UDIMM_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_afa8.protoinst new file mode 100644 index 0000000..a0656b6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_afa8.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_afa8": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_ba6a.protoinst new file mode 100644 index 0000000..c42e1c4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/protoinst_files/bd_ba6a.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_ba6a": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/vhdl.prj b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/vhdl.prj new file mode 100644 index 0000000..a2f5f6c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/vhdl.prj @@ -0,0 +1,12 @@ +vhdl xil_defaultlib \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_0/sim/bd_ba6a_microblaze_I_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_1/sim/bd_ba6a_rst_0_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_2/sim/bd_ba6a_ilmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_3/sim/bd_ba6a_dlmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_4/sim/bd_ba6a_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_5/sim/bd_ba6a_ilmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_7/sim/bd_ba6a_second_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_8/sim/bd_ba6a_second_ilmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_10/sim/bd_ba6a_iomodule_0_0.vhd" \ + +nosort diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/vlog.prj new file mode 100644 index 0000000..6357e2a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_ddr4_udimm/xsim/vlog.prj @@ -0,0 +1,47 @@ +verilog xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_6/sim/bd_ba6a_lmb_bram_I_0.v" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/ip/ip_9/sim/bd_ba6a_second_lmb_bram_I_0.v" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/bd_0/sim/bd_ba6a.v" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_0/sim/phy_ddr4_udimm_microblaze_mcs.v" \ + +sv xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/map" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top" --include "../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/phy_ddr4_udimm_phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/ip_1/rtl/ip_top/phy_ddr4_udimm_phy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/cal/phy_ddr4_udimm_ddr4_cal_riu.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/rtl/ip_top/phy_ddr4_udimm.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_ddr4_udimm/tb/microblaze_mcs_0.sv" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/README.txt new file mode 100644 index 0000000..5acdd2f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/README.txt new file mode 100644 index 0000000..5254a3c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:00 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_rdimm_x8_dual.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_rdimm_x8_dual.sh' script. + +./phy_rdimm_x8_dual.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_rdimm_x8_dual.sh -noclean_files + +For more information on the script, please type './phy_rdimm_x8_dual.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/compile.do new file mode 100644 index 0000000..fd40a0e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/compile.do @@ -0,0 +1,137 @@ +vlib work +vlib activehdl + +vlib activehdl/xilinx_vip +vlib activehdl/xpm +vlib activehdl/microblaze_v11_0_4 +vlib activehdl/xil_defaultlib +vlib activehdl/lib_cdc_v1_0_2 +vlib activehdl/proc_sys_reset_v5_0_13 +vlib activehdl/lmb_v10_v3_0_11 +vlib activehdl/lmb_bram_if_cntlr_v4_0_19 +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/iomodule_v3_1_6 + +vmap xilinx_vip activehdl/xilinx_vip +vmap xpm activehdl/xpm +vmap microblaze_v11_0_4 activehdl/microblaze_v11_0_4 +vmap xil_defaultlib activehdl/xil_defaultlib +vmap lib_cdc_v1_0_2 activehdl/lib_cdc_v1_0_2 +vmap proc_sys_reset_v5_0_13 activehdl/proc_sys_reset_v5_0_13 +vmap lmb_v10_v3_0_11 activehdl/lmb_v10_v3_0_11 +vmap lmb_bram_if_cntlr_v4_0_19 activehdl/lmb_bram_if_cntlr_v4_0_19 +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap iomodule_v3_1_6 activehdl/iomodule_v3_1_6 + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work microblaze_v11_0_4 -93 \ +"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd" \ + +vcom -work lib_cdc_v1_0_2 -93 \ +"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work proc_sys_reset_v5_0_13 -93 \ +"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd" \ + +vcom -work lmb_v10_v3_0_11 -93 \ +"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd" \ + +vcom -work lmb_bram_if_cntlr_v4_0_19 -93 \ +"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v" \ + +vcom -work iomodule_v3_1_6 -93 \ +"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v" \ + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/file_info.txt new file mode 100644 index 0000000..48f86b9 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/file_info.txt @@ -0,0 +1,70 @@ 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+ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" 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+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" 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+phy_rdimm_x8_dual_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" 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+phy_rdimm_x8_dual.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual.h new file mode 100755 index 0000000..ba46738 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual.h @@ -0,0 +1,477 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_H_ +#define IP_PHY_RDIMM_X8_DUAL_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_rdimm_x8_dual_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_RDIMM_X8_DUAL_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual.sh new file mode 100755 index 0000000..20f6be7 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_rdimm_x8_dual.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:00 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_rdimm_x8_dual.sh [-help] +# usage: phy_rdimm_x8_dual.sh [-lib_map_path] +# usage: phy_rdimm_x8_dual.sh [-noclean_files] +# usage: phy_rdimm_x8_dual.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_rdimm_x8_dual.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "phy_rdimm_x8_dual.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_rdimm_x8_dual.sh [-help]\n\ +Usage: phy_rdimm_x8_dual.sh [-lib_map_path]\n\ +Usage: phy_rdimm_x8_dual.sh [-reset_run]\n\ +Usage: phy_rdimm_x8_dual.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual_sc.h new file mode 100755 index 0000000..cdbac59 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/phy_rdimm_x8_dual_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_ +#define IP_PHY_RDIMM_X8_DUAL_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module +{ +public: + + phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&); + const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&); + +}; + +#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/simulate.do new file mode 100644 index 0000000..c364255 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+phy_rdimm_x8_dual -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.phy_rdimm_x8_dual xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {phy_rdimm_x8_dual.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/README.txt new file mode 100644 index 0000000..cad0d93 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:00 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_rdimm_x8_dual.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_rdimm_x8_dual.sh' script. + +./phy_rdimm_x8_dual.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_rdimm_x8_dual.sh -noclean_files + +For more information on the script, please type './phy_rdimm_x8_dual.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/file_info.txt new file mode 100644 index 0000000..1d20825 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" 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+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" 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+bd_afa8_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" 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+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_19,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" 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+ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +phy_rdimm_x8_dual_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +phy_rdimm_x8_dual_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +phy_rdimm_x8_dual.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual.h new file mode 100755 index 0000000..ba46738 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual.h @@ -0,0 +1,477 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_H_ +#define IP_PHY_RDIMM_X8_DUAL_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_rdimm_x8_dual_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_RDIMM_X8_DUAL_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual.sh new file mode 100755 index 0000000..3ff2d6e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual.sh @@ -0,0 +1,182 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_rdimm_x8_dual.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:00 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_rdimm_x8_dual.sh [-help] +# usage: phy_rdimm_x8_dual.sh [-lib_map_path] +# usage: phy_rdimm_x8_dual.sh [-noclean_files] +# usage: phy_rdimm_x8_dual.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_rdimm_x8_dual.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "phy_rdimm_x8_dual.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.phy_rdimm_x8_dual \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_rdimm_x8_dual.sh [-help]\n\ +Usage: phy_rdimm_x8_dual.sh [-lib_map_path]\n\ +Usage: phy_rdimm_x8_dual.sh [-reset_run]\n\ +Usage: phy_rdimm_x8_dual.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual_sc.h new file mode 100755 index 0000000..cdbac59 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/phy_rdimm_x8_dual_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_ +#define IP_PHY_RDIMM_X8_DUAL_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module +{ +public: + + phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&); + const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&); + +}; + +#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/run.f new file mode 100644 index 0000000..5804bac --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/run.f @@ -0,0 +1,113 @@ +-makelib ies_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/microblaze_v11_0_4 \ + "../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd" \ +-endlib +-makelib ies_lib/lib_cdc_v1_0_2 \ + "../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ +-endlib +-makelib ies_lib/proc_sys_reset_v5_0_13 \ + "../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd" \ +-endlib +-makelib ies_lib/lmb_v10_v3_0_11 \ + "../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd" \ +-endlib +-makelib ies_lib/lmb_bram_if_cntlr_v4_0_19 \ + "../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v" \ +-endlib +-makelib ies_lib/iomodule_v3_1_6 \ + "../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v" \ +-endlib +-makelib ies_lib/xil_defaultlib -sv \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/ies/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/README.txt new file mode 100644 index 0000000..5254a3c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:00 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_rdimm_x8_dual.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_rdimm_x8_dual.sh' script. + +./phy_rdimm_x8_dual.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_rdimm_x8_dual.sh -noclean_files + +For more information on the script, please type './phy_rdimm_x8_dual.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/compile.do new file mode 100644 index 0000000..4189b83 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/compile.do @@ -0,0 +1,137 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xilinx_vip +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/microblaze_v11_0_4 +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/lib_cdc_v1_0_2 +vlib modelsim_lib/msim/proc_sys_reset_v5_0_13 +vlib modelsim_lib/msim/lmb_v10_v3_0_11 +vlib modelsim_lib/msim/lmb_bram_if_cntlr_v4_0_19 +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/iomodule_v3_1_6 + +vmap xilinx_vip modelsim_lib/msim/xilinx_vip +vmap xpm modelsim_lib/msim/xpm +vmap microblaze_v11_0_4 modelsim_lib/msim/microblaze_v11_0_4 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap lib_cdc_v1_0_2 modelsim_lib/msim/lib_cdc_v1_0_2 +vmap proc_sys_reset_v5_0_13 modelsim_lib/msim/proc_sys_reset_v5_0_13 +vmap lmb_v10_v3_0_11 modelsim_lib/msim/lmb_v10_v3_0_11 +vmap lmb_bram_if_cntlr_v4_0_19 modelsim_lib/msim/lmb_bram_if_cntlr_v4_0_19 +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap iomodule_v3_1_6 modelsim_lib/msim/iomodule_v3_1_6 + +vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work microblaze_v11_0_4 -64 -93 \ +"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd" \ + +vcom -work lib_cdc_v1_0_2 -64 -93 \ +"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work proc_sys_reset_v5_0_13 -64 -93 \ +"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd" \ + +vcom -work lmb_v10_v3_0_11 -64 -93 \ +"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd" \ + +vcom -work lmb_bram_if_cntlr_v4_0_19 -64 -93 \ +"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v" \ + +vcom -work iomodule_v3_1_6 -64 -93 \ +"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v" \ + +vlog -work xil_defaultlib -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/file_info.txt new file mode 100644 index 0000000..48f86b9 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_11,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" 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/devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual.h new file mode 100755 index 0000000..ba46738 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual.h @@ -0,0 +1,477 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_H_ +#define IP_PHY_RDIMM_X8_DUAL_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_rdimm_x8_dual_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_RDIMM_X8_DUAL_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual.sh new file mode 100755 index 0000000..f6f7bba --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_rdimm_x8_dual.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:00 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_rdimm_x8_dual.sh [-help] +# usage: phy_rdimm_x8_dual.sh [-lib_map_path] +# usage: phy_rdimm_x8_dual.sh [-noclean_files] +# usage: phy_rdimm_x8_dual.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_rdimm_x8_dual.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "phy_rdimm_x8_dual.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_rdimm_x8_dual.sh [-help]\n\ +Usage: phy_rdimm_x8_dual.sh [-lib_map_path]\n\ +Usage: phy_rdimm_x8_dual.sh [-reset_run]\n\ +Usage: phy_rdimm_x8_dual.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual_sc.h new file mode 100755 index 0000000..cdbac59 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/phy_rdimm_x8_dual_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_ +#define IP_PHY_RDIMM_X8_DUAL_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module +{ +public: + + phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&); + const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&); + +}; + +#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/simulate.do new file mode 100644 index 0000000..efa07d3 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.phy_rdimm_x8_dual xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {phy_rdimm_x8_dual.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/README.txt new file mode 100644 index 0000000..5254a3c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:00 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_rdimm_x8_dual.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_rdimm_x8_dual.sh' script. + +./phy_rdimm_x8_dual.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_rdimm_x8_dual.sh -noclean_files + +For more information on the script, please type './phy_rdimm_x8_dual.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/compile.do new file mode 100644 index 0000000..7436bae --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/compile.do @@ -0,0 +1,137 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xilinx_vip +vlib questa_lib/msim/xpm +vlib questa_lib/msim/microblaze_v11_0_4 +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/lib_cdc_v1_0_2 +vlib questa_lib/msim/proc_sys_reset_v5_0_13 +vlib questa_lib/msim/lmb_v10_v3_0_11 +vlib questa_lib/msim/lmb_bram_if_cntlr_v4_0_19 +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/iomodule_v3_1_6 + +vmap xilinx_vip questa_lib/msim/xilinx_vip +vmap xpm questa_lib/msim/xpm +vmap microblaze_v11_0_4 questa_lib/msim/microblaze_v11_0_4 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap lib_cdc_v1_0_2 questa_lib/msim/lib_cdc_v1_0_2 +vmap proc_sys_reset_v5_0_13 questa_lib/msim/proc_sys_reset_v5_0_13 +vmap lmb_v10_v3_0_11 questa_lib/msim/lmb_v10_v3_0_11 +vmap lmb_bram_if_cntlr_v4_0_19 questa_lib/msim/lmb_bram_if_cntlr_v4_0_19 +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap iomodule_v3_1_6 questa_lib/msim/iomodule_v3_1_6 + +vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work microblaze_v11_0_4 -64 -93 \ +"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd" \ + +vcom -work lib_cdc_v1_0_2 -64 -93 \ +"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work proc_sys_reset_v5_0_13 -64 -93 \ +"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd" \ + +vcom -work lmb_v10_v3_0_11 -64 -93 \ +"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd" \ + +vcom -work lmb_bram_if_cntlr_v4_0_19 -64 -93 \ +"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v" \ + +vcom -work iomodule_v3_1_6 -64 -93 \ +"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v" \ + +vlog -work xil_defaultlib -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/elaborate.do new file mode 100644 index 0000000..cc36de1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.phy_rdimm_x8_dual xil_defaultlib.glbl -o phy_rdimm_x8_dual_opt diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/file_info.txt new file mode 100644 index 0000000..48f86b9 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" 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+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +phy_rdimm_x8_dual_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +phy_rdimm_x8_dual_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +phy_rdimm_x8_dual.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual.h new file mode 100755 index 0000000..ba46738 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual.h @@ -0,0 +1,477 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_H_ +#define IP_PHY_RDIMM_X8_DUAL_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_rdimm_x8_dual_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_RDIMM_X8_DUAL_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual.sh new file mode 100755 index 0000000..e3d05fc --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_rdimm_x8_dual.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:00 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_rdimm_x8_dual.sh [-help] +# usage: phy_rdimm_x8_dual.sh [-lib_map_path] +# usage: phy_rdimm_x8_dual.sh [-noclean_files] +# usage: phy_rdimm_x8_dual.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_rdimm_x8_dual.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "phy_rdimm_x8_dual.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_rdimm_x8_dual.sh [-help]\n\ +Usage: phy_rdimm_x8_dual.sh [-lib_map_path]\n\ +Usage: phy_rdimm_x8_dual.sh [-reset_run]\n\ +Usage: phy_rdimm_x8_dual.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual_sc.h new file mode 100755 index 0000000..cdbac59 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/phy_rdimm_x8_dual_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_ +#define IP_PHY_RDIMM_X8_DUAL_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module +{ +public: + + phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&); + const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&); + +}; + +#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/simulate.do new file mode 100644 index 0000000..74f65a1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -lib xil_defaultlib phy_rdimm_x8_dual_opt + +do {wave.do} + +view wave +view structure +view signals + +do {phy_rdimm_x8_dual.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/README.txt new file mode 100644 index 0000000..5254a3c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:00 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_rdimm_x8_dual.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_rdimm_x8_dual.sh' script. + +./phy_rdimm_x8_dual.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_rdimm_x8_dual.sh -noclean_files + +For more information on the script, please type './phy_rdimm_x8_dual.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/compile.do new file mode 100644 index 0000000..4dbd432 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/compile.do @@ -0,0 +1,137 @@ +vlib work +vlib riviera + +vlib riviera/xilinx_vip +vlib riviera/xpm +vlib riviera/microblaze_v11_0_4 +vlib riviera/xil_defaultlib +vlib riviera/lib_cdc_v1_0_2 +vlib riviera/proc_sys_reset_v5_0_13 +vlib riviera/lmb_v10_v3_0_11 +vlib riviera/lmb_bram_if_cntlr_v4_0_19 +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/iomodule_v3_1_6 + +vmap xilinx_vip riviera/xilinx_vip +vmap xpm riviera/xpm +vmap microblaze_v11_0_4 riviera/microblaze_v11_0_4 +vmap xil_defaultlib riviera/xil_defaultlib +vmap lib_cdc_v1_0_2 riviera/lib_cdc_v1_0_2 +vmap proc_sys_reset_v5_0_13 riviera/proc_sys_reset_v5_0_13 +vmap lmb_v10_v3_0_11 riviera/lmb_v10_v3_0_11 +vmap lmb_bram_if_cntlr_v4_0_19 riviera/lmb_bram_if_cntlr_v4_0_19 +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap iomodule_v3_1_6 riviera/iomodule_v3_1_6 + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work microblaze_v11_0_4 -93 \ +"../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd" \ + +vcom -work lib_cdc_v1_0_2 -93 \ +"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work proc_sys_reset_v5_0_13 -93 \ +"../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd" \ + +vcom -work lmb_v10_v3_0_11 -93 \ +"../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd" \ + +vcom -work lmb_bram_if_cntlr_v4_0_19 -93 \ +"../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v" \ + +vcom -work iomodule_v3_1_6 -93 \ +"../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v" \ + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" "+incdir+../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/file_info.txt new file mode 100644 index 0000000..48f86b9 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" 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+ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" 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+phy_rdimm_x8_dual.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv,incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual.h new file mode 100755 index 0000000..ba46738 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual.h @@ -0,0 +1,477 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_H_ +#define IP_PHY_RDIMM_X8_DUAL_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_rdimm_x8_dual_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_RDIMM_X8_DUAL_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual.sh new file mode 100755 index 0000000..d7a697b --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_rdimm_x8_dual.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:00 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_rdimm_x8_dual.sh [-help] +# usage: phy_rdimm_x8_dual.sh [-lib_map_path] +# usage: phy_rdimm_x8_dual.sh [-noclean_files] +# usage: phy_rdimm_x8_dual.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_rdimm_x8_dual.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "phy_rdimm_x8_dual.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_rdimm_x8_dual.sh [-help]\n\ +Usage: phy_rdimm_x8_dual.sh [-lib_map_path]\n\ +Usage: phy_rdimm_x8_dual.sh [-reset_run]\n\ +Usage: phy_rdimm_x8_dual.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual.udo b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual_sc.h new file mode 100755 index 0000000..cdbac59 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/phy_rdimm_x8_dual_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_ +#define IP_PHY_RDIMM_X8_DUAL_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module +{ +public: + + phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&); + const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&); + +}; + +#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/simulate.do new file mode 100644 index 0000000..c364255 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+phy_rdimm_x8_dual -L xilinx_vip -L xpm -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.phy_rdimm_x8_dual xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {phy_rdimm_x8_dual.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/README.txt new file mode 100644 index 0000000..5254a3c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:00 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_rdimm_x8_dual.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_rdimm_x8_dual.sh' script. + +./phy_rdimm_x8_dual.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_rdimm_x8_dual.sh -noclean_files + +For more information on the script, please type './phy_rdimm_x8_dual.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/file_info.txt new file mode 100644 index 0000000..1d20825 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" 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+phy_rdimm_x8_dual_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +phy_rdimm_x8_dual.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual.h new file mode 100755 index 0000000..ba46738 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual.h @@ -0,0 +1,477 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_H_ +#define IP_PHY_RDIMM_X8_DUAL_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_rdimm_x8_dual_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_RDIMM_X8_DUAL_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual.sh new file mode 100755 index 0000000..58ae743 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual.sh @@ -0,0 +1,346 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_rdimm_x8_dual.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:00 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_rdimm_x8_dual.sh [-help] +# usage: phy_rdimm_x8_dual.sh [-lib_map_path] +# usage: phy_rdimm_x8_dual.sh [-noclean_files] +# usage: phy_rdimm_x8_dual.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_rdimm_x8_dual.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "phy_rdimm_x8_dual.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work microblaze_v11_0_4 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work lib_cdc_v1_0_2 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work proc_sys_reset_v5_0_13 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work lmb_v10_v3_0_11 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work lmb_bram_if_cntlr_v4_0_19 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work iomodule_v3_1_6 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.phy_rdimm_x8_dual xil_defaultlib.glbl -o phy_rdimm_x8_dual_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./phy_rdimm_x8_dual_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key phy_rdimm_x8_dual_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc phy_rdimm_x8_dual_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_rdimm_x8_dual.sh [-help]\n\ +Usage: phy_rdimm_x8_dual.sh [-lib_map_path]\n\ +Usage: phy_rdimm_x8_dual.sh [-reset_run]\n\ +Usage: phy_rdimm_x8_dual.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual_sc.h new file mode 100755 index 0000000..cdbac59 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/phy_rdimm_x8_dual_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_ +#define IP_PHY_RDIMM_X8_DUAL_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module +{ +public: + + phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&); + const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&); + +}; + +#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/README.txt new file mode 100644 index 0000000..cad0d93 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:00 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_rdimm_x8_dual.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_rdimm_x8_dual.sh' script. + +./phy_rdimm_x8_dual.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_rdimm_x8_dual.sh -noclean_files + +For more information on the script, please type './phy_rdimm_x8_dual.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/file_info.txt new file mode 100644 index 0000000..1d20825 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/file_info.txt @@ -0,0 +1,70 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_4,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" 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+ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" 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+phy_rdimm_x8_dual_phy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_infrastructure.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_xsdb_bram.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_write.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_wr_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_wr_bit.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_sync.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_read.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_rd_en.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_pi.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_mc_odt.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_debug_microblaze.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_cplx_data.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_cplx.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_config_rom.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_addr_decode.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +phy_rdimm_x8_dual_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +phy_rdimm_x8_dual_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +phy_rdimm_x8_dual.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual.h new file mode 100755 index 0000000..ba46738 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual.h @@ -0,0 +1,477 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_H_ +#define IP_PHY_RDIMM_X8_DUAL_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_rdimm_x8_dual_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_RDIMM_X8_DUAL_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual.sh new file mode 100755 index 0000000..be05b23 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual.sh @@ -0,0 +1,182 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_rdimm_x8_dual.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:00 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_rdimm_x8_dual.sh [-help] +# usage: phy_rdimm_x8_dual.sh [-lib_map_path] +# usage: phy_rdimm_x8_dual.sh [-noclean_files] +# usage: phy_rdimm_x8_dual.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'phy_rdimm_x8_dual.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm microblaze_v11_0_4 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_11 lmb_bram_if_cntlr_v4_0_19 blk_mem_gen_v8_4_4 iomodule_v3_1_6) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "phy_rdimm_x8_dual.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.phy_rdimm_x8_dual \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" \ + +incdir+"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_rdimm_x8_dual.sh [-help]\n\ +Usage: phy_rdimm_x8_dual.sh [-lib_map_path]\n\ +Usage: phy_rdimm_x8_dual.sh [-reset_run]\n\ +Usage: phy_rdimm_x8_dual.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual_sc.h new file mode 100755 index 0000000..cdbac59 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/phy_rdimm_x8_dual_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_ +#define IP_PHY_RDIMM_X8_DUAL_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module +{ +public: + + phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&); + const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&); + +}; + +#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/run.f new file mode 100644 index 0000000..510c873 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/run.f @@ -0,0 +1,113 @@ +-makelib xcelium_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/microblaze_v11_0_4 \ + "../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd" \ +-endlib +-makelib xcelium_lib/lib_cdc_v1_0_2 \ + "../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \ +-endlib +-makelib xcelium_lib/proc_sys_reset_v5_0_13 \ + "../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd" \ +-endlib +-makelib xcelium_lib/lmb_v10_v3_0_11 \ + "../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd" \ +-endlib +-makelib xcelium_lib/lmb_bram_if_cntlr_v4_0_19 \ + "../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v" \ +-endlib +-makelib xcelium_lib/iomodule_v3_1_6 \ + "../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib -sv \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv" \ + "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xcelium/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/README.txt new file mode 100644 index 0000000..5254a3c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:00 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./phy_rdimm_x8_dual.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './phy_rdimm_x8_dual.sh' script. + +./phy_rdimm_x8_dual.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./phy_rdimm_x8_dual.sh -noclean_files + +For more information on the script, please type './phy_rdimm_x8_dual.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/U200.smi new file mode 100644 index 0000000..f20b0a8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/U200.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2020.2 (64-bit) --> +<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 --> +<!-- --> +<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 18 2020 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcu200-fsgd2104-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/file_info.txt new file mode 100644 index 0000000..2119c88 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/file_info.txt @@ -0,0 +1,50 @@ +bd_afa8_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_second_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8_iomodule_0_0.vhd,vhdl,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +bd_afa8.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +phy_rdimm_x8_dual_microblaze_mcs.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +phy_rdimm_x8_dual_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_phy_v2_2_xiphy_behav.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_phy_v2_2_xiphy.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_phy_v2_2_iob_byte.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_phy_v2_2_iob.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_phy_v2_2_pll.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_phy_v2_2_xiphy_control_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +ddr4_phy_v2_2_xiphy_byte_wrapper.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" 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+phy_rdimm_x8_dual_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +phy_rdimm_x8_dual.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top"incdir="../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual.h new file mode 100755 index 0000000..ba46738 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual.h @@ -0,0 +1,477 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_H_ +#define IP_PHY_RDIMM_X8_DUAL_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "phy_rdimm_x8_dual_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +class DllExport phy_rdimm_x8_dual : public phy_rdimm_x8_dual_sc +{ +public: + + phy_rdimm_x8_dual(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual(); + + // module pin-to-pin RTL interface + + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + sc_core::sc_out< sc_dt::sc_bv<512> > dbg_bus; + sc_core::sc_out< bool > c0_ddr4_parity; + sc_core::sc_out< bool > c0_ddr4_ui_clk; + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > sys_rst; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEn; + sc_core::sc_out< sc_dt::sc_bv<1> > rdDataEnd; + sc_core::sc_out< sc_dt::sc_bv<1> > per_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > rmw_rd_done; + sc_core::sc_out< sc_dt::sc_bv<1> > wrDataEn; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ACT_n; + sc_core::sc_in< sc_dt::sc_bv<2> > mcCasSlot; + sc_core::sc_in< sc_dt::sc_bv<1> > mcCasSlot2; + sc_core::sc_in< sc_dt::sc_bv<1> > mcRdCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > mcWrCAS; + sc_core::sc_in< sc_dt::sc_bv<1> > winInjTxn; + sc_core::sc_in< sc_dt::sc_bv<1> > winRmw; + sc_core::sc_in< bool > gt_data_ready; + sc_core::sc_in< sc_dt::sc_bv<2> > winRank; + sc_core::sc_out< sc_dt::sc_bv<6> > tCWL; + sc_core::sc_in< sc_dt::sc_bv<576> > wrData; + sc_core::sc_in< sc_dt::sc_bv<72> > wrDataMask; + sc_core::sc_out< sc_dt::sc_bv<576> > rdData; + sc_core::sc_in< sc_dt::sc_bv<136> > mc_ADR; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BA; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CKE; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_CS_n; + sc_core::sc_in< sc_dt::sc_bv<8> > mc_ODT; + sc_core::sc_in< sc_dt::sc_bv<5> > dBufAdr; + sc_core::sc_out< sc_dt::sc_bv<5> > rdDataAddr; + sc_core::sc_out< sc_dt::sc_bv<5> > wrDataAddr; + sc_core::sc_in< sc_dt::sc_bv<5> > winBuf; + sc_core::sc_out< bool > ddr4_act_n; + sc_core::sc_out< sc_dt::sc_bv<17> > ddr4_adr; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_ba; + sc_core::sc_out< sc_dt::sc_bv<2> > ddr4_bg; + sc_core::sc_out< bool > ddr4_par; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cke; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_odt; + sc_core::sc_out< sc_dt::sc_bv<1> > ddr4_cs_n; + sc_core::sc_out< bool > ddr4_ck_t; + sc_core::sc_out< bool > ddr4_ck_c; + sc_core::sc_out< bool > ddr4_reset_n; + sc_core::sc_out< bool > ddr4_parity; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dm_dbi_n; + sc_core::sc_out< sc_dt::sc_bv<72> > ddr4_dq; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_c; + sc_core::sc_out< sc_dt::sc_bv<9> > ddr4_dqs_t; + sc_core::sc_in< sc_dt::sc_bv<16> > mc_BG; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + + // Transactor stubs + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_PHY_RDIMM_X8_DUAL_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual.sh b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual.sh new file mode 100755 index 0000000..47249e6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual.sh @@ -0,0 +1,214 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : phy_rdimm_x8_dual.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:00 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: phy_rdimm_x8_dual.sh [-help] +# usage: phy_rdimm_x8_dual.sh [-lib_map_path] +# usage: phy_rdimm_x8_dual.sh [-noclean_files] +# usage: phy_rdimm_x8_dual.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0 +xvlog_opts="--relax -L xdma_v4_1_8" +xvhdl_opts="--relax" + + +# Script info +echo -e "phy_rdimm_x8_dual.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L microblaze_v11_0_4 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lmb_v10_v3_0_11 -L lmb_bram_if_cntlr_v4_0_19 -L blk_mem_gen_v8_4_4 -L iomodule_v3_1_6 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot phy_rdimm_x8_dual xil_defaultlib.phy_rdimm_x8_dual xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim phy_rdimm_x8_dual -key {Behavioral:sim_1:Functional:phy_rdimm_x8_dual} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb phy_rdimm_x8_dual.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./phy_rdimm_x8_dual.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: phy_rdimm_x8_dual.sh [-help]\n\ +Usage: phy_rdimm_x8_dual.sh [-lib_map_path]\n\ +Usage: phy_rdimm_x8_dual.sh [-reset_run]\n\ +Usage: phy_rdimm_x8_dual.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual_sc.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual_sc.h new file mode 100755 index 0000000..cdbac59 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/phy_rdimm_x8_dual_sc.h @@ -0,0 +1,94 @@ +#ifndef IP_PHY_RDIMM_X8_DUAL_SC_H_ +#define IP_PHY_RDIMM_X8_DUAL_SC_H_ + +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include <systemc> +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class sim_ddr_v2_0; + +class DllExport phy_rdimm_x8_dual_sc : public sc_core::sc_module +{ +public: + + phy_rdimm_x8_dual_sc(const sc_core::sc_module_name& nm); + virtual ~phy_rdimm_x8_dual_sc(); + + // module socket-to-socket AXI TLM interfaces + + + // module socket-to-socket TLM interfaces + + +protected: + + sim_ddr_v2_0* mp_impl; + +private: + + phy_rdimm_x8_dual_sc(const phy_rdimm_x8_dual_sc&); + const phy_rdimm_x8_dual_sc& operator=(const phy_rdimm_x8_dual_sc&); + +}; + +#endif // IP_PHY_RDIMM_X8_DUAL_SC_H_ diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_afa8.protoinst new file mode 100644 index 0000000..a0656b6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_afa8.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_afa8": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_ba6a.protoinst new file mode 100644 index 0000000..c42e1c4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/protoinst_files/bd_ba6a.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_ba6a": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/sim_ddr_v2_0.h b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/sim_ddr_v2_0.h new file mode 100755 index 0000000..8dc8c75 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/sim_ddr_v2_0.h @@ -0,0 +1,221 @@ +// (c) Copyright(C) 2013 - 2019 by Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +#include "utils/xtlm_cmnhdr.h" +#include "xtlm.h" +#include "report_handler.h" +#include <sstream> +#ifdef SDACCEL_WITH_DATA_CONVERTER +#include "sdaccel_data_converter.h" +#endif +#include "sim_ddrx.h" +#ifdef TLM2_PROTOCOL_CHEKER +#include "tlm2_base_protocol_checker.h" +#endif +#ifndef sim_ddr_v2_0_H +#define sim_ddr_v2_0_H +#include "utils/xsc_stub_port.h" +#include <utils/xtlm_aximm_passthru_module.h> +class sim_ddr_v2_0 :public sc_module{ + public: + explicit sim_ddr_v2_0(sc_core::sc_module_name name, + xsc::common_cpp::properties model_param_props); + ~sim_ddr_v2_0(); + + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_rd_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_wr_socket; + xtlm::xtlm_aximm_target_socket* C0_DDR_SAXI_CTRL_rd_socket; + + xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util; + xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util; + SC_HAS_PROCESS(sim_ddr_v2_0); + +#ifdef SDACCEL_WITH_DATA_CONVERTER + sdaccel_data_converter* sdaccel_data_converter_model; +#endif + +#ifdef TLM2_PROTOCOL_CHEKER + tlm2_base_protocol_checker* checker; +#endif + sc_core::sc_out<bool> c0_ddr4_ui_clk; + sc_core::sc_in<bool> c0_ddr4_aresetn; + sc_core::sc_in<bool> sys_rst; + sc_core::sc_out< bool > c0_init_calib_complete; + sc_core::sc_out< bool > dbg_clk; + sc_core::sc_in< bool > c0_sys_clk_p; + sc_core::sc_in< bool > c0_sys_clk_n; + xsc::utils::xsc_stub_port dbg_bus; + xsc::utils::xsc_stub_port c0_ddr4_adr; + xsc::utils::xsc_stub_port c0_ddr4_ba; + xsc::utils::xsc_stub_port c0_ddr4_cke; + xsc::utils::xsc_stub_port c0_ddr4_cs_n; + xsc::utils::xsc_stub_port c0_ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port c0_ddr4_dq; + xsc::utils::xsc_stub_port c0_ddr4_dqs_c; + xsc::utils::xsc_stub_port c0_ddr4_dqs_t; + xsc::utils::xsc_stub_port c0_ddr4_odt; + xsc::utils::xsc_stub_port c0_ddr4_bg; + xsc::utils::xsc_stub_port c0_ddr4_parity; + xsc::utils::xsc_stub_port c0_ddr4_reset_n; + xsc::utils::xsc_stub_port c0_ddr4_act_n; + xsc::utils::xsc_stub_port c0_ddr4_ck_c; + xsc::utils::xsc_stub_port c0_ddr4_ck_t; + xsc::utils::xsc_stub_port c0_ddr4_interrupt; + xsc::utils::xsc_stub_port addn_ui_clkout1; + xsc::utils::xsc_stub_port dbg_rd_data_cmp; + xsc::utils::xsc_stub_port dbg_expected_data; + xsc::utils::xsc_stub_port dbg_cal_seq; + xsc::utils::xsc_stub_port dbg_cal_seq_cnt; + xsc::utils::xsc_stub_port dbg_cal_seq_rd_cnt; + xsc::utils::xsc_stub_port dbg_rd_valid; + xsc::utils::xsc_stub_port dbg_cmp_byte; + xsc::utils::xsc_stub_port dbg_rd_data; + xsc::utils::xsc_stub_port dbg_cplx_config; + xsc::utils::xsc_stub_port dbg_cplx_status; + xsc::utils::xsc_stub_port dbg_io_address; + xsc::utils::xsc_stub_port dbg_pllGate; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_fixdly_rdy_upp; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_low; + xsc::utils::xsc_stub_port dbg_phy2clb_phy_rdy_upp; + xsc::utils::xsc_stub_port cal_r0_status; + xsc::utils::xsc_stub_port cal_post_status; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ce; + xsc::utils::xsc_stub_port c0_ddr4_mcs_lmb_ue; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_sref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_en; + xsc::utils::xsc_stub_port c0_ddr4_app_restore_complete; + xsc::utils::xsc_stub_port c0_ddr4_app_mem_init_skip; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_select; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_en; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_wr_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_xsdb_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_dbg_out; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_req; + xsc::utils::xsc_stub_port c0_ddr4_app_ref_ack; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_req; + xsc::utils::xsc_stub_port c0_ddr4_app_zq_ack; + xsc::utils::xsc_stub_port c0_ddr4_restore_crc_error; + xsc::utils::xsc_stub_port c0_ddr4_app_addr; + xsc::utils::xsc_stub_port c0_ddr4_app_cmd; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_data; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_mask; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data; + xsc::utils::xsc_stub_port c0_ddr4_app_en; + xsc::utils::xsc_stub_port c0_ddr4_app_hi_pri; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_end; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_wren; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_end; + xsc::utils::xsc_stub_port c0_ddr4_app_rd_data_valid; + xsc::utils::xsc_stub_port c0_ddr4_app_rdy; + xsc::utils::xsc_stub_port c0_ddr4_app_wdf_rdy; + xsc::utils::xsc_stub_port rdDataEn; + xsc::utils::xsc_stub_port rdDataEnd; + xsc::utils::xsc_stub_port per_rd_done; + xsc::utils::xsc_stub_port rmw_rd_done; + xsc::utils::xsc_stub_port wrDataEn; + xsc::utils::xsc_stub_port mc_ACT_n; + xsc::utils::xsc_stub_port mcCasSlot; + xsc::utils::xsc_stub_port mcCasSlot2; + xsc::utils::xsc_stub_port mcRdCAS; + xsc::utils::xsc_stub_port mcWrCAS; + xsc::utils::xsc_stub_port winInjTxn; + xsc::utils::xsc_stub_port winRmw; + xsc::utils::xsc_stub_port gt_data_ready; + xsc::utils::xsc_stub_port winRank; + xsc::utils::xsc_stub_port tCWL; + xsc::utils::xsc_stub_port wrData; + xsc::utils::xsc_stub_port wrDataMask; + xsc::utils::xsc_stub_port rdData; + xsc::utils::xsc_stub_port mc_ADR; + xsc::utils::xsc_stub_port mc_BA; + xsc::utils::xsc_stub_port mc_CKE; + xsc::utils::xsc_stub_port mc_CS_n; + xsc::utils::xsc_stub_port mc_ODT; + xsc::utils::xsc_stub_port dBufAdr; + xsc::utils::xsc_stub_port rdDataAddr; + xsc::utils::xsc_stub_port wrDataAddr; + xsc::utils::xsc_stub_port winBuf; + xsc::utils::xsc_stub_port ddr4_act_n; + xsc::utils::xsc_stub_port ddr4_adr; + xsc::utils::xsc_stub_port ddr4_ba; + xsc::utils::xsc_stub_port ddr4_bg; + xsc::utils::xsc_stub_port ddr4_par; + xsc::utils::xsc_stub_port ddr4_cke; + xsc::utils::xsc_stub_port ddr4_odt; + xsc::utils::xsc_stub_port ddr4_cs_n; + xsc::utils::xsc_stub_port ddr4_ck_t; + xsc::utils::xsc_stub_port ddr4_ck_c; + xsc::utils::xsc_stub_port ddr4_reset_n; + xsc::utils::xsc_stub_port ddr4_dm_dbi_n; + xsc::utils::xsc_stub_port ddr4_dq; + xsc::utils::xsc_stub_port ddr4_dqs_c; + xsc::utils::xsc_stub_port ddr4_dqs_t; + xsc::utils::xsc_stub_port mc_BG; + + sc_core::sc_out< bool > c0_ddr4_ui_clk_sync_rst; + sc_core::sc_in< bool > c0_sys_clk_i; + sc_core::sc_signal<bool>out1; + sc_core::sc_signal<bool>out2; + xsc::common_cpp::report_handler* m_report_handler; + std::stringstream m_ss; + float clk; + void generateReset(); + protected: + + private: + xsc::sim_ddr_v1_0::sim_ddrx * ddrx_top_tlm_model; + + std::map<std::string, int> user_param_int; + std::map<std::string, std::string> user_param_string; + +}; +#endif + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/vhdl.prj b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/vhdl.prj new file mode 100644 index 0000000..0382c33 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/vhdl.prj @@ -0,0 +1,12 @@ +vhdl xil_defaultlib \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_0/sim/bd_afa8_microblaze_I_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_1/sim/bd_afa8_rst_0_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_2/sim/bd_afa8_ilmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_3/sim/bd_afa8_dlmb_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_4/sim/bd_afa8_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_5/sim/bd_afa8_ilmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_7/sim/bd_afa8_second_dlmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_8/sim/bd_afa8_second_ilmb_cntlr_0.vhd" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_10/sim/bd_afa8_iomodule_0_0.vhd" \ + +nosort diff --git a/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/vlog.prj new file mode 100644 index 0000000..fdcf685 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/phy_rdimm_x8_dual/xsim/vlog.prj @@ -0,0 +1,47 @@ +verilog xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" --include "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" --include "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_6/sim/bd_afa8_lmb_bram_I_0.v" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/ip/ip_9/sim/bd_afa8_second_lmb_bram_I_0.v" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/bd_0/sim/bd_afa8.v" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_0/sim/phy_rdimm_x8_dual_microblaze_mcs.v" \ + +sv xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/map" --include "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top" --include "../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/phy_rdimm_x8_dual_phy_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/ip_1/rtl/ip_top/phy_rdimm_x8_dual_phy.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/clocking/ddr4_v2_2_infrastructure.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_write.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_sync.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_read.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_pi.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_cplx.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_top.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_cal.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/ddr4_v2_2_dp_AB9.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual_ddr4.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/cal/phy_rdimm_x8_dual_ddr4_cal_riu.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/rtl/ip_top/phy_rdimm_x8_dual.sv" \ +"../../../../U200.srcs/sources_1/ip/phy_rdimm_x8_dual/tb/microblaze_mcs_0.sv" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/README.txt new file mode 100644 index 0000000..5acdd2f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/README.txt new file mode 100644 index 0000000..f904239 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:17 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_read_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_read_mem.sh' script. + +./pr_read_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_read_mem.sh -noclean_files + +For more information on the script, please type './pr_read_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/compile.do new file mode 100644 index 0000000..b1b6b86 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/compile.do @@ -0,0 +1,41 @@ +vlib work +vlib activehdl + +vlib activehdl/xilinx_vip +vlib activehdl/xpm +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/xil_defaultlib + +vmap xilinx_vip activehdl/xilinx_vip +vmap xpm activehdl/xpm +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/file_info.txt new file mode 100644 index 0000000..00864a6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_read_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read.coe new file mode 100755 index 0000000..b9ccb93 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.mif new file mode 100755 index 0000000..ef3787e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.mif @@ -0,0 +1,13 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010000000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001011000001100101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001001000001000101 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.sh new file mode 100755 index 0000000..1435f6c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : pr_read_mem.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:17 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_read_mem.sh [-help] +# usage: pr_read_mem.sh [-lib_map_path] +# usage: pr_read_mem.sh [-noclean_files] +# usage: pr_read_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_read_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_read_mem.sh [-help]\n\ +Usage: pr_read_mem.sh [-lib_map_path]\n\ +Usage: pr_read_mem.sh [-reset_run]\n\ +Usage: pr_read_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/pr_read_mem.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/simulate.do new file mode 100644 index 0000000..357f2a3 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+pr_read_mem -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.pr_read_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {pr_read_mem.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/summary.log new file mode 100755 index 0000000..abd7c4a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [16] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/README.txt new file mode 100644 index 0000000..d5ba57d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:17 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_read_mem.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_read_mem.sh' script. + +./pr_read_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_read_mem.sh -noclean_files + +For more information on the script, please type './pr_read_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/file_info.txt new file mode 100644 index 0000000..00864a6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_read_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read.coe new file mode 100755 index 0000000..b9ccb93 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.mif new file mode 100755 index 0000000..ef3787e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.mif @@ -0,0 +1,13 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010000000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001011000001100101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001001000001000101 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.sh new file mode 100755 index 0000000..be93888 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/pr_read_mem.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : pr_read_mem.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:17 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_read_mem.sh [-help] +# usage: pr_read_mem.sh [-lib_map_path] +# usage: pr_read_mem.sh [-noclean_files] +# usage: pr_read_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_read_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.pr_read_mem \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_read_mem.sh [-help]\n\ +Usage: pr_read_mem.sh [-lib_map_path]\n\ +Usage: pr_read_mem.sh [-reset_run]\n\ +Usage: pr_read_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/run.f new file mode 100644 index 0000000..ea2704b --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/run.f @@ -0,0 +1,29 @@ +-makelib ies_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/summary.log new file mode 100755 index 0000000..abd7c4a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/ies/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [16] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/README.txt new file mode 100644 index 0000000..f904239 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:17 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_read_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_read_mem.sh' script. + +./pr_read_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_read_mem.sh -noclean_files + +For more information on the script, please type './pr_read_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/compile.do new file mode 100644 index 0000000..83f62b1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/compile.do @@ -0,0 +1,41 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xilinx_vip +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xilinx_vip modelsim_lib/msim/xilinx_vip +vmap xpm modelsim_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/file_info.txt new file mode 100644 index 0000000..00864a6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_read_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read.coe new file mode 100755 index 0000000..b9ccb93 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.mif new file mode 100755 index 0000000..ef3787e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.mif @@ -0,0 +1,13 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010000000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001011000001100101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001001000001000101 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.sh new file mode 100755 index 0000000..6b34932 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : pr_read_mem.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:17 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_read_mem.sh [-help] +# usage: pr_read_mem.sh [-lib_map_path] +# usage: pr_read_mem.sh [-noclean_files] +# usage: pr_read_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_read_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_read_mem.sh [-help]\n\ +Usage: pr_read_mem.sh [-lib_map_path]\n\ +Usage: pr_read_mem.sh [-reset_run]\n\ +Usage: pr_read_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/pr_read_mem.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/simulate.do new file mode 100644 index 0000000..9dd5de1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.pr_read_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {pr_read_mem.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/summary.log new file mode 100755 index 0000000..abd7c4a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [16] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/README.txt new file mode 100644 index 0000000..f904239 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:17 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_read_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_read_mem.sh' script. + +./pr_read_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_read_mem.sh -noclean_files + +For more information on the script, please type './pr_read_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/compile.do new file mode 100644 index 0000000..ddbc2f1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/compile.do @@ -0,0 +1,41 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xilinx_vip +vlib questa_lib/msim/xpm +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/xil_defaultlib + +vmap xilinx_vip questa_lib/msim/xilinx_vip +vmap xpm questa_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/elaborate.do new file mode 100644 index 0000000..443408f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.pr_read_mem xil_defaultlib.glbl -o pr_read_mem_opt diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/file_info.txt new file mode 100644 index 0000000..00864a6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_read_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read.coe new file mode 100755 index 0000000..b9ccb93 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.mif new file mode 100755 index 0000000..ef3787e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.mif @@ -0,0 +1,13 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010000000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001011000001100101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001001000001000101 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.sh new file mode 100755 index 0000000..6a63354 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : pr_read_mem.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:17 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_read_mem.sh [-help] +# usage: pr_read_mem.sh [-lib_map_path] +# usage: pr_read_mem.sh [-noclean_files] +# usage: pr_read_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_read_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_read_mem.sh [-help]\n\ +Usage: pr_read_mem.sh [-lib_map_path]\n\ +Usage: pr_read_mem.sh [-reset_run]\n\ +Usage: pr_read_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/pr_read_mem.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/simulate.do new file mode 100644 index 0000000..4989f3c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -lib xil_defaultlib pr_read_mem_opt + +do {wave.do} + +view wave +view structure +view signals + +do {pr_read_mem.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/summary.log new file mode 100755 index 0000000..abd7c4a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [16] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/README.txt new file mode 100644 index 0000000..f904239 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:17 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_read_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_read_mem.sh' script. + +./pr_read_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_read_mem.sh -noclean_files + +For more information on the script, please type './pr_read_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/compile.do new file mode 100644 index 0000000..6800dfd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/compile.do @@ -0,0 +1,41 @@ +vlib work +vlib riviera + +vlib riviera/xilinx_vip +vlib riviera/xpm +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/xil_defaultlib + +vmap xilinx_vip riviera/xilinx_vip +vmap xpm riviera/xpm +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/file_info.txt new file mode 100644 index 0000000..00864a6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_read_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read.coe new file mode 100755 index 0000000..b9ccb93 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.mif new file mode 100755 index 0000000..ef3787e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.mif @@ -0,0 +1,13 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010000000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001011000001100101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001001000001000101 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.sh new file mode 100755 index 0000000..afc4fb3 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : pr_read_mem.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:17 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_read_mem.sh [-help] +# usage: pr_read_mem.sh [-lib_map_path] +# usage: pr_read_mem.sh [-noclean_files] +# usage: pr_read_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_read_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_read_mem.sh [-help]\n\ +Usage: pr_read_mem.sh [-lib_map_path]\n\ +Usage: pr_read_mem.sh [-reset_run]\n\ +Usage: pr_read_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/pr_read_mem.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/simulate.do new file mode 100644 index 0000000..357f2a3 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+pr_read_mem -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.pr_read_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {pr_read_mem.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/summary.log new file mode 100755 index 0000000..abd7c4a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [16] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/README.txt new file mode 100644 index 0000000..f904239 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:17 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_read_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_read_mem.sh' script. + +./pr_read_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_read_mem.sh -noclean_files + +For more information on the script, please type './pr_read_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/file_info.txt new file mode 100644 index 0000000..00864a6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_read_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read.coe new file mode 100755 index 0000000..b9ccb93 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.mif new file mode 100755 index 0000000..ef3787e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.mif @@ -0,0 +1,13 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010000000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001011000001100101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001001000001000101 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.sh new file mode 100755 index 0000000..32e2dec --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/pr_read_mem.sh @@ -0,0 +1,247 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : pr_read_mem.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:17 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_read_mem.sh [-help] +# usage: pr_read_mem.sh [-lib_map_path] +# usage: pr_read_mem.sh [-noclean_files] +# usage: pr_read_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_read_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xpm $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.pr_read_mem xil_defaultlib.glbl -o pr_read_mem_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./pr_read_mem_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key pr_read_mem_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc pr_read_mem_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_read_mem.sh [-help]\n\ +Usage: pr_read_mem.sh [-lib_map_path]\n\ +Usage: pr_read_mem.sh [-reset_run]\n\ +Usage: pr_read_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/summary.log new file mode 100755 index 0000000..abd7c4a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/vcs/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [16] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/README.txt new file mode 100644 index 0000000..d5ba57d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:17 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_read_mem.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_read_mem.sh' script. + +./pr_read_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_read_mem.sh -noclean_files + +For more information on the script, please type './pr_read_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/file_info.txt new file mode 100644 index 0000000..00864a6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_read_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read.coe new file mode 100755 index 0000000..b9ccb93 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.mif new file mode 100755 index 0000000..ef3787e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.mif @@ -0,0 +1,13 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010000000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001011000001100101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001001000001000101 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.sh new file mode 100755 index 0000000..efe3f37 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/pr_read_mem.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : pr_read_mem.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:17 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_read_mem.sh [-help] +# usage: pr_read_mem.sh [-lib_map_path] +# usage: pr_read_mem.sh [-noclean_files] +# usage: pr_read_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_read_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.pr_read_mem \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_read_mem.sh [-help]\n\ +Usage: pr_read_mem.sh [-lib_map_path]\n\ +Usage: pr_read_mem.sh [-reset_run]\n\ +Usage: pr_read_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/run.f new file mode 100644 index 0000000..c99cd33 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/run.f @@ -0,0 +1,29 @@ +-makelib xcelium_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/summary.log new file mode 100755 index 0000000..abd7c4a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xcelium/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [16] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/README.txt new file mode 100644 index 0000000..f904239 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:17 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_read_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_read_mem.sh' script. + +./pr_read_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_read_mem.sh -noclean_files + +For more information on the script, please type './pr_read_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/U200.smi new file mode 100644 index 0000000..f20b0a8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/U200.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2020.2 (64-bit) --> +<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 --> +<!-- --> +<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 18 2020 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcu200-fsgd2104-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/file_info.txt new file mode 100644 index 0000000..8baa891 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/file_info.txt @@ -0,0 +1,2 @@ +pr_read_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read.coe new file mode 100755 index 0000000..b9ccb93 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read.coe @@ -0,0 +1,15 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010000000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001011000001100101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001001000001000101, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.mif new file mode 100755 index 0000000..ef3787e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.mif @@ -0,0 +1,13 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010000000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001011000001100101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001001000001000101 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.sh new file mode 100755 index 0000000..532cd8d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/pr_read_mem.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : pr_read_mem.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:17 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_read_mem.sh [-help] +# usage: pr_read_mem.sh [-lib_map_path] +# usage: pr_read_mem.sh [-noclean_files] +# usage: pr_read_mem.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0 +xvlog_opts="--relax -L xdma_v4_1_8" + + +# Script info +echo -e "pr_read_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pr_read_mem xil_defaultlib.pr_read_mem xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim pr_read_mem -key {Behavioral:sim_1:Functional:pr_read_mem} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb pr_read_mem.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_read_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_read_mem.sh [-help]\n\ +Usage: pr_read_mem.sh [-lib_map_path]\n\ +Usage: pr_read_mem.sh [-reset_run]\n\ +Usage: pr_read_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_afa8.protoinst new file mode 100644 index 0000000..a0656b6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_afa8.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_afa8": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_ba6a.protoinst new file mode 100644 index 0000000..c42e1c4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/protoinst_files/bd_ba6a.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_ba6a": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/summary.log new file mode 100755 index 0000000..abd7c4a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [16] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/vlog.prj new file mode 100644 index 0000000..47ef914 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/README.txt new file mode 100644 index 0000000..5acdd2f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/README.txt new file mode 100644 index 0000000..2983911 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:30 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_ref_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_ref_mem.sh' script. + +./pr_ref_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_ref_mem.sh -noclean_files + +For more information on the script, please type './pr_ref_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/compile.do new file mode 100644 index 0000000..24a4914 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/compile.do @@ -0,0 +1,41 @@ +vlib work +vlib activehdl + +vlib activehdl/xilinx_vip +vlib activehdl/xpm +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/xil_defaultlib + +vmap xilinx_vip activehdl/xilinx_vip +vmap xpm activehdl/xpm +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/file_info.txt new file mode 100644 index 0000000..b74ac4e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_ref_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref.coe new file mode 100755 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, 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+0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001101000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 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+1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.sh new file mode 100755 index 0000000..2c4cb46 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : pr_ref_mem.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:30 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_ref_mem.sh [-help] +# usage: pr_ref_mem.sh [-lib_map_path] +# usage: pr_ref_mem.sh [-noclean_files] +# usage: pr_ref_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_ref_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_ref_mem.sh [-help]\n\ +Usage: pr_ref_mem.sh [-lib_map_path]\n\ +Usage: pr_ref_mem.sh [-reset_run]\n\ +Usage: pr_ref_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/pr_ref_mem.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/simulate.do new file mode 100644 index 0000000..991d7aa --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+pr_ref_mem -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.pr_ref_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {pr_ref_mem.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/README.txt new file mode 100644 index 0000000..aeafe09 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:30 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_ref_mem.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_ref_mem.sh' script. + +./pr_ref_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_ref_mem.sh -noclean_files + +For more information on the script, please type './pr_ref_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/file_info.txt new file mode 100644 index 0000000..b74ac4e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_ref_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref.coe new file mode 100755 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.mif new file mode 100755 index 0000000..b3e8583 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.mif @@ -0,0 +1,49 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001101000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.sh new file mode 100755 index 0000000..e5319c6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/pr_ref_mem.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : pr_ref_mem.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:30 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_ref_mem.sh [-help] +# usage: pr_ref_mem.sh [-lib_map_path] +# usage: pr_ref_mem.sh [-noclean_files] +# usage: pr_ref_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_ref_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.pr_ref_mem \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_ref_mem.sh [-help]\n\ +Usage: pr_ref_mem.sh [-lib_map_path]\n\ +Usage: pr_ref_mem.sh [-reset_run]\n\ +Usage: pr_ref_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/run.f new file mode 100644 index 0000000..1b0ab35 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/run.f @@ -0,0 +1,29 @@ +-makelib ies_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/ies/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/README.txt new file mode 100644 index 0000000..2983911 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:30 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_ref_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_ref_mem.sh' script. + +./pr_ref_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_ref_mem.sh -noclean_files + +For more information on the script, please type './pr_ref_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/compile.do new file mode 100644 index 0000000..86720f7 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/compile.do @@ -0,0 +1,41 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xilinx_vip +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xilinx_vip modelsim_lib/msim/xilinx_vip +vmap xpm modelsim_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/file_info.txt new file mode 100644 index 0000000..b74ac4e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_ref_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref.coe new file mode 100755 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, 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+1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.mif new file mode 100755 index 0000000..b3e8583 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.mif @@ -0,0 +1,49 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001101000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.sh new file mode 100755 index 0000000..de1374e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : pr_ref_mem.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:30 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_ref_mem.sh [-help] +# usage: pr_ref_mem.sh [-lib_map_path] +# usage: pr_ref_mem.sh [-noclean_files] +# usage: pr_ref_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_ref_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_ref_mem.sh [-help]\n\ +Usage: pr_ref_mem.sh [-lib_map_path]\n\ +Usage: pr_ref_mem.sh [-reset_run]\n\ +Usage: pr_ref_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/pr_ref_mem.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/simulate.do new file mode 100644 index 0000000..f3e4fcd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.pr_ref_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {pr_ref_mem.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/README.txt new file mode 100644 index 0000000..2983911 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:30 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_ref_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_ref_mem.sh' script. + +./pr_ref_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_ref_mem.sh -noclean_files + +For more information on the script, please type './pr_ref_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/compile.do new file mode 100644 index 0000000..e4871d4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/compile.do @@ -0,0 +1,41 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xilinx_vip +vlib questa_lib/msim/xpm +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/xil_defaultlib + +vmap xilinx_vip questa_lib/msim/xilinx_vip +vmap xpm questa_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/elaborate.do new file mode 100644 index 0000000..c4c1bb4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.pr_ref_mem xil_defaultlib.glbl -o pr_ref_mem_opt diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/file_info.txt new file mode 100644 index 0000000..b74ac4e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_ref_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref.coe new file mode 100755 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, 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+1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.mif new file mode 100755 index 0000000..b3e8583 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.mif @@ -0,0 +1,49 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 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+1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.sh new file mode 100755 index 0000000..ffb79d8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : pr_ref_mem.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:30 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_ref_mem.sh [-help] +# usage: pr_ref_mem.sh [-lib_map_path] +# usage: pr_ref_mem.sh [-noclean_files] +# usage: pr_ref_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_ref_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_ref_mem.sh [-help]\n\ +Usage: pr_ref_mem.sh [-lib_map_path]\n\ +Usage: pr_ref_mem.sh [-reset_run]\n\ +Usage: pr_ref_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/pr_ref_mem.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/simulate.do new file mode 100644 index 0000000..44c93df --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -lib xil_defaultlib pr_ref_mem_opt + +do {wave.do} + +view wave +view structure +view signals + +do {pr_ref_mem.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/README.txt new file mode 100644 index 0000000..2983911 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:30 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_ref_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_ref_mem.sh' script. + +./pr_ref_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_ref_mem.sh -noclean_files + +For more information on the script, please type './pr_ref_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/compile.do new file mode 100644 index 0000000..115a790 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/compile.do @@ -0,0 +1,41 @@ +vlib work +vlib riviera + +vlib riviera/xilinx_vip +vlib riviera/xpm +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/xil_defaultlib + +vmap xilinx_vip riviera/xilinx_vip +vmap xpm riviera/xpm +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/file_info.txt new file mode 100644 index 0000000..b74ac4e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_ref_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref.coe new file mode 100755 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, 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+0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001101000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.sh new file mode 100755 index 0000000..5803e51 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : pr_ref_mem.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:30 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_ref_mem.sh [-help] +# usage: pr_ref_mem.sh [-lib_map_path] +# usage: pr_ref_mem.sh [-noclean_files] +# usage: pr_ref_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_ref_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_ref_mem.sh [-help]\n\ +Usage: pr_ref_mem.sh [-lib_map_path]\n\ +Usage: pr_ref_mem.sh [-reset_run]\n\ +Usage: pr_ref_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/pr_ref_mem.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/simulate.do new file mode 100644 index 0000000..991d7aa --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+pr_ref_mem -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.pr_ref_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {pr_ref_mem.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/README.txt new file mode 100644 index 0000000..2983911 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:30 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_ref_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_ref_mem.sh' script. + +./pr_ref_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_ref_mem.sh -noclean_files + +For more information on the script, please type './pr_ref_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/file_info.txt new file mode 100644 index 0000000..b74ac4e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_ref_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref.coe new file mode 100755 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.mif new file mode 100755 index 0000000..b3e8583 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.mif @@ -0,0 +1,49 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001101000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.sh new file mode 100755 index 0000000..faec53d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/pr_ref_mem.sh @@ -0,0 +1,247 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : pr_ref_mem.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:30 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_ref_mem.sh [-help] +# usage: pr_ref_mem.sh [-lib_map_path] +# usage: pr_ref_mem.sh [-noclean_files] +# usage: pr_ref_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_ref_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xpm $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.pr_ref_mem xil_defaultlib.glbl -o pr_ref_mem_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./pr_ref_mem_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key pr_ref_mem_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc pr_ref_mem_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_ref_mem.sh [-help]\n\ +Usage: pr_ref_mem.sh [-lib_map_path]\n\ +Usage: pr_ref_mem.sh [-reset_run]\n\ +Usage: pr_ref_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/vcs/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/README.txt new file mode 100644 index 0000000..aeafe09 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:30 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_ref_mem.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_ref_mem.sh' script. + +./pr_ref_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_ref_mem.sh -noclean_files + +For more information on the script, please type './pr_ref_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/file_info.txt new file mode 100644 index 0000000..b74ac4e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +pr_ref_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref.coe new file mode 100755 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.mif new file mode 100755 index 0000000..b3e8583 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.mif @@ -0,0 +1,49 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001101000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.sh new file mode 100755 index 0000000..d8ba376 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/pr_ref_mem.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : pr_ref_mem.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:30 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_ref_mem.sh [-help] +# usage: pr_ref_mem.sh [-lib_map_path] +# usage: pr_ref_mem.sh [-noclean_files] +# usage: pr_ref_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'pr_ref_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.pr_ref_mem \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_ref_mem.sh [-help]\n\ +Usage: pr_ref_mem.sh [-lib_map_path]\n\ +Usage: pr_ref_mem.sh [-reset_run]\n\ +Usage: pr_ref_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/run.f new file mode 100644 index 0000000..9e68376 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/run.f @@ -0,0 +1,29 @@ +-makelib xcelium_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xcelium/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/README.txt new file mode 100644 index 0000000..2983911 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:30 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./pr_ref_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './pr_ref_mem.sh' script. + +./pr_ref_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./pr_ref_mem.sh -noclean_files + +For more information on the script, please type './pr_ref_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/U200.smi new file mode 100644 index 0000000..f20b0a8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/U200.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2020.2 (64-bit) --> +<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 --> +<!-- --> +<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 18 2020 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcu200-fsgd2104-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/file_info.txt new file mode 100644 index 0000000..ff9f878 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/file_info.txt @@ -0,0 +1,2 @@ +pr_ref_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref.coe b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref.coe new file mode 100755 index 0000000..8b0a9e1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref.coe @@ -0,0 +1,51 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001101000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.mif new file mode 100755 index 0000000..b3e8583 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.mif @@ -0,0 +1,49 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001101000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.sh new file mode 100755 index 0000000..04a3dfb --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/pr_ref_mem.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : pr_ref_mem.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:30 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: pr_ref_mem.sh [-help] +# usage: pr_ref_mem.sh [-lib_map_path] +# usage: pr_ref_mem.sh [-noclean_files] +# usage: pr_ref_mem.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0 +xvlog_opts="--relax -L xdma_v4_1_8" + + +# Script info +echo -e "pr_ref_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pr_ref_mem xil_defaultlib.pr_ref_mem xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim pr_ref_mem -key {Behavioral:sim_1:Functional:pr_ref_mem} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb pr_ref_mem.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./pr_ref_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: pr_ref_mem.sh [-help]\n\ +Usage: pr_ref_mem.sh [-lib_map_path]\n\ +Usage: pr_ref_mem.sh [-reset_run]\n\ +Usage: pr_ref_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_afa8.protoinst new file mode 100644 index 0000000..a0656b6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_afa8.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_afa8": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_ba6a.protoinst new file mode 100644 index 0000000..c42e1c4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/protoinst_files/bd_ba6a.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_ba6a": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/vlog.prj new file mode 100644 index 0000000..c886734 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/pr_ref_mem/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../../U200.srcs/sources_1/ip/pr_ref_mem/sim/pr_ref_mem.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/README.txt new file mode 100644 index 0000000..5acdd2f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/README.txt new file mode 100644 index 0000000..6aedcac --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/compile.do new file mode 100644 index 0000000..16739bc --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/compile.do @@ -0,0 +1,47 @@ +vlib work +vlib activehdl + +vlib activehdl/xilinx_vip +vlib activehdl/xpm +vlib activehdl/fifo_generator_v13_2_5 +vlib activehdl/xil_defaultlib + +vmap xilinx_vip activehdl/xilinx_vip +vmap xpm activehdl/xpm +vmap fifo_generator_v13_2_5 activehdl/fifo_generator_v13_2_5 +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work fifo_generator_v13_2_5 -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + +vcom -work fifo_generator_v13_2_5 -93 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + +vlog -work fifo_generator_v13_2_5 -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/file_info.txt new file mode 100644 index 0000000..b3bd811 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/file_info.txt @@ -0,0 +1,18 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/rdback_fifo.sh new file mode 100755 index 0000000..e6fa5c8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/rdback_fifo.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rdback_fifo.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/rdback_fifo.udo b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/rdback_fifo.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/rdback_fifo.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/simulate.do new file mode 100644 index 0000000..85b1785 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+rdback_fifo -L xilinx_vip -L xpm -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.rdback_fifo xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {rdback_fifo.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/README.txt new file mode 100644 index 0000000..66cb393 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/file_info.txt new file mode 100644 index 0000000..b3bd811 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/file_info.txt @@ -0,0 +1,18 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/rdback_fifo.sh new file mode 100755 index 0000000..4e1e027 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/rdback_fifo.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rdback_fifo.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm fifo_generator_v13_2_5 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.rdback_fifo \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/run.f new file mode 100644 index 0000000..67477c0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/ies/run.f @@ -0,0 +1,35 @@ +-makelib ies_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/fifo_generator_v13_2_5 \ + "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ +-endlib +-makelib ies_lib/fifo_generator_v13_2_5 \ + "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ +-endlib +-makelib ies_lib/fifo_generator_v13_2_5 \ + "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/README.txt new file mode 100644 index 0000000..6aedcac --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/compile.do new file mode 100644 index 0000000..2a07e86 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/compile.do @@ -0,0 +1,47 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xilinx_vip +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/fifo_generator_v13_2_5 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xilinx_vip modelsim_lib/msim/xilinx_vip +vmap xpm modelsim_lib/msim/xpm +vmap fifo_generator_v13_2_5 modelsim_lib/msim/fifo_generator_v13_2_5 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work fifo_generator_v13_2_5 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + +vcom -work fifo_generator_v13_2_5 -64 -93 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + +vlog -work fifo_generator_v13_2_5 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/file_info.txt new file mode 100644 index 0000000..b3bd811 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/file_info.txt @@ -0,0 +1,18 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.sh new file mode 100755 index 0000000..8596a31 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rdback_fifo.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.udo b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/rdback_fifo.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/simulate.do new file mode 100644 index 0000000..13d9d23 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -L xilinx_vip -L xpm -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.rdback_fifo xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {rdback_fifo.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/README.txt new file mode 100644 index 0000000..6aedcac --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/compile.do new file mode 100644 index 0000000..593e8f3 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/compile.do @@ -0,0 +1,47 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xilinx_vip +vlib questa_lib/msim/xpm +vlib questa_lib/msim/fifo_generator_v13_2_5 +vlib questa_lib/msim/xil_defaultlib + +vmap xilinx_vip questa_lib/msim/xilinx_vip +vmap xpm questa_lib/msim/xpm +vmap fifo_generator_v13_2_5 questa_lib/msim/fifo_generator_v13_2_5 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work fifo_generator_v13_2_5 -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + +vcom -work fifo_generator_v13_2_5 -64 -93 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + +vlog -work fifo_generator_v13_2_5 -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + +vlog -work xil_defaultlib -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/elaborate.do new file mode 100644 index 0000000..e16495d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.rdback_fifo xil_defaultlib.glbl -o rdback_fifo_opt diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/file_info.txt new file mode 100644 index 0000000..b3bd811 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/file_info.txt @@ -0,0 +1,18 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.sh new file mode 100755 index 0000000..e466991 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rdback_fifo.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.udo b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/simulate.do new file mode 100644 index 0000000..36dd6b6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -lib xil_defaultlib rdback_fifo_opt + +do {wave.do} + +view wave +view structure +view signals + +do {rdback_fifo.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/README.txt new file mode 100644 index 0000000..6aedcac --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/compile.do new file mode 100644 index 0000000..75b575c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/compile.do @@ -0,0 +1,47 @@ +vlib work +vlib riviera + +vlib riviera/xilinx_vip +vlib riviera/xpm +vlib riviera/fifo_generator_v13_2_5 +vlib riviera/xil_defaultlib + +vmap xilinx_vip riviera/xilinx_vip +vmap xpm riviera/xpm +vmap fifo_generator_v13_2_5 riviera/fifo_generator_v13_2_5 +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work fifo_generator_v13_2_5 -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + +vcom -work fifo_generator_v13_2_5 -93 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + +vlog -work fifo_generator_v13_2_5 -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/file_info.txt new file mode 100644 index 0000000..b3bd811 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/file_info.txt @@ -0,0 +1,18 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/rdback_fifo.sh new file mode 100755 index 0000000..1a4dd2f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/rdback_fifo.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rdback_fifo.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/rdback_fifo.udo b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/rdback_fifo.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/rdback_fifo.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/simulate.do new file mode 100644 index 0000000..85b1785 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+rdback_fifo -L xilinx_vip -L xpm -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.rdback_fifo xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {rdback_fifo.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/README.txt new file mode 100644 index 0000000..6aedcac --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/file_info.txt new file mode 100644 index 0000000..b3bd811 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/file_info.txt @@ -0,0 +1,18 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/rdback_fifo.sh new file mode 100755 index 0000000..4f840a9 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/rdback_fifo.sh @@ -0,0 +1,255 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rdback_fifo.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xilinx_vip xpm fifo_generator_v13_2_5 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xpm $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work fifo_generator_v13_2_5 $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work fifo_generator_v13_2_5 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work fifo_generator_v13_2_5 $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.rdback_fifo xil_defaultlib.glbl -o rdback_fifo_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./rdback_fifo_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key rdback_fifo_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc rdback_fifo_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/README.txt new file mode 100644 index 0000000..66cb393 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/file_info.txt new file mode 100644 index 0000000..b3bd811 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/file_info.txt @@ -0,0 +1,18 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/rdback_fifo.sh new file mode 100755 index 0000000..b1f1037 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/rdback_fifo.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rdback_fifo.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm fifo_generator_v13_2_5 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.rdback_fifo \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/run.f new file mode 100644 index 0000000..415504c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xcelium/run.f @@ -0,0 +1,35 @@ +-makelib xcelium_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/fifo_generator_v13_2_5 \ + "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ +-endlib +-makelib xcelium_lib/fifo_generator_v13_2_5 \ + "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ +-endlib +-makelib xcelium_lib/fifo_generator_v13_2_5 \ + "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/README.txt new file mode 100644 index 0000000..6aedcac --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/U200.smi new file mode 100644 index 0000000..f20b0a8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/U200.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2020.2 (64-bit) --> +<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 --> +<!-- --> +<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 18 2020 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcu200-fsgd2104-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/file_info.txt new file mode 100644 index 0000000..4ebc368 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/file_info.txt @@ -0,0 +1,2 @@ +rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_afa8.protoinst new file mode 100644 index 0000000..a0656b6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_afa8.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_afa8": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_ba6a.protoinst new file mode 100644 index 0000000..c42e1c4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_ba6a.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_ba6a": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/rdback_fifo.sh new file mode 100755 index 0000000..199b134 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/rdback_fifo.sh @@ -0,0 +1,214 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0 +xvlog_opts="--relax -L xdma_v4_1_8" +xvhdl_opts="--relax" + + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot rdback_fifo xil_defaultlib.rdback_fifo xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim rdback_fifo -key {Behavioral:sim_1:Functional:rdback_fifo} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb rdback_fifo.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vhdl.prj b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vhdl.prj new file mode 100644 index 0000000..359cbd5 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vhdl.prj @@ -0,0 +1,2 @@ + +nosort diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vlog.prj new file mode 100644 index 0000000..094bca5 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/README.txt new file mode 100644 index 0000000..5acdd2f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/README.txt new file mode 100644 index 0000000..2eae1bd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:53 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./scratchpad.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './scratchpad.sh' script. + +./scratchpad.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./scratchpad.sh -noclean_files + +For more information on the script, please type './scratchpad.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/compile.do new file mode 100644 index 0000000..ef7be87 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/compile.do @@ -0,0 +1,41 @@ +vlib work +vlib activehdl + +vlib activehdl/xilinx_vip +vlib activehdl/xpm +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/xil_defaultlib + +vmap xilinx_vip activehdl/xilinx_vip +vmap xpm activehdl/xpm +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/file_info.txt new file mode 100644 index 0000000..df82e18 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +scratchpad.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/scratchpad.sh b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/scratchpad.sh new file mode 100755 index 0000000..62643c3 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/scratchpad.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : scratchpad.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:53 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: scratchpad.sh [-help] +# usage: scratchpad.sh [-lib_map_path] +# usage: scratchpad.sh [-noclean_files] +# usage: scratchpad.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'scratchpad.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: scratchpad.sh [-help]\n\ +Usage: scratchpad.sh [-lib_map_path]\n\ +Usage: scratchpad.sh [-reset_run]\n\ +Usage: scratchpad.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/scratchpad.udo b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/scratchpad.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/scratchpad.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/simulate.do new file mode 100644 index 0000000..6c79e4a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+scratchpad -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.scratchpad xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {scratchpad.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/summary.log new file mode 100755 index 0000000..28dc68a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [32] +Port A Write Width : [32] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 2.119075 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/README.txt new file mode 100644 index 0000000..7abac0d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:53 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./scratchpad.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './scratchpad.sh' script. + +./scratchpad.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./scratchpad.sh -noclean_files + +For more information on the script, please type './scratchpad.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/file_info.txt new file mode 100644 index 0000000..df82e18 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +scratchpad.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/run.f new file mode 100644 index 0000000..af75aa4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/run.f @@ -0,0 +1,29 @@ +-makelib ies_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/scratchpad.sh b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/scratchpad.sh new file mode 100755 index 0000000..8784621 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/scratchpad.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : scratchpad.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:53 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: scratchpad.sh [-help] +# usage: scratchpad.sh [-lib_map_path] +# usage: scratchpad.sh [-noclean_files] +# usage: scratchpad.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'scratchpad.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.scratchpad \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: scratchpad.sh [-help]\n\ +Usage: scratchpad.sh [-lib_map_path]\n\ +Usage: scratchpad.sh [-reset_run]\n\ +Usage: scratchpad.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/summary.log new file mode 100755 index 0000000..28dc68a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/ies/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [32] +Port A Write Width : [32] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 2.119075 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/README.txt new file mode 100644 index 0000000..2eae1bd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:53 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./scratchpad.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './scratchpad.sh' script. + +./scratchpad.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./scratchpad.sh -noclean_files + +For more information on the script, please type './scratchpad.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/compile.do new file mode 100644 index 0000000..e8c4be4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/compile.do @@ -0,0 +1,41 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xilinx_vip +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xilinx_vip modelsim_lib/msim/xilinx_vip +vmap xpm modelsim_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/file_info.txt new file mode 100644 index 0000000..df82e18 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +scratchpad.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/scratchpad.sh b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/scratchpad.sh new file mode 100755 index 0000000..e0a9ed5 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/scratchpad.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : scratchpad.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:53 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: scratchpad.sh [-help] +# usage: scratchpad.sh [-lib_map_path] +# usage: scratchpad.sh [-noclean_files] +# usage: scratchpad.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'scratchpad.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: scratchpad.sh [-help]\n\ +Usage: scratchpad.sh [-lib_map_path]\n\ +Usage: scratchpad.sh [-reset_run]\n\ +Usage: scratchpad.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/scratchpad.udo b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/scratchpad.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/scratchpad.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/simulate.do new file mode 100644 index 0000000..6e1a057 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.scratchpad xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {scratchpad.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/summary.log new file mode 100755 index 0000000..28dc68a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [32] +Port A Write Width : [32] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 2.119075 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/README.txt new file mode 100644 index 0000000..2eae1bd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:53 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./scratchpad.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './scratchpad.sh' script. + +./scratchpad.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./scratchpad.sh -noclean_files + +For more information on the script, please type './scratchpad.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/compile.do new file mode 100644 index 0000000..78fc227 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/compile.do @@ -0,0 +1,41 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xilinx_vip +vlib questa_lib/msim/xpm +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/xil_defaultlib + +vmap xilinx_vip questa_lib/msim/xilinx_vip +vmap xpm questa_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/elaborate.do new file mode 100644 index 0000000..f4279c7 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.scratchpad xil_defaultlib.glbl -o scratchpad_opt diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/file_info.txt new file mode 100644 index 0000000..df82e18 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +scratchpad.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/scratchpad.sh b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/scratchpad.sh new file mode 100755 index 0000000..26758fa --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/scratchpad.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : scratchpad.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:53 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: scratchpad.sh [-help] +# usage: scratchpad.sh [-lib_map_path] +# usage: scratchpad.sh [-noclean_files] +# usage: scratchpad.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'scratchpad.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: scratchpad.sh [-help]\n\ +Usage: scratchpad.sh [-lib_map_path]\n\ +Usage: scratchpad.sh [-reset_run]\n\ +Usage: scratchpad.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/scratchpad.udo b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/scratchpad.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/scratchpad.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/simulate.do new file mode 100644 index 0000000..aa4b5cd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -lib xil_defaultlib scratchpad_opt + +do {wave.do} + +view wave +view structure +view signals + +do {scratchpad.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/summary.log new file mode 100755 index 0000000..28dc68a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [32] +Port A Write Width : [32] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 2.119075 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/README.txt new file mode 100644 index 0000000..2eae1bd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:53 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./scratchpad.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './scratchpad.sh' script. + +./scratchpad.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./scratchpad.sh -noclean_files + +For more information on the script, please type './scratchpad.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/compile.do new file mode 100644 index 0000000..ffa5c78 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/compile.do @@ -0,0 +1,41 @@ +vlib work +vlib riviera + +vlib riviera/xilinx_vip +vlib riviera/xpm +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/xil_defaultlib + +vmap xilinx_vip riviera/xilinx_vip +vmap xpm riviera/xpm +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/file_info.txt new file mode 100644 index 0000000..df82e18 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +scratchpad.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/scratchpad.sh b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/scratchpad.sh new file mode 100755 index 0000000..2baf52b --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/scratchpad.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : scratchpad.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:53 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: scratchpad.sh [-help] +# usage: scratchpad.sh [-lib_map_path] +# usage: scratchpad.sh [-noclean_files] +# usage: scratchpad.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'scratchpad.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: scratchpad.sh [-help]\n\ +Usage: scratchpad.sh [-lib_map_path]\n\ +Usage: scratchpad.sh [-reset_run]\n\ +Usage: scratchpad.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/scratchpad.udo b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/scratchpad.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/scratchpad.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/simulate.do new file mode 100644 index 0000000..6c79e4a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+scratchpad -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.scratchpad xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {scratchpad.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/summary.log new file mode 100755 index 0000000..28dc68a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [32] +Port A Write Width : [32] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 2.119075 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/README.txt new file mode 100644 index 0000000..2eae1bd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:53 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./scratchpad.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './scratchpad.sh' script. + +./scratchpad.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./scratchpad.sh -noclean_files + +For more information on the script, please type './scratchpad.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/file_info.txt new file mode 100644 index 0000000..df82e18 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +scratchpad.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/scratchpad.sh b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/scratchpad.sh new file mode 100755 index 0000000..886794d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/scratchpad.sh @@ -0,0 +1,247 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : scratchpad.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:53 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: scratchpad.sh [-help] +# usage: scratchpad.sh [-lib_map_path] +# usage: scratchpad.sh [-noclean_files] +# usage: scratchpad.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'scratchpad.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xpm $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.scratchpad xil_defaultlib.glbl -o scratchpad_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./scratchpad_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key scratchpad_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc scratchpad_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: scratchpad.sh [-help]\n\ +Usage: scratchpad.sh [-lib_map_path]\n\ +Usage: scratchpad.sh [-reset_run]\n\ +Usage: scratchpad.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/summary.log new file mode 100755 index 0000000..28dc68a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/vcs/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [32] +Port A Write Width : [32] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 2.119075 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/README.txt new file mode 100644 index 0000000..7abac0d --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:53 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./scratchpad.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './scratchpad.sh' script. + +./scratchpad.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./scratchpad.sh -noclean_files + +For more information on the script, please type './scratchpad.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/file_info.txt new file mode 100644 index 0000000..df82e18 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +scratchpad.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/run.f new file mode 100644 index 0000000..fe626da --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/run.f @@ -0,0 +1,29 @@ +-makelib xcelium_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/scratchpad.sh b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/scratchpad.sh new file mode 100755 index 0000000..5f71422 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/scratchpad.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : scratchpad.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:53 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: scratchpad.sh [-help] +# usage: scratchpad.sh [-lib_map_path] +# usage: scratchpad.sh [-noclean_files] +# usage: scratchpad.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'scratchpad.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.scratchpad \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: scratchpad.sh [-help]\n\ +Usage: scratchpad.sh [-lib_map_path]\n\ +Usage: scratchpad.sh [-reset_run]\n\ +Usage: scratchpad.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/summary.log new file mode 100755 index 0000000..28dc68a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xcelium/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [32] +Port A Write Width : [32] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 2.119075 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/README.txt new file mode 100644 index 0000000..2eae1bd --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:53 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./scratchpad.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './scratchpad.sh' script. + +./scratchpad.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./scratchpad.sh -noclean_files + +For more information on the script, please type './scratchpad.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/U200.smi new file mode 100644 index 0000000..f20b0a8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/U200.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2020.2 (64-bit) --> +<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 --> +<!-- --> +<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 18 2020 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcu200-fsgd2104-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/file_info.txt new file mode 100644 index 0000000..a593cef --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/file_info.txt @@ -0,0 +1,2 @@ +scratchpad.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_afa8.protoinst new file mode 100644 index 0000000..a0656b6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_afa8.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_afa8": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_ba6a.protoinst new file mode 100644 index 0000000..c42e1c4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/protoinst_files/bd_ba6a.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_ba6a": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/scratchpad.sh b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/scratchpad.sh new file mode 100755 index 0000000..3ee51c2 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/scratchpad.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : scratchpad.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:53 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: scratchpad.sh [-help] +# usage: scratchpad.sh [-lib_map_path] +# usage: scratchpad.sh [-noclean_files] +# usage: scratchpad.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0 +xvlog_opts="--relax -L xdma_v4_1_8" + + +# Script info +echo -e "scratchpad.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot scratchpad xil_defaultlib.scratchpad xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim scratchpad -key {Behavioral:sim_1:Functional:scratchpad} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb scratchpad.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./scratchpad.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: scratchpad.sh [-help]\n\ +Usage: scratchpad.sh [-lib_map_path]\n\ +Usage: scratchpad.sh [-reset_run]\n\ +Usage: scratchpad.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/summary.log new file mode 100755 index 0000000..28dc68a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [32] +Port A Write Width : [32] +Memory Depth : [1024] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 2.119075 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/vlog.prj new file mode 100644 index 0000000..cd813ef --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/scratchpad/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../../U200.srcs/sources_1/ip/scratchpad/sim/scratchpad.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/README.txt new file mode 100644 index 0000000..5acdd2f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/README.txt new file mode 100644 index 0000000..80d792b --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:25:07 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/compile.do new file mode 100644 index 0000000..030f535 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/compile.do @@ -0,0 +1,122 @@ +vlib work +vlib activehdl + +vlib activehdl/xilinx_vip +vlib activehdl/xpm +vlib activehdl/gtwizard_ultrascale_v1_7_9 +vlib activehdl/xil_defaultlib +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/xdma_v4_1_8 + +vmap xilinx_vip activehdl/xilinx_vip +vmap xpm activehdl/xpm +vmap gtwizard_ultrascale_v1_7_9 activehdl/gtwizard_ultrascale_v1_7_9 +vmap xil_defaultlib activehdl/xil_defaultlib +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap xdma_v4_1_8 activehdl/xdma_v4_1_8 + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work gtwizard_ultrascale_v1_7_9 -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v" \ + +vlog -work xdma_v4_1_8 -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \ + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/file_info.txt new file mode 100644 index 0000000..4b7b0db --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/file_info.txt @@ -0,0 +1,85 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" 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+xdma_pcie4_ip_pipe.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pcie4_uscale_core_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_8_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_8_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_8,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_2048.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/simulate.do new file mode 100644 index 0000000..34e7202 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+xdma -L xilinx_vip -L xpm -L gtwizard_ultrascale_v1_7_9 -L xil_defaultlib -L blk_mem_gen_v8_4_4 -L xdma_v4_1_8 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.xdma xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {xdma.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/xdma.sh b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/xdma.sh new file mode 100755 index 0000000..9f94baf --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/xdma.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:25:07 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'xdma.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/xdma.udo b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/xdma.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/activehdl/xdma.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/README.txt new file mode 100644 index 0000000..4fcaf1f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:25:07 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/file_info.txt new file mode 100644 index 0000000..06871a0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/file_info.txt @@ -0,0 +1,85 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" 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+xdma_pcie4_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sync_cell.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sync.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pl_eq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_vf_decode.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pipe.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pcie4_uscale_core_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_8_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_8_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_8,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_2048.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/run.f new file mode 100644 index 0000000..b87a2cf --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/run.f @@ -0,0 +1,106 @@ +-makelib ies_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/gtwizard_ultrascale_v1_7_9 \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v" \ +-endlib +-makelib ies_lib/xdma_v4_1_8 -sv \ + "../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \ +-endlib +-makelib ies_lib/xil_defaultlib -sv \ + "../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ + "../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ + "../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv" \ + "../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ + "../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/xdma.sh b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/xdma.sh new file mode 100755 index 0000000..7e1b3b4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/ies/xdma.sh @@ -0,0 +1,180 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:25:07 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'xdma.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm gtwizard_ultrascale_v1_7_9 xil_defaultlib blk_mem_gen_v8_4_4 xdma_v4_1_8) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.xdma \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" \ + +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" \ + +incdir+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" \ + +incdir+"../../../ipstatic/hdl/verilog" \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/README.txt new file mode 100644 index 0000000..80d792b --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:25:07 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/compile.do new file mode 100644 index 0000000..c8f906f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/compile.do @@ -0,0 +1,122 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xilinx_vip +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/gtwizard_ultrascale_v1_7_9 +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/xdma_v4_1_8 + +vmap xilinx_vip modelsim_lib/msim/xilinx_vip +vmap xpm modelsim_lib/msim/xpm +vmap gtwizard_ultrascale_v1_7_9 modelsim_lib/msim/gtwizard_ultrascale_v1_7_9 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap xdma_v4_1_8 modelsim_lib/msim/xdma_v4_1_8 + +vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work gtwizard_ultrascale_v1_7_9 -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v" \ + +vlog -work xdma_v4_1_8 -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \ + +vlog -work xil_defaultlib -64 -incr -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/file_info.txt new file mode 100644 index 0000000..4b7b0db --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/file_info.txt @@ -0,0 +1,85 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_reset.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_reset_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_reset_inv_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_16k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_32k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_msix.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_rep.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_tph.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sync_cell.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sync.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pl_eq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_vf_decode.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pipe.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pcie4_uscale_core_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_8_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_8_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_8,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_2048.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/simulate.do new file mode 100644 index 0000000..dc180fb --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -L xilinx_vip -L xpm -L gtwizard_ultrascale_v1_7_9 -L xil_defaultlib -L blk_mem_gen_v8_4_4 -L xdma_v4_1_8 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.xdma xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {xdma.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/xdma.sh b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/xdma.sh new file mode 100755 index 0000000..95e2767 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/xdma.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:25:07 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'xdma.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/xdma.udo b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/xdma.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/modelsim/xdma.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/README.txt new file mode 100644 index 0000000..80d792b --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:25:07 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/compile.do new file mode 100644 index 0000000..3de0736 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/compile.do @@ -0,0 +1,122 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xilinx_vip +vlib questa_lib/msim/xpm +vlib questa_lib/msim/gtwizard_ultrascale_v1_7_9 +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/xdma_v4_1_8 + +vmap xilinx_vip questa_lib/msim/xilinx_vip +vmap xpm questa_lib/msim/xpm +vmap gtwizard_ultrascale_v1_7_9 questa_lib/msim/gtwizard_ultrascale_v1_7_9 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap xdma_v4_1_8 questa_lib/msim/xdma_v4_1_8 + +vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work gtwizard_ultrascale_v1_7_9 -64 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v" \ + +vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v" \ + +vlog -work xdma_v4_1_8 -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \ + +vlog -work xil_defaultlib -64 -sv -L xdma_v4_1_8 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/elaborate.do new file mode 100644 index 0000000..33613c4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L gtwizard_ultrascale_v1_7_9 -L xil_defaultlib -L blk_mem_gen_v8_4_4 -L xdma_v4_1_8 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.xdma xil_defaultlib.glbl -o xdma_opt diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/file_info.txt new file mode 100644 index 0000000..4b7b0db --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/file_info.txt @@ -0,0 +1,85 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_memory.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_bit_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gte4_drp_arb.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_reset.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_reset_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_reset_inv_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_16k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_32k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_msix.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_rep.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_tph.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sync_cell.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sync.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pl_eq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_vf_decode.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pipe.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pcie4_uscale_core_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_8_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_8_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_8,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_2048.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/simulate.do new file mode 100644 index 0000000..76f4faa --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -lib xil_defaultlib xdma_opt + +do {wave.do} + +view wave +view structure +view signals + +do {xdma.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/xdma.sh b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/xdma.sh new file mode 100755 index 0000000..fbc7127 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/xdma.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:25:07 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'xdma.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/xdma.udo b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/xdma.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/questa/xdma.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/README.txt new file mode 100644 index 0000000..80d792b --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:25:07 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/compile.do new file mode 100644 index 0000000..e219d31 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/compile.do @@ -0,0 +1,122 @@ +vlib work +vlib riviera + +vlib riviera/xilinx_vip +vlib riviera/xpm +vlib riviera/gtwizard_ultrascale_v1_7_9 +vlib riviera/xil_defaultlib +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/xdma_v4_1_8 + +vmap xilinx_vip riviera/xilinx_vip +vmap xpm riviera/xpm +vmap gtwizard_ultrascale_v1_7_9 riviera/gtwizard_ultrascale_v1_7_9 +vmap xil_defaultlib riviera/xil_defaultlib +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap xdma_v4_1_8 riviera/xdma_v4_1_8 + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work gtwizard_ultrascale_v1_7_9 -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \ +"../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v" \ + +vlog -work xdma_v4_1_8 -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \ + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" "+incdir+../../../ipstatic/hdl/verilog" "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/file_info.txt new file mode 100644 index 0000000..4b7b0db --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/file_info.txt @@ -0,0 +1,85 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" 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+xdma_pcie4_ip_bram_16k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_32k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_msix.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_rep.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_tph.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sync_cell.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sync.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pl_eq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_vf_decode.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pipe.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pcie4_uscale_core_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_8_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_8_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_8,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_2048.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/simulate.do new file mode 100644 index 0000000..34e7202 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+xdma -L xilinx_vip -L xpm -L gtwizard_ultrascale_v1_7_9 -L xil_defaultlib -L blk_mem_gen_v8_4_4 -L xdma_v4_1_8 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.xdma xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {xdma.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/xdma.sh b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/xdma.sh new file mode 100755 index 0000000..92736d2 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/xdma.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:25:07 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'xdma.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/xdma.udo b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/xdma.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/riviera/xdma.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/README.txt new file mode 100644 index 0000000..80d792b --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:25:07 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/file_info.txt new file mode 100644 index 0000000..06871a0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/file_info.txt @@ -0,0 +1,85 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" 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+gtwizard_ultrascale_v1_7_reset_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_reset_inv_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_16k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_32k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_msix.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_rep.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_tph.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sync_cell.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sync.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pl_eq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_vf_decode.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pipe.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pcie4_uscale_core_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_8_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_8_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_8,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_2048.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/xdma.sh b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/xdma.sh new file mode 100755 index 0000000..865fe76 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/vcs/xdma.sh @@ -0,0 +1,328 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:25:07 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'xdma.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xilinx_vip xpm gtwizard_ultrascale_v1_7_9 xil_defaultlib blk_mem_gen_v8_4_4 xdma_v4_1_8) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work gtwizard_ultrascale_v1_7_9 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \ + "$ref_dir/../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xdma_v4_1_8 $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.xdma xil_defaultlib.glbl -o xdma_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./xdma_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key xdma_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc xdma_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/README.txt new file mode 100644 index 0000000..4fcaf1f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:25:07 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/file_info.txt new file mode 100644 index 0000000..06871a0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/file_info.txt @@ -0,0 +1,85 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +axi_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +clk_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +rst_vip_if.sv,systemverilog,xilinx_vip,../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_cdc.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xpm_fifo.sv,systemverilog,xpm,../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" 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+gtwizard_ultrascale_v1_7_reset_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_reset_inv_sync.v,verilog,gtwizard_ultrascale_v1_7_9,../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_16k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_32k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_msix.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_rep.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_tph.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sync_cell.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sync.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pl_eq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_vf_decode.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pipe.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pcie4_uscale_core_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_8_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_8_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_vl_rfs.sv,systemverilog,xdma_v4_1_8,../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_2048.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/run.f new file mode 100644 index 0000000..5b72987 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/run.f @@ -0,0 +1,106 @@ +-makelib xcelium_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/gtwizard_ultrascale_v1_7_9 \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_bit_sync.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gte4_drp_arb.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_reset.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_sync.v" \ + "../../../ipstatic/hdl/gtwizard_ultrascale_v1_7_reset_inv_sync.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v" \ + "../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v" \ +-endlib +-makelib xcelium_lib/xdma_v4_1_8 -sv \ + "../../../ipstatic/hdl/xdma_v4_1_vl_rfs.sv" \ +-endlib +-makelib xcelium_lib/xil_defaultlib -sv \ + "../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ + "../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ + "../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv" \ + "../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ + "../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/xdma.sh b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/xdma.sh new file mode 100755 index 0000000..e70b217 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xcelium/xdma.sh @@ -0,0 +1,180 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:25:07 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'xdma.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm gtwizard_ultrascale_v1_7_9 xil_defaultlib blk_mem_gen_v8_4_4 xdma_v4_1_8) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.xdma \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" \ + +incdir+"$ref_dir/../../../ipstatic/hdl/verilog" \ + +incdir+"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" \ + +incdir+"../../../ipstatic/hdl/verilog" \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/README.txt new file mode 100644 index 0000000..80d792b --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:25:07 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./xdma.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './xdma.sh' script. + +./xdma.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./xdma.sh -noclean_files + +For more information on the script, please type './xdma.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/U200.smi new file mode 100644 index 0000000..f20b0a8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/U200.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2020.2 (64-bit) --> +<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 --> +<!-- --> +<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 18 2020 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcu200-fsgd2104-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/file_info.txt new file mode 100644 index 0000000..31e1717 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/file_info.txt @@ -0,0 +1,47 @@ +gtwizard_ultrascale_v1_7_gtye4_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +gtwizard_ultrascale_v1_7_gtye4_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtye4_common_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtwizard_gtye4.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gtwizard_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_ff_chain.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_pipeline.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_16k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_16k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_32k.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_4k_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_msix.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_rep_int.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_rep.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram_tph.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_bram.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gt_channel.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_gt_common.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_clk.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_rst.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_rxeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_txeq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sync_cell.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sync.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_receiver_detect_rxterm.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_gt_phy_wrapper.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_init_ctrl.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pl_eq.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_vf_decode.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pipe.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_phy_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_seqnum_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_sys_clk_gen_ps.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip_pcie4_uscale_core_top.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_pcie4_ip.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_8_blk_mem_64_reg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_v4_1_8_blk_mem_64_noreg_be.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_1024.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_dma_bram_wrap_2048.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma_core_top.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +xdma.sv,systemverilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv,incdir="$ref_dir/../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="$ref_dir/../../../ipstatic/hdl/verilog"incdir="../../../../U200.srcs/sources_1/ip/xdma/ip_0/source"incdir="../../../ipstatic/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_afa8.protoinst new file mode 100644 index 0000000..a0656b6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_afa8.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_afa8": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_ba6a.protoinst new file mode 100644 index 0000000..c42e1c4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/protoinst_files/bd_ba6a.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_ba6a": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/vlog.prj new file mode 100644 index 0000000..27b76e4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/vlog.prj @@ -0,0 +1,53 @@ +verilog xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" --include "../../../ipstatic/hdl/verilog" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_channel.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_channel_wrapper.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/gtwizard_ultrascale_v1_7_gtye4_common.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtye4_common_wrapper.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_gtye4.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt_gtwizard_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/ip_0/sim/xdma_pcie4_ip_gt.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gtwizard_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_ff_chain.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_pipeline.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k_int.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_16k.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_32k.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_4k_int.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_msix.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep_int.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_rep.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram_tph.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_bram.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_channel.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_gt_common.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_clk.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rst.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_rxeq.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_txeq.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync_cell.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sync.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_cdr_ctrl_on_eidle.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_receiver_detect_rxterm.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_gt_phy_wrapper.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_init_ctrl.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pl_eq.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_vf_decode.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pipe.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_phy_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_seqnum_fifo.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_sys_clk_gen_ps.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/source/xdma_pcie4_ip_pcie4_uscale_core_top.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_0/sim/xdma_pcie4_ip.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v" \ +"../../../../U200.srcs/sources_1/ip/xdma/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v" \ + +sv xil_defaultlib --include "../../../../U200.srcs/sources_1/ip/xdma/ip_0/source" --include "../../../ipstatic/hdl/verilog" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_1024.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_dma_bram_wrap_2048.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/xdma_v4_1/hdl/verilog/xdma_core_top.sv" \ +"../../../../U200.srcs/sources_1/ip/xdma/sim/xdma.sv" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/xdma.sh b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/xdma.sh new file mode 100755 index 0000000..016da74 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/xdma/xsim/xdma.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : xdma.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:25:07 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: xdma.sh [-help] +# usage: xdma.sh [-lib_map_path] +# usage: xdma.sh [-noclean_files] +# usage: xdma.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0 +xvlog_opts="--relax -L xdma_v4_1_8" + + +# Script info +echo -e "xdma.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L gtwizard_ultrascale_v1_7_9 -L xil_defaultlib -L blk_mem_gen_v8_4_4 -L xdma_v4_1_8 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot xdma xil_defaultlib.xdma xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim xdma -key {Behavioral:sim_1:Functional:xdma} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=(xil_defaultlib) + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb xdma.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./xdma.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: xdma.sh [-help]\n\ +Usage: xdma.sh [-lib_map_path]\n\ +Usage: xdma.sh [-reset_run]\n\ +Usage: xdma.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/README.txt new file mode 100644 index 0000000..5acdd2f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +<current_working_directory>/export_sim/<simulator> + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +<simulation_top>.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +<ip-name>.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/README.txt new file mode 100644 index 0000000..9c5c2d0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:25:29 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./zq_calib_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './zq_calib_mem.sh' script. + +./zq_calib_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./zq_calib_mem.sh -noclean_files + +For more information on the script, please type './zq_calib_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/compile.do new file mode 100644 index 0000000..ebe0a4e --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/compile.do @@ -0,0 +1,41 @@ +vlib work +vlib activehdl + +vlib activehdl/xilinx_vip +vlib activehdl/xpm +vlib activehdl/blk_mem_gen_v8_4_4 +vlib activehdl/xil_defaultlib + +vmap xilinx_vip activehdl/xilinx_vip +vmap xpm activehdl/xpm +vmap blk_mem_gen_v8_4_4 activehdl/blk_mem_gen_v8_4_4 +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/file_info.txt new file mode 100644 index 0000000..6503f24 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +zq_calib_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/pr_zq.coe b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/pr_zq.coe new file mode 100755 index 0000000..16d563c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/simulate.do new file mode 100644 index 0000000..98824fe --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+zq_calib_mem -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.zq_calib_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {zq_calib_mem.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.mif new file mode 100755 index 0000000..fdf3bb0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.mif @@ -0,0 +1,40 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001100000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.sh new file mode 100755 index 0000000..c698103 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : zq_calib_mem.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:25:29 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: zq_calib_mem.sh [-help] +# usage: zq_calib_mem.sh [-lib_map_path] +# usage: zq_calib_mem.sh [-noclean_files] +# usage: zq_calib_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'zq_calib_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: zq_calib_mem.sh [-help]\n\ +Usage: zq_calib_mem.sh [-lib_map_path]\n\ +Usage: zq_calib_mem.sh [-reset_run]\n\ +Usage: zq_calib_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/activehdl/zq_calib_mem.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/README.txt new file mode 100644 index 0000000..c57722c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:25:29 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./zq_calib_mem.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './zq_calib_mem.sh' script. + +./zq_calib_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./zq_calib_mem.sh -noclean_files + +For more information on the script, please type './zq_calib_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/file_info.txt new file mode 100644 index 0000000..6503f24 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +zq_calib_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/pr_zq.coe b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/pr_zq.coe new file mode 100755 index 0000000..16d563c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/run.f b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/run.f new file mode 100644 index 0000000..123f2d0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/run.f @@ -0,0 +1,29 @@ +-makelib ies_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib ies_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.mif new file mode 100755 index 0000000..fdf3bb0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.mif @@ -0,0 +1,40 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001100000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.sh new file mode 100755 index 0000000..c2171a1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/ies/zq_calib_mem.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : zq_calib_mem.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:25:29 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: zq_calib_mem.sh [-help] +# usage: zq_calib_mem.sh [-lib_map_path] +# usage: zq_calib_mem.sh [-noclean_files] +# usage: zq_calib_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'zq_calib_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.zq_calib_mem \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: zq_calib_mem.sh [-help]\n\ +Usage: zq_calib_mem.sh [-lib_map_path]\n\ +Usage: zq_calib_mem.sh [-reset_run]\n\ +Usage: zq_calib_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/README.txt new file mode 100644 index 0000000..9c5c2d0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:25:29 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./zq_calib_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './zq_calib_mem.sh' script. + +./zq_calib_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./zq_calib_mem.sh -noclean_files + +For more information on the script, please type './zq_calib_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/compile.do new file mode 100644 index 0000000..ca24810 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/compile.do @@ -0,0 +1,41 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xilinx_vip +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/blk_mem_gen_v8_4_4 +vlib modelsim_lib/msim/xil_defaultlib + +vmap xilinx_vip modelsim_lib/msim/xilinx_vip +vmap xpm modelsim_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 modelsim_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xilinx_vip -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -incr -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/file_info.txt new file mode 100644 index 0000000..6503f24 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +zq_calib_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/pr_zq.coe b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/pr_zq.coe new file mode 100755 index 0000000..16d563c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/simulate.do new file mode 100644 index 0000000..05efcd8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.zq_calib_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {zq_calib_mem.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.mif new file mode 100755 index 0000000..fdf3bb0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.mif @@ -0,0 +1,40 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001100000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.sh new file mode 100755 index 0000000..e158b8a --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : zq_calib_mem.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:25:29 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: zq_calib_mem.sh [-help] +# usage: zq_calib_mem.sh [-lib_map_path] +# usage: zq_calib_mem.sh [-noclean_files] +# usage: zq_calib_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'zq_calib_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: zq_calib_mem.sh [-help]\n\ +Usage: zq_calib_mem.sh [-lib_map_path]\n\ +Usage: zq_calib_mem.sh [-reset_run]\n\ +Usage: zq_calib_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/modelsim/zq_calib_mem.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/README.txt new file mode 100644 index 0000000..9c5c2d0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:25:29 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./zq_calib_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './zq_calib_mem.sh' script. + +./zq_calib_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./zq_calib_mem.sh -noclean_files + +For more information on the script, please type './zq_calib_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/compile.do new file mode 100644 index 0000000..01d7b08 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/compile.do @@ -0,0 +1,41 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xilinx_vip +vlib questa_lib/msim/xpm +vlib questa_lib/msim/blk_mem_gen_v8_4_4 +vlib questa_lib/msim/xil_defaultlib + +vmap xilinx_vip questa_lib/msim/xilinx_vip +vmap xpm questa_lib/msim/xpm +vmap blk_mem_gen_v8_4_4 questa_lib/msim/blk_mem_gen_v8_4_4 +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xilinx_vip -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -64 -sv -L xdma_v4_1_8 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/elaborate.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/elaborate.do new file mode 100644 index 0000000..c1d3233 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc=npr -l elaborate.log -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.zq_calib_mem xil_defaultlib.glbl -o zq_calib_mem_opt diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/file_info.txt new file mode 100644 index 0000000..6503f24 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +zq_calib_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/pr_zq.coe b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/pr_zq.coe new file mode 100755 index 0000000..16d563c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/simulate.do new file mode 100644 index 0000000..c04f9f4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -lib xil_defaultlib zq_calib_mem_opt + +do {wave.do} + +view wave +view structure +view signals + +do {zq_calib_mem.udo} + +run -all + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.mif new file mode 100755 index 0000000..fdf3bb0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.mif @@ -0,0 +1,40 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001100000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.sh new file mode 100755 index 0000000..6e09ac3 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : zq_calib_mem.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:25:29 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: zq_calib_mem.sh [-help] +# usage: zq_calib_mem.sh [-lib_map_path] +# usage: zq_calib_mem.sh [-noclean_files] +# usage: zq_calib_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'zq_calib_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: zq_calib_mem.sh [-help]\n\ +Usage: zq_calib_mem.sh [-lib_map_path]\n\ +Usage: zq_calib_mem.sh [-reset_run]\n\ +Usage: zq_calib_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/questa/zq_calib_mem.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/README.txt new file mode 100644 index 0000000..9c5c2d0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:25:29 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./zq_calib_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './zq_calib_mem.sh' script. + +./zq_calib_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./zq_calib_mem.sh -noclean_files + +For more information on the script, please type './zq_calib_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/compile.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/compile.do new file mode 100644 index 0000000..f940f79 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/compile.do @@ -0,0 +1,41 @@ +vlib work +vlib riviera + +vlib riviera/xilinx_vip +vlib riviera/xpm +vlib riviera/blk_mem_gen_v8_4_4 +vlib riviera/xil_defaultlib + +vmap xilinx_vip riviera/xilinx_vip +vmap xpm riviera/xpm +vmap blk_mem_gen_v8_4_4 riviera/blk_mem_gen_v8_4_4 +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xilinx_vip -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + +vlog -work xpm -sv2k12 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_4 -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ +"../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/file_info.txt new file mode 100644 index 0000000..6503f24 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +zq_calib_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/pr_zq.coe b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/pr_zq.coe new file mode 100755 index 0000000..16d563c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/simulate.do new file mode 100644 index 0000000..98824fe --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+zq_calib_mem -L xilinx_vip -L xpm -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.zq_calib_mem xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {zq_calib_mem.udo} + +run -all + +endsim + +quit -force diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/wave.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.mif new file mode 100755 index 0000000..fdf3bb0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.mif @@ -0,0 +1,40 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001100000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.sh new file mode 100755 index 0000000..0138397 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : zq_calib_mem.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:25:29 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: zq_calib_mem.sh [-help] +# usage: zq_calib_mem.sh [-lib_map_path] +# usage: zq_calib_mem.sh [-noclean_files] +# usage: zq_calib_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'zq_calib_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: <simulate> +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: zq_calib_mem.sh [-help]\n\ +Usage: zq_calib_mem.sh [-lib_map_path]\n\ +Usage: zq_calib_mem.sh [-reset_run]\n\ +Usage: zq_calib_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.udo b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.udo new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/riviera/zq_calib_mem.udo diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/README.txt new file mode 100644 index 0000000..9c5c2d0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:25:29 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./zq_calib_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './zq_calib_mem.sh' script. + +./zq_calib_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./zq_calib_mem.sh -noclean_files + +For more information on the script, please type './zq_calib_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/file_info.txt new file mode 100644 index 0000000..6503f24 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +zq_calib_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/pr_zq.coe b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/pr_zq.coe new file mode 100755 index 0000000..16d563c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/simulate.do b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.mif new file mode 100755 index 0000000..fdf3bb0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.mif @@ -0,0 +1,40 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001100000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.sh new file mode 100755 index 0000000..095e6f1 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/vcs/zq_calib_mem.sh @@ -0,0 +1,247 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : zq_calib_mem.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:25:29 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: zq_calib_mem.sh [-help] +# usage: zq_calib_mem.sh [-lib_map_path] +# usage: zq_calib_mem.sh [-noclean_files] +# usage: zq_calib_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'zq_calib_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xpm $vlogan_opts -sverilog +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" \ + "$ref_dir/../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.zq_calib_mem xil_defaultlib.glbl -o zq_calib_mem_simv +} + +# RUN_STEP: <simulate> +simulate() +{ + ./zq_calib_mem_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/ataberk/SoftMC_DDR4/projects/U200/U200.cache/compile_simlib/vcs" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key zq_calib_mem_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc zq_calib_mem_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: zq_calib_mem.sh [-help]\n\ +Usage: zq_calib_mem.sh [-lib_map_path]\n\ +Usage: zq_calib_mem.sh [-reset_run]\n\ +Usage: zq_calib_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/README.txt new file mode 100644 index 0000000..c57722c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:25:29 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./zq_calib_mem.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './zq_calib_mem.sh' script. + +./zq_calib_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./zq_calib_mem.sh -noclean_files + +For more information on the script, please type './zq_calib_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/file_info.txt new file mode 100644 index 0000000..6503f24 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/file_info.txt @@ -0,0 +1,16 @@ +axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv, +axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv, +xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv, +axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv, +axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv, +axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv, +axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv, +clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv, +rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv, +xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv, +xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +zq_calib_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/pr_zq.coe b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/pr_zq.coe new file mode 100755 index 0000000..16d563c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/run.f b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/run.f new file mode 100644 index 0000000..53b8cb9 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/run.f @@ -0,0 +1,29 @@ +-makelib xcelium_lib/xilinx_vip -sv \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/axi_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/clk_vip_if.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/hdl/rst_vip_if.sv" \ +-endlib +-makelib xcelium_lib/xpm -sv \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_4 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.mif new file mode 100755 index 0000000..fdf3bb0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.mif @@ -0,0 +1,40 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001100000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.sh new file mode 100755 index 0000000..72db278 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xcelium/zq_calib_mem.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : zq_calib_mem.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:25:29 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: zq_calib_mem.sh [-help] +# usage: zq_calib_mem.sh [-lib_map_path] +# usage: zq_calib_mem.sh [-noclean_files] +# usage: zq_calib_mem.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'zq_calib_mem.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xilinx_vip xpm blk_mem_gen_v8_4_4 xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: <execute> +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.zq_calib_mem \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"/tools/Xilinx/Vivado/2020.2/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: zq_calib_mem.sh [-help]\n\ +Usage: zq_calib_mem.sh [-lib_map_path]\n\ +Usage: zq_calib_mem.sh [-reset_run]\n\ +Usage: zq_calib_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/README.txt new file mode 100644 index 0000000..9c5c2d0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:25:29 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./zq_calib_mem.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './zq_calib_mem.sh' script. + +./zq_calib_mem.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./zq_calib_mem.sh -noclean_files + +For more information on the script, please type './zq_calib_mem.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/U200.smi new file mode 100644 index 0000000..f20b0a8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/U200.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2020.2 (64-bit) --> +<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 --> +<!-- --> +<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 18 2020 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcu200-fsgd2104-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/file_info.txt new file mode 100644 index 0000000..cacfd7c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/file_info.txt @@ -0,0 +1,2 @@ +zq_calib_mem.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/pr_zq.coe b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/pr_zq.coe new file mode 100755 index 0000000..16d563c --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/pr_zq.coe @@ -0,0 +1,42 @@ +memory_initialization_radix=2; +memory_initialization_vector= +0001100000000000000000000000000000000000010000000000000000000000, +0001100000000000000000000000000000000000010100000000000000000000, +0001100000000000000000000000000000000000011000000000000000000000, +1111000000000000111100000000000011110000000000001010100000000101, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001100000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000, +1111000000000000111100000000000011110000000000001111000000000000; diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_afa8.protoinst new file mode 100644 index 0000000..a0656b6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_afa8.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_afa8": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_ba6a.protoinst new file mode 100644 index 0000000..c42e1c4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/protoinst_files/bd_ba6a.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_ba6a": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/summary.log b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/summary.log new file mode 100755 index 0000000..7930542 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/summary.log @@ -0,0 +1,20 @@ + +User Configuration +-------------------------------------------------------------------------------- +Algorithm : Minimum_Area +Memory Type : Single_Port_RAM +Port A Read Width : [64] +Port A Write Width : [64] +Memory Depth : [64] + +---------------------------------------------------------------------------------- + +Block RAM resource(s) (18K BRAMs) : [0] +Block RAM resource(s) (36K BRAMs) : [1] +---------------------------------------------------------------------------------- +Clock A Frequency : [100] +Port A Enable Rate : [100] +Port A Write Rate : [50] +---------------------------------------------------------------------------------- +Estimated Power for IP : 5.931282 mW +---------------------------------------------------------------------------------- diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/vlog.prj new file mode 100644 index 0000000..c533a42 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../../U200.srcs/sources_1/ip/zq_calib_mem/sim/zq_calib_mem.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/zq_calib_mem.mif b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/zq_calib_mem.mif new file mode 100755 index 0000000..fdf3bb0 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/zq_calib_mem.mif @@ -0,0 +1,40 @@ +0001100000000000000000000000000000000000010000000000000000000000 +0001100000000000000000000000000000000000010100000000000000000000 +0001100000000000000000000000000000000000011000000000000000000000 +1111000000000000111100000000000011110000000000001010100000000101 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001100000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 +1111000000000000111100000000000011110000000000001111000000000000 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/zq_calib_mem.sh b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/zq_calib_mem.sh new file mode 100755 index 0000000..0dd964b --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/zq_calib_mem/xsim/zq_calib_mem.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : zq_calib_mem.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:25:29 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: zq_calib_mem.sh [-help] +# usage: zq_calib_mem.sh [-lib_map_path] +# usage: zq_calib_mem.sh [-noclean_files] +# usage: zq_calib_mem.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0 +xvlog_opts="--relax -L xdma_v4_1_8" + + +# Script info +echo -e "zq_calib_mem.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot zq_calib_mem xil_defaultlib.zq_calib_mem xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim zq_calib_mem -key {Behavioral:sim_1:Functional:zq_calib_mem} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb zq_calib_mem.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./zq_calib_mem.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: zq_calib_mem.sh [-help]\n\ +Usage: zq_calib_mem.sh [-lib_map_path]\n\ +Usage: zq_calib_mem.sh [-reset_run]\n\ +Usage: zq_calib_mem.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 |