Add sources for U50 HBM2

1 files changed, 95 insertions, 0 deletions

diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo.vho
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+++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/wrdata_fifo/wrdata_fifo.vho
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+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
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+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
+-- IP Revision: 5
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT wrdata_fifo
+  PORT (
+    srst : IN STD_LOGIC;
+    wr_clk : IN STD_LOGIC;
+    rd_clk : IN STD_LOGIC;
+    din : IN STD_LOGIC_VECTOR(1023 DOWNTO 0);
+    wr_en : IN STD_LOGIC;
+    rd_en : IN STD_LOGIC;
+    dout : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
+    full : OUT STD_LOGIC;
+    empty : OUT STD_LOGIC;
+    wr_rst_busy : OUT STD_LOGIC;
+    rd_rst_busy : OUT STD_LOGIC
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : wrdata_fifo
+  PORT MAP (
+    srst => srst,
+    wr_clk => wr_clk,
+    rd_clk => rd_clk,
+    din => din,
+    wr_en => wr_en,
+    rd_en => rd_en,
+    dout => dout,
+    full => full,
+    empty => empty,
+    wr_rst_busy => wr_rst_busy,
+    rd_rst_busy => rd_rst_busy
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file wrdata_fifo.vhd when simulating
+-- the core, wrdata_fifo. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+