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| author | Ataberk <olgunataberk@gmail.com> | 2024-05-02 17:22:05 +0200 |
|---|---|---|
| committer | Ataberk <olgunataberk@gmail.com> | 2024-05-02 17:22:05 +0200 |
| commit | 7721980589f4c7fa811689e815a77d63f2556497 (patch) | |
| tree | ded507bcfb0aeddb7ef647dd3888ef93ff12e630 /projects/U50-HBM/U50-HBM.srcs/sim_1 | |
| parent | 82b4ae69fa5fa8728b7aa9a513a9a27fb14a5f78 (diff) | |
| download | dram-bender-7721980589f4c7fa811689e815a77d63f2556497.tar.gz | |
Add sources for U50 HBM2
Diffstat (limited to 'projects/U50-HBM/U50-HBM.srcs/sim_1')
| -rw-r--r-- | projects/U50-HBM/U50-HBM.srcs/sim_1/new/sim_tb_top.v | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/projects/U50-HBM/U50-HBM.srcs/sim_1/new/sim_tb_top.v b/projects/U50-HBM/U50-HBM.srcs/sim_1/new/sim_tb_top.v new file mode 100644 index 0000000..0f3824f --- /dev/null +++ b/projects/U50-HBM/U50-HBM.srcs/sim_1/new/sim_tb_top.v @@ -0,0 +1,43 @@ +`timescale 1ps / 1ps + +module sim_tb_top; + + // common signals + reg c0_sys_clk_p; + reg c0_sys_clk_n; + reg sys_rst_l; + + softmc_top UUT( + .c0_sys_clk_p(c0_sys_clk_p), + .c0_sys_clk_n(c0_sys_clk_n), + .sys_rst_l(sys_rst_l) + + ); + + initial + c0_sys_clk_p = 1'b0; + always + c0_sys_clk_p = #(10000/2.0) ~c0_sys_clk_p; + + initial + c0_sys_clk_n = 1'b1; + always + c0_sys_clk_n = #(10000/2.0) ~c0_sys_clk_n; + + + initial begin + sys_rst_l = 1'b0; + #200000; + sys_rst_l = 1'b0; + #4500000; + sys_rst_l = 1'b1; + end + + + + + + + + +endmodule |
