Add sources for U50 HBM2

8 files changed, 4862 insertions, 0 deletions

diff --git a/projects/U50-HBM/verilog/HBM_adapter.v b/projects/U50-HBM/verilog/HBM_adapter.v
new file mode 100644
index 0000000..7a887ab
--- /dev/null
+++ b/projects/U50-HBM/verilog/HBM_adapter.v
@@ -0,0 +1,215 @@
+`include "parameters.vh"
+`include "project.vh"
+
+module HBM_adapter(
+      // common signals
+      input                                             c0_sys_clk_p,
+      input                                             sys_rst,
+      input                                             fab_clk,
+      input                                             dfi_clk,
+      input                                             dfi_rst_n,
+      
+      // ddr_pipeline <-> HBM_adapter
+      input [3:0]                 ddr_write,
+      input [3:0]                 ddr_read,
+      input [3:0]                 ddr_pre,
+      input [3:0]                 ddr_act,
+      input [3:0]                 ddr_ref,
+      input [3:0]                 hbm_sel_ch,
+      input [3:0]                 ddr_nop,
+      input [3:0]                 ddr_ap,
+      input [3:0]                 ddr_rank,
+      input [3:0]                 ddr_pall,
+      input [4*`HBM_CH_WIDTH-1:0] hbm_ch,
+      input [4*`BG_WIDTH-1:0]     ddr_bg,
+      input [4*`BANK_WIDTH-1:0]   ddr_bank,
+      input [4*`COL_WIDTH-1:0]    ddr_col,
+      input [4*`ROW_WIDTH-1:0]    ddr_row,
+      input [511:0]               ddr_wdata,
+      
+      output o_dfi_0_init_complete,
+      output o_HBM_ready,
+      
+      // Received by readback engine
+      output [255 : 0] o_dfi_0_dw_rddata_p0,
+      output [255 : 0] o_dfi_0_dw_rddata_p1,
+      output o_dfi_0_dw_rddata_valid,
+      
+      output [6:0] hbm0_temp,
+      output [6:0] hbm1_temp                 
+    );
+    
+    // HBM PHY signals
+    wire dfi_0_init_complete;
+    wire [255 : 0] dfi_0_dw_rddata_p0;
+    wire [255 : 0] dfi_0_dw_rddata_p1;
+    wire [3 : 0] dfi_0_dw_rddata_valid;
+    wire dfi_0_out_rst_n;
+    
+    wire	[2*`ROW_ADDR_WIDTH-1:0]	    row_addr_2;
+    wire	[2*`COL_ADDR_WIDTH-1:0]	    col_addr_2;
+    wire	[2*`BA_ADDR_WIDTH-1:0]	    ba_addr_2;
+    wire	[511:0]                     wrdata_2;
+    wire	[2*`CMD_TYPE_WIDTH-1:0]	    cmd_type_2;
+    wire    [2*`PC_WIDTH-1:0]		    BA4_2;
+    wire    [2*`HBM_CH_WIDTH-1:0]   channel_id_2;
+    
+    /*
+    wire	[4*`ROW_ADDR_WIDTH-1:0]	    row_addr_4;
+    wire	[4*`COL_ADDR_WIDTH-1:0]	    col_addr_4;
+    wire	[4*`BA_ADDR_WIDTH-1:0]	    ba_addr_4;
+    wire	[511:0]                     wrdata_4;
+    wire	[4*`CMD_TYPE_WIDTH-1:0]	    cmd_type_4;
+    wire    [4*`PC_WIDTH-1:0]		    BA4_4;
+    */
+    
+    wire w_dfi_0_dw_rddata_valid;
+    wire [255:0] w_dfi_0_dw_rddata_p0;
+    wire [255:0] w_dfi_0_dw_rddata_p1;
+      
+    wire HBM_ready;
+    
+    wire [1023:0] wrdata;
+    wire [511:0]  o_wrdata;
+    wire [127:0]  fifo_data;
+    wire [63:0]   o_fifo_data;
+    
+    assign o_dfi_0_dw_rddata_p0     = w_dfi_0_dw_rddata_p0;
+    assign o_dfi_0_dw_rddata_p1     = w_dfi_0_dw_rddata_p1;
+    assign o_dfi_0_dw_rddata_valid  = w_dfi_0_dw_rddata_valid;
+    assign o_dfi_0_init_complete    = dfi_0_init_complete;
+    assign o_HBM_ready              = HBM_ready;
+    
+    
+    cmd_gen cmd_genn(
+      .clk(fab_clk),
+      .rst(~HBM_ready),
+      
+      // ddr_pipeline <-> HBM_adapter
+      .ddr_write(ddr_write),  
+      .ddr_read(ddr_read),  
+      .ddr_pre(ddr_pre),    
+      .ddr_act(ddr_act),    
+      .ddr_ref(ddr_ref),    
+      .hbm_sel_ch(hbm_sel_ch),
+      .hbm_ch(hbm_ch),      
+      .ddr_nop(ddr_nop),    
+      .ddr_ap(ddr_ap),    
+      .ddr_rank(ddr_rank), 
+      .ddr_pall(ddr_pall), 
+      .ddr_bg(ddr_bg),    
+      .ddr_bank(ddr_bank),  
+      .ddr_col(ddr_col),    
+      .ddr_row(ddr_row),    
+      .ddr_wdata(ddr_wdata),
+      
+      /*
+      .row_addr_4(row_addr_4),
+      .col_addr_4(col_addr_4),
+      .ba_addr_4(ba_addr_4),
+      .wrdata_4(wrdata_4),
+      .cmd_type_4(cmd_type_4),
+      .BA4_4(BA4_4)
+      */
+      .fifo_data(fifo_data),
+      .wrdata(wrdata)
+      
+    );
+    
+    cmd_fifo cmd_fifo (
+        .srst(~dfi_rst_n),
+        .wr_clk(fab_clk),
+        .rd_clk(dfi_clk),
+        .din(fifo_data),
+        .wr_en(1'b1), // not sure of this
+        .rd_en(1'b1),
+        .dout(o_fifo_data)
+        //.full(),
+        //.empty(),
+        //.wr_rst_busy(),
+        //.rd_rst_busy()
+    );
+    
+    wrdata_fifo wrdata_fifo (
+        .srst(~dfi_rst_n),
+        .wr_clk(fab_clk),
+        .rd_clk(dfi_clk),
+        .din(wrdata),
+        .wr_en(1'b1),
+        .rd_en(1'b1),
+        .dout(o_wrdata)
+        //.full(),
+        //.empty(),
+        //.wr_rst_busy(),
+        //.rd_rst_busy()
+    );
+    
+    /*
+    (* dont_touch = "yes" *) cmd_buf cmd_buff(
+        .dfi_clk(dfi_clk),
+    	.dfi_rst_n(dfi_rst_n),
+    	
+    	.row_addr_4(row_addr_4),
+		.col_addr_4(col_addr_4),
+		.ba_addr_4(ba_addr_4),
+		.wrdata_4(wrdata_4),
+		.cmd_type_4(cmd_type_4),
+		.BA4_4(BA4_4),
+		
+		.row_addr_2(row_addr_2),
+		.col_addr_2(col_addr_2),
+		.ba_addr_2(ba_addr_2),
+		.wrdata_2(wrdata_2),
+		.cmd_type_2(cmd_type_2),
+		.BA4_2(BA4_2)
+    );
+    */
+    
+    controller_top ctrl_top(
+		// Input these to HBM_interface
+		.row_addr(o_fifo_data[2*`CMD_TYPE_WIDTH +: 2*`ROW_ADDR_WIDTH]),
+		.col_addr(o_fifo_data[2*`ROW_ADDR_WIDTH + 2*`CMD_TYPE_WIDTH  +: 2*`COL_ADDR_WIDTH]),
+		.ba_addr(o_fifo_data[2*`ROW_ADDR_WIDTH + 2*`CMD_TYPE_WIDTH + 2*`COL_ADDR_WIDTH +: 2*`BA_ADDR_WIDTH]),
+		.i_wrdata(o_wrdata),
+		.cmd_type(o_fifo_data[0 +: 2*`CMD_TYPE_WIDTH]),
+		.BA4(o_fifo_data[2*`ROW_ADDR_WIDTH + 2*`CMD_TYPE_WIDTH + 2*`COL_ADDR_WIDTH + 2*`BA_ADDR_WIDTH +: 2*`PC_WIDTH]),
+		.channel_id(o_fifo_data[2*`ROW_ADDR_WIDTH + 2*`CMD_TYPE_WIDTH + 2*`COL_ADDR_WIDTH + 2*`BA_ADDR_WIDTH + 2*`PC_WIDTH  +: 2*`HBM_CH_WIDTH]),
+		
+		.dfi_clk(dfi_clk),
+    	.dfi_rst_n(dfi_rst_n),
+    	
+    	// Input these to HBM PHY IP
+		.HBM_REF_CLK_0(c0_sys_clk_p),
+		.HBM_REF_CLK_1(c0_sys_clk_p),
+	    .APB_0_PCLK(c0_sys_clk_p),
+		.APB_0_PRESET_N(sys_rst),
+		.APB_1_PCLK(c0_sys_clk_p),
+		.APB_1_PRESET_N(sys_rst),
+		
+		.hbm0_temp(hbm0_temp),
+		.hbm1_temp(hbm1_temp),
+		
+		.dfi_0_init_complete(dfi_0_init_complete),
+		.dfi_0_dw_rddata_p0(dfi_0_dw_rddata_p0),
+		.dfi_0_dw_rddata_p1(dfi_0_dw_rddata_p1),
+		.dfi_0_dw_rddata_valid(dfi_0_dw_rddata_valid),
+		.dfi_0_out_rst_n(dfi_0_out_rst_n),
+		.ready(HBM_ready)
+		
+    );
+    
+    
+   cdc_HBM_to_rbe cdc_HBM(
+        .dfi_clk(dfi_clk),
+        .dfi_rst_n(dfi_rst_n),
+        .fab_clk(fab_clk),
+        .dfi_0_dw_rddata_p0(dfi_0_dw_rddata_p0),
+		.dfi_0_dw_rddata_p1(dfi_0_dw_rddata_p1),
+        .dfi_0_dw_rddata_valid(dfi_0_dw_rddata_valid),
+        .o_dfi_0_dw_rddata_p0(w_dfi_0_dw_rddata_p0),
+		.o_dfi_0_dw_rddata_p1(w_dfi_0_dw_rddata_p1),
+		.o_dfi_0_dw_rddata_valid(w_dfi_0_dw_rddata_valid)
+   );
+    
+    
+endmodule
diff --git a/projects/U50-HBM/verilog/HBM_interface.v b/projects/U50-HBM/verilog/HBM_interface.v
new file mode 100644
index 0000000..3600f2b
--- /dev/null
+++ b/projects/U50-HBM/verilog/HBM_interface.v
@@ -0,0 +1,628 @@
+`include "project.vh"
+`include "parameters.vh"
+
+// This module takes 2 DDR commands as input at every dfi_clock cycle
+// The HBM is 2x dfi_clock, which means that it can process 2 commands per dfi_clock cycle
+
+module HBM_interface # (
+		parameter		ROW_ADDR_WIDTH         = 14,
+		parameter		COL_ADDR_WIDTH         = 5,
+		parameter		BA_ADDR_WIDTH          = 4,
+		// these are used for MRS
+		parameter		P_DRIVE_PRECHARGE_CMD  = 114,
+		parameter		P_DRIVE_ACT_CMD        = 240,
+		parameter		P_MRS_CNT              = 8'hc0
+    )(
+	
+	// USER INPUTS
+	input	[2*`ROW_ADDR_WIDTH-1:0]	   row_addr,
+    input	[2*`COL_ADDR_WIDTH-1:0]	   col_addr,
+    input	[2*`BA_ADDR_WIDTH-1:0]	   ba_addr,
+    input	[2*`WR_DATA_WIDTH-1:0]     i_wrdata,
+    input	[2*`CMD_TYPE_WIDTH-1:0]	   cmd_type,
+    input 	[2*`PC_WIDTH-1:0]		   BA4, // indicates target PC
+						
+    // DFI INTERFACE SIGNALS
+    input            	dfi_clk,
+    input           	dfi_rst_n,
+    input            	dfi_rst_buf_n,
+    
+    // Get these from output of PHY. Not used by this module in example design.
+    input            	dfi_ctrlupd_req,
+    input            	dfi_phyupd_ack,  
+    input               apb_complete_0,
+    input               apb_complete_1,
+	input               DRAM_0_STAT_CATTRIP,
+	input  [6:0]        DRAM_0_STAT_TEMP,
+	input               DRAM_1_STAT_CATTRIP,
+	input  [6:0]        DRAM_1_STAT_TEMP,
+    
+    input            	dfi_init_complete,
+	
+    output	           	dfi_init_start,
+    output	[1:0]   	dfi_aw_ck_p0,
+    output  [1:0]   	dfi_aw_cke_p0,
+    output	[11:0]  	dfi_aw_row_p0,
+    output	[15:0]		dfi_aw_col_p0,
+    output	[255:0] 	dfi_dw_wrdata_p0,
+    
+    output  [31:0]		dfi_dw_wrdata_mask_p0,
+    output  [31:0]		dfi_dw_wrdata_dbi_p0,
+    output  [7:0]		dfi_dw_wrdata_par_p0,
+    output  [7:0]		dfi_dw_wrdata_dq_en_p0,
+    output  [7:0]		dfi_dw_wrdata_par_en_p0,
+
+    output  [1:0]		dfi_aw_ck_p1,
+    output  [1:0]		dfi_aw_cke_p1,
+    output	[11:0]		dfi_aw_row_p1,
+    output	[15:0]		dfi_aw_col_p1,
+    output	[255:0]		dfi_dw_wrdata_p1,
+    
+    output  [31:0]		dfi_dw_wrdata_mask_p1,
+    output  [31:0]		dfi_dw_wrdata_dbi_p1,
+    output  [7:0]		dfi_dw_wrdata_par_p1,
+    output  [7:0]		dfi_dw_wrdata_dq_en_p1,
+    output  [7:0]		dfi_dw_wrdata_par_en_p1,
+
+    output           	dfi_aw_ck_dis,
+    output           	dfi_lp_pwr_e_req,
+    output           	dfi_lp_sr_e_req,
+    output           	dfi_lp_pwr_x_e_req,
+    output           	dfi_aw_tx_indx_ld,
+    output           	dfi_dw_tx_indx_ld,
+    output           	dfi_dw_rx_indx_ld,
+    output           	dfi_ctrlupd_ack,
+    output           	dfi_phyupd_req,
+    
+    output              ready
+    
+    );
+    
+    
+    // FSM states
+	localparam IDLE_S		= 2'b00;
+	localparam MRS_S		= 2'b01;
+	localparam READY_S		= 2'b10;
+
+	// Row Commands
+	localparam CMD_RNOP		= 3'b111;
+	localparam CMD_ACT		= 3'b010; // 3rd bit is SID0, set to 0 for this HBM configuration.
+	localparam CMD_PRE		= 3'b011;  
+	localparam CMD_PREA		= 3'b011;
+	localparam CMD_REFSB	= 3'b100;
+	localparam CMD_REF		= 3'b100;
+	localparam CMD_PDE		= 3'b111; // Not needed
+	localparam CMD_SRE		= 3'b100; // Not needed
+	localparam CMD_PDX_SRX	= 3'b111; // Not needed
+	
+	// Column Commands
+	localparam CMD_CNOP		= 4'b1111; 
+	localparam CMD_RD		= 4'b0101;
+	localparam CMD_RDA		= 4'b1101;
+	localparam CMD_WR		= 4'b0001;
+	localparam CMD_WRA		= 4'b1001;
+	localparam CMD_MRS		= 3'b000;
+	
+	// Other parameters
+	localparam PAR		    = 1'b1; // Parity signal
+	localparam BA4_0	    = 1'b0; // Direct commands to PC0
+	localparam BA4_1	    = 1'b1; // Direct commands to PC1
+	
+	localparam LP_MRS0_A 	= 4'b0001;
+	localparam LP_MRS1_A 	= 4'b0001;
+	localparam LP_MRS2_A 	= 4'b0010;
+	localparam LP_MRS3_A 	= 4'b0011;
+	localparam LP_MRS4_A 	= 4'b0100;
+	localparam LP_MRS5_A 	= 4'b0101;
+	localparam LP_MRS6_A 	= 4'b0110;
+	localparam LP_MRS7_A 	= 4'b0111;
+	
+
+	// Wires declaration
+	wire				           w_fsm_rst_b;
+	wire				           w_mrs_lat_cnt_done;
+	wire				           w_precharge_lat_done; 
+	
+	// Registers declaration
+	reg				               r_fsm_rst_b;	
+	reg		[3:0]	               r_fsm_ps;
+	reg		[3:0]	               r_fsm_ns;
+	
+	reg     [11:0]                 r_row_cmd [1:0];
+	reg     [15:0]                 r_col_cmd [1:0];
+	
+	reg	           		           r_dfi_init_start;
+	reg  	[1:0]		           r_dfi_aw_ck_p0;
+	reg     [1:0] 		           r_dfi_aw_cke_p0;
+	reg     [1:0]	 	           r_dfi_aw_ck_p1;
+	reg     [1:0] 		           r_dfi_aw_cke_p1;
+	reg		[3:0]		           cke_cnt; 
+	   
+	reg 	[7:0]		             r_mrs_reg_cnt;
+	reg		[11:0]		             r_activate_lat_cnt;
+	reg 	[11:0]		             r_precharge_lat_cnt;
+	reg					             r_precharge_lat_done; 
+	reg					             r_mrs_lat_cnt_done;
+	
+	
+	reg     [`CMD_TYPE_WIDTH-1:0]     r_cmd_type_ps [1:0];
+	reg     [2*`ROW_ADDR_WIDTH-1:0]   r_row_addr;
+	reg     [2*`COL_ADDR_WIDTH-1:0]   r_col_addr;
+	reg     [2*`BA_ADDR_WIDTH-1:0]    r_ba_addr;
+    reg     [2*`WR_DATA_WIDTH-1:0]    r_wrdata;
+	reg     [2*`PC_WIDTH-1:0]         r_BA4;
+	
+	reg r_ready;
+	
+	integer i;
+	
+	// Unused signals
+    assign dfi_dw_wrdata_mask_p0   = 32'h0000_0000;
+	assign dfi_dw_wrdata_dbi_p0    = 32'h0000_0000;
+	assign dfi_dw_wrdata_par_p0    = 8'h00;
+	assign dfi_dw_wrdata_dq_en_p0  = 8'h00;
+	assign dfi_dw_wrdata_par_en_p0 = 8'h00;
+	
+	assign dfi_dw_wrdata_mask_p1   = 32'h0000_0000;
+	assign dfi_dw_wrdata_dbi_p1    = 32'h0000_0000;
+	assign dfi_dw_wrdata_par_p1    = 8'h00;
+	assign dfi_dw_wrdata_dq_en_p1  = 8'h00;
+	assign dfi_dw_wrdata_par_en_p1 = 8'h00;
+	
+	assign dfi_aw_ck_dis           = 1'b0;
+	assign dfi_lp_pwr_e_req        = 1'b0;
+	assign dfi_lp_sr_e_req         = 1'b0;
+	assign dfi_lp_pwr_x_e_req      = 1'b0;
+	assign dfi_aw_tx_indx_ld       = 1'b0;
+	assign dfi_dw_tx_indx_ld       = 1'b0;
+	assign dfi_dw_rx_indx_ld       = 1'b0;
+	assign dfi_ctrlupd_ack         = 1'b0; // left as Z in example design
+	assign dfi_phyupd_req          = 1'b0;
+	
+	// Output mapping
+	assign dfi_init_start 		   = r_dfi_init_start;
+	
+	assign dfi_aw_ck_p0  		   = r_dfi_aw_ck_p0;
+	assign dfi_aw_cke_p0 		   = r_dfi_aw_cke_p0;
+	assign dfi_aw_row_p0		   = r_row_cmd[0];
+	assign dfi_aw_col_p0		   = r_col_cmd[0];
+	// other version
+	//assign dfi_dw_wrdata_p0 	   = r_wrdata[0 +: `WR_DATA_WIDTH];
+	assign dfi_dw_wrdata_p0 	   = {r_wrdata[192 +: 64], r_wrdata[128 +: 64], r_wrdata[64 +: 64], r_wrdata[0 +: 64]};
+	
+	assign dfi_aw_ck_p1  		   = r_dfi_aw_ck_p1;
+	assign dfi_aw_cke_p1		   = r_dfi_aw_cke_p1;
+	assign dfi_aw_row_p1		   = r_row_cmd[1];
+	assign dfi_aw_col_p1		   = r_col_cmd[1];
+	
+	// other version
+	//assign dfi_dw_wrdata_p1 	   = r_wrdata[`WR_DATA_WIDTH +: `WR_DATA_WIDTH];
+	assign dfi_dw_wrdata_p1 	   = {r_wrdata[448 +: 64], r_wrdata[384 +: 64], r_wrdata[320 +: 64], r_wrdata[256 +: 64]};
+
+	
+	assign ready = r_ready;
+	
+	
+	// Counter to wait for driving CKE signal
+	// We basically wait for initialization to complete, and then drive CKE and CK
+	// After that, we can start performing regular writes/reads
+	
+	always @ (posedge dfi_clk or negedge dfi_rst_n) begin
+	  if (~dfi_rst_n) begin
+		cke_cnt <= 4'h0;
+	  end else if (dfi_init_complete == 1'b1 && cke_cnt != 4'hf) begin
+		cke_cnt <= cke_cnt + 1'b1;
+	  end
+	end
+
+	always @ (posedge dfi_clk or negedge dfi_rst_n) begin
+	  if (~dfi_rst_n) begin
+		r_dfi_aw_cke_p0 <= 2'b00;
+		r_dfi_aw_cke_p1 <= 2'b00;
+		r_dfi_aw_ck_p0  <= 2'b00;
+		r_dfi_aw_ck_p1  <= 2'b00;
+	  end else if (cke_cnt == 4'he) begin
+		r_dfi_aw_cke_p0 <= 2'b11;
+		r_dfi_aw_cke_p1 <= 2'b11;
+		r_dfi_aw_ck_p0  <= 2'b01;
+		r_dfi_aw_ck_p1  <= 2'b01;
+	  end
+	end
+
+	
+	// Driving init_start signal after APB initialization sequence is complete
+	// We read the dfi_rst_buf_n coming from the HBM IP to determine when initialization completes
+	// We can use dfi_rst_buf_n or dfi_init_complete (dfi_rst_buf_n is set by the HBM IP 1CC after dfi_init_complete)
+	
+	always @ (posedge dfi_clk or negedge dfi_rst_n) begin
+	  if (~dfi_rst_n) begin
+		r_dfi_init_start <= 1'b0;
+	  end else if (dfi_rst_buf_n == 1'b1) begin
+		r_dfi_init_start <= 1'b1;
+	  end
+	end
+	
+	// Counter to count pre-charge latency before issuing Mode Registers commands
+	// This makes sure that we correctly set the mode registers
+	
+	always @ (posedge dfi_clk or negedge dfi_rst_n) begin
+	  if (~dfi_rst_n) begin
+		r_precharge_lat_cnt <= 12'h000;
+		r_precharge_lat_done <= 1'b0; 
+	  end else
+	  begin
+		r_precharge_lat_done <= w_precharge_lat_done; 
+		if (r_fsm_ps == IDLE_S && dfi_init_complete == 1'b1 && r_precharge_lat_cnt != P_DRIVE_PRECHARGE_CMD) begin
+		r_precharge_lat_cnt <= r_precharge_lat_cnt + 1'b1;
+	  end
+	  end
+	end
+
+	assign w_precharge_lat_done = (r_precharge_lat_cnt >= P_DRIVE_PRECHARGE_CMD) ? 1'b1 : 1'b0;
+	
+	// FSM is in IDLE_S state until initialization completes
+	// After that, we move to the MRS_S state where we can initialize the mode registers
+	assign w_fsm_rst_b = r_precharge_lat_done && dfi_init_complete;
+	
+	
+	// Counter to count activate latency before issuing ACT command for correct operation
+	// We are using this for the purpose of appropriately setting the Mode Registers
+	// After that, we move to the READY_S state, where we can start sending arbitrary DDR commands
+	
+	always @ (posedge dfi_clk or negedge dfi_rst_n) begin
+	  if (~dfi_rst_n) begin
+		r_activate_lat_cnt <= 12'h000;
+		r_mrs_lat_cnt_done	<= 1'b0; 
+	  end else
+	  begin
+		r_mrs_lat_cnt_done	<= w_mrs_lat_cnt_done; 
+	  if (r_fsm_ps == MRS_S && ( r_mrs_reg_cnt == P_MRS_CNT) && r_activate_lat_cnt != P_DRIVE_ACT_CMD) begin
+		r_activate_lat_cnt <= r_activate_lat_cnt + 1'b1;
+	  end
+	  end
+	end
+
+	assign w_mrs_lat_cnt_done = (r_activate_lat_cnt >= P_DRIVE_ACT_CMD) ? 1'b1 : 0;
+
+	// Counter to count the MR commands sent
+	// Also used to induce tMRC latency between back-to-back MRS commands
+	
+	always @ (posedge dfi_clk or negedge dfi_rst_n) begin
+	  if (~dfi_rst_n) begin
+		r_mrs_reg_cnt <= 8'h00;
+	  end else if ((r_fsm_ps == MRS_S) && (r_mrs_reg_cnt != P_MRS_CNT)) begin
+		r_mrs_reg_cnt <= r_mrs_reg_cnt + 1'b1;
+	  end
+	end
+	
+	
+	
+	// Registers Assignment
+	always @ ( posedge dfi_clk or negedge dfi_rst_n )
+	begin
+		if( dfi_rst_n == 1'b0 )
+		begin
+			r_fsm_ps			<= IDLE_S;
+			r_fsm_rst_b	 		<= 1'b0;
+			
+			r_cmd_type_ps[0] <= {4{1'b1}};
+			r_cmd_type_ps[1] <= {4{1'b1}};
+            r_row_addr 			<= {2*ROW_ADDR_WIDTH{1'b0}};
+            r_col_addr 			<= {2*COL_ADDR_WIDTH{1'b0}};
+            r_ba_addr 			<= {2*BA_ADDR_WIDTH{1'b0}};
+            r_wrdata 			<= {2*`WR_DATA_WIDTH{1'b0}};
+            r_BA4 				<= 2'b00;
+		end
+		else
+		begin
+			r_fsm_ps			<= r_fsm_ns;
+			r_fsm_rst_b	 		<= w_fsm_rst_b;
+			
+			r_cmd_type_ps[0]    <= cmd_type[`CMD_TYPE_WIDTH*0 +: `CMD_TYPE_WIDTH];
+		    r_cmd_type_ps[1]    <= cmd_type[`CMD_TYPE_WIDTH*1 +: `CMD_TYPE_WIDTH];
+			r_row_addr 			<= row_addr;
+			r_col_addr 			<= col_addr;
+			r_ba_addr 			<= ba_addr;
+			r_BA4 				<= BA4;
+			
+			// wrDATA [255:0] corresponds to the data we want to write using the first command
+			// wrDATA [511:256] corresponds to the data we want to write using the second command
+			
+			// Each command can target a different PC
+			// Depending on the target PC, we need to write the data accordingly
+			
+			// Sent to PC0:
+			// {dfi_dw_wrdata_p1[191:128], dfi_dw_wrdata_p1[63:0], dfi_dw_wrdata_p0[191:128], dfi_dw_wrdata_p0[63:0]}
+			// Sent to PC1:
+			// {dfi_dw_wrdata_p1[255:192], dfi_dw_wrdata_p1[127:64], dfi_dw_wrdata_p0[255:192], dfi_dw_wrdata_p0[127:64]}
+			
+			// However, we are still not sure if this is how 256 consecutive bits are stored in memory
+			
+			for (i = 0; i < 2; i = i + 1) begin
+                if (r_cmd_type_ps[i] == `WR || r_cmd_type_ps[i] == `WRA) begin
+                    // This could be one option
+                    
+                    //r_wrdata[0   + 64*BA4[i] +: 64]    <=  i_wrdata[`WR_DATA_WIDTH*i + 0   +: 64];
+                    //r_wrdata[128 + 64*BA4[i] +: 64]    <=  i_wrdata[`WR_DATA_WIDTH*i + 64  +: 64];
+                    //r_wrdata[256 + 64*BA4[i] +: 64]    <=  i_wrdata[`WR_DATA_WIDTH*i + 128 +: 64];
+                    //r_wrdata[384 + 64*BA4[i] +: 64]    <=  i_wrdata[`WR_DATA_WIDTH*i + 192 +: 64];
+                    
+                    // Another option we will use is that we assume wrData [255:0] always targets PC0 and wrData[511:256] always targets PC1
+                    r_wrdata[0   + 64*0 +: 64]    <=  i_wrdata[`WR_DATA_WIDTH*0 + 0   +: 64];
+                    r_wrdata[128 + 64*0 +: 64]    <=  i_wrdata[`WR_DATA_WIDTH*0 + 64  +: 64];
+                    r_wrdata[256 + 64*0 +: 64]    <=  i_wrdata[`WR_DATA_WIDTH*0 + 128 +: 64];
+                    r_wrdata[384 + 64*0 +: 64]    <=  i_wrdata[`WR_DATA_WIDTH*0 + 192 +: 64];
+                    r_wrdata[0   + 64*1 +: 64]    <=  i_wrdata[`WR_DATA_WIDTH*1 + 0   +: 64];
+                    r_wrdata[128 + 64*1 +: 64]    <=  i_wrdata[`WR_DATA_WIDTH*1 + 64  +: 64];
+                    r_wrdata[256 + 64*1 +: 64]    <=  i_wrdata[`WR_DATA_WIDTH*1 + 128 +: 64];
+                    r_wrdata[384 + 64*1 +: 64]    <=  i_wrdata[`WR_DATA_WIDTH*1 + 192 +: 64];
+                end else begin
+                    //r_wrdata[`WR_DATA_WIDTH*i +: `WR_DATA_WIDTH] <= r_wrdata[`WR_DATA_WIDTH*i +: `WR_DATA_WIDTH];
+                end
+            end
+		end
+	end
+
+	// State Transition
+	always @ (*)
+	begin
+		case( r_fsm_ps )
+			IDLE_S:
+			begin
+				if( r_fsm_rst_b == 1'b0  ) begin
+					r_fsm_ns	= IDLE_S;
+				end
+				else begin
+					r_fsm_ns = MRS_S;
+				end
+			end
+			MRS_S: 
+			begin
+				if( r_fsm_rst_b == 1'b0 ) begin
+					r_fsm_ns = IDLE_S;
+				end
+				else begin
+					if( r_mrs_lat_cnt_done == 1'b1 ) begin
+						r_fsm_ns = READY_S;
+					end
+					else begin
+						r_fsm_ns = MRS_S;
+					end
+				end
+			end
+			READY_S:
+			begin
+				if( r_fsm_rst_b == 1'b0 ) begin
+					r_fsm_ns = IDLE_S;
+				end
+				else begin
+					r_fsm_ns = READY_S;
+				end
+			end
+			default:
+			begin
+				r_fsm_ns = IDLE_S;
+			end
+		endcase
+	end
+	
+	// assert ready signal so that other modules know when to start running user program
+	// We cannot use the dfi_init_complete or dfi_0_out_rst_n for this purpose 
+	// since we also need to wait for the MRS sequence to complete
+	
+	always @ ( posedge dfi_clk or negedge dfi_rst_n )
+	begin
+		if( dfi_rst_n == 1'b0 )
+		begin
+		  r_ready <= 1'b0;
+		end else begin
+		  if (r_fsm_ps == READY_S) begin
+		      r_ready <= 1'b1;
+		  end else begin
+		      r_ready <= 1'b0;
+		  end
+		end
+	end
+	
+	// Row Commands
+	always @ ( posedge dfi_clk or negedge dfi_rst_n )
+	begin
+		if( dfi_rst_n == 1'b0 )
+		begin
+			r_row_cmd[0]		<= 12'hfff;
+			r_row_cmd[1]		<= 12'hfff;
+		end
+		else
+		begin
+			case( r_fsm_ps )
+			IDLE_S:
+			begin
+				r_row_cmd[0]		<= 12'hfff;
+				r_row_cmd[1]		<= 12'hfff;
+			end
+			MRS_S: // Initialize Mode Registers
+			begin
+				r_row_cmd[0]		<= 12'hfff;
+				r_row_cmd[1]		<= 12'hfff;
+			end
+			READY_S: // Ready to start performing regular operations
+			begin
+			    // Handle ACT command
+			    // Since we can only issue a single ACT per DFI_CLK cycle, any other command alongside an ACT will be ignored
+			    if (r_cmd_type_ps[0] == `ACTT) begin
+			        // CC1
+                    r_row_cmd[0]	    <= {r_ba_addr[`BA_ADDR_WIDTH*0 + 3], r_row_addr[`ROW_ADDR_WIDTH*0 + 13], r_BA4[0], PAR, r_row_addr[`ROW_ADDR_WIDTH*0+11 +: 2], r_ba_addr[`BA_ADDR_WIDTH*0 +: 3], CMD_ACT};
+                    // CC2
+                    r_row_cmd[1]	    <= {r_row_addr[`ROW_ADDR_WIDTH*0+2 +: 3], PAR, r_row_addr[`ROW_ADDR_WIDTH*0 +: 2], r_row_addr[`ROW_ADDR_WIDTH*0+5 +: 6]};
+			    end else if (r_cmd_type_ps[1] == `ACTT) begin
+			        // CC1
+			        r_row_cmd[0]	    <= {r_ba_addr[`BA_ADDR_WIDTH*1 + 3], r_row_addr[`ROW_ADDR_WIDTH*1 + 13], r_BA4[1], PAR, r_row_addr[`ROW_ADDR_WIDTH*1+11 +: 2], r_ba_addr[`BA_ADDR_WIDTH*1 +: 3], CMD_ACT};
+			        // CC2
+                    r_row_cmd[1]	    <= {r_row_addr[`ROW_ADDR_WIDTH*1+2 +: 3], PAR, r_row_addr[`ROW_ADDR_WIDTH*1 +: 2], r_row_addr[`ROW_ADDR_WIDTH*1+5 +: 6]};
+			    end else begin
+                    for (i = 0; i < 2; i = i + 1) begin
+                        case (r_cmd_type_ps[i])
+                            `RNOP:
+                            begin
+                                r_row_cmd[i]		<= {3'b111, PAR, 5'b11111, CMD_RNOP};
+                            end
+                            `PREE:
+                            begin
+                                r_row_cmd[i]		<= {r_ba_addr[`BA_ADDR_WIDTH*i + 3], 1'b0, r_BA4[i], PAR, 2'b11, r_ba_addr[`BA_ADDR_WIDTH*i +: 3], CMD_PRE};
+                            end
+                            `PREA:
+                            begin
+                                r_row_cmd[i]		<= {2'b11, r_BA4[i], PAR, 5'b11111, CMD_PREA};
+                            end
+                            `REFSB:
+                            begin
+                                r_row_cmd[i]		<= {r_ba_addr[`BA_ADDR_WIDTH*i + 3], 1'b0, r_BA4[i], PAR, 2'b11, r_ba_addr[`BA_ADDR_WIDTH*i +: 3], CMD_REFSB};
+                            end
+                            `REFF:
+                            begin
+                                r_row_cmd[i]		<= {2'b11, r_BA4[i], PAR, 5'b11111, CMD_REF};
+                            end
+                            // Not sure how we can use the following commands or if they work
+                            // They are not necessary for the purpose of DRAM Bender
+                            `PDE:
+                            begin
+                                r_row_cmd[i]		<= {3'b111, PAR, 5'b11111, CMD_PDE};
+                            end
+                            `SREE:
+                            begin
+                                r_row_cmd[i]		<= {3'b111, PAR, 5'b11111, CMD_SRE};
+                            end
+                            `PDX_SRX:
+                            begin
+                                r_row_cmd[i]		<= 12'hfff;
+                            end
+                            default:
+                            begin
+                                r_row_cmd[i]		<= 12'hfff;
+                            end
+                        endcase
+                    end
+                end
+			end
+			default:
+			begin
+				r_row_cmd[0]		<= 12'hfff;
+				r_row_cmd[1]		<= 12'hfff;
+			end
+			endcase
+		end
+	end
+	
+	
+	// Col Commands
+	always @ ( posedge dfi_clk or negedge dfi_rst_n )
+	begin
+		if( dfi_rst_n == 1'b0 )
+		begin
+			r_col_cmd[0]		<= 16'hffff;
+			r_col_cmd[1]		<= 16'hffff;
+		end
+		else
+		begin
+			case( r_fsm_ps )
+			IDLE_S:
+			begin
+				r_col_cmd[0]		<= 16'hffff;
+				r_col_cmd[1]		<= 16'hffff;
+			end
+			MRS_S: // Initialize Mode Registers
+			begin
+				case (r_mrs_reg_cnt)
+				8'h00: begin
+				  r_col_cmd[0] <= 16'h0000; //MR-0
+				  r_col_cmd[1] <= 16'hffff;
+				end
+			 	8'h10: begin
+				  r_col_cmd[0] <= 16'hffff;
+				  //r_col_cmd_p1 <= 16'hea10; //MR-1
+				  r_col_cmd[1] <= 16'ha010; //MR-1
+				end
+			 	8'h20: begin
+				  //r_col_cmd_p0 <= 16'h2e28; //w_T_WL_MRS2 MR-2
+				  r_col_cmd[0] <= {4'b0010, 1'b1, PAR, 2'b10, LP_MRS2_A, 1'b1, CMD_MRS}; //MR-2
+				  r_col_cmd[1] <= 16'hffff;
+				end
+			 	8'h30: begin
+				  r_col_cmd[0] <= 16'hffff;
+				  //r_col_cmd_p1 <= 16'h4138; //MR-3
+				  r_col_cmd[1] <= 16'hc138; //MR-3
+				end
+			 	8'h40: begin
+				  //r_col_cmd_p0 <= 16'h1c40; //MR-4
+				  r_col_cmd[0] <= 16'h0440; //MR-4
+				  r_col_cmd[1] <= 16'hffff;
+				end
+			 	8'h50: begin
+				  r_col_cmd[0] <= 16'hffff;
+				  r_col_cmd[1] <= 16'h0050; //MR-5
+				end
+			 	8'h60: begin
+				  r_col_cmd[0] <= 16'hc060; //MR-6
+				  r_col_cmd[1] <= 16'hffff;
+				end
+			 	8'h70: begin
+				  r_col_cmd[0] <= 16'hffff;
+				  r_col_cmd[1] <= 16'h0270; //MR-7
+				end
+			 	8'h80: begin
+				  r_col_cmd[0] <= 16'h00f0;
+				  r_col_cmd[1] <= 16'hffff; //MR-7
+				end
+				default : begin
+				  r_col_cmd[0] <= 16'hffff;
+				  r_col_cmd[1] <= 16'hffff;
+				end
+				endcase
+			end
+			READY_S: // Ready to start performing regular operations
+			begin
+			    for (i = 0; i < 2; i = i + 1) begin
+                    case (r_cmd_type_ps[i])
+                        `CNOP:
+                        begin
+                            r_col_cmd[i]		<= {5'b11111, PAR, 6'b111111, CMD_CNOP};
+                        end
+                        `RD:
+                        begin
+                            // Here we assume the column address is 5 bits.
+                            // According to JEDEC, it is 6 bits, but only col_addr[5:1] are used (so its actually 5 bits)
+                            // So here col_addr[4:0] corresponds to col_addr[5:1] in the JEDEC standard
+                              r_col_cmd[i]		<= {r_BA4[i], r_col_addr[`COL_ADDR_WIDTH*i+1 +: 4], PAR, r_col_addr[`COL_ADDR_WIDTH*i], 1'b0, r_ba_addr[`BA_ADDR_WIDTH*i +: 4], CMD_RD};                       
+                        end
+                        `RDA:
+                        begin
+                              r_col_cmd[i]		<= {r_BA4[i], r_col_addr[`COL_ADDR_WIDTH*i+1 +: 4], PAR, r_col_addr[`COL_ADDR_WIDTH*i], 1'b0, r_ba_addr[`BA_ADDR_WIDTH*i +: 4], CMD_RDA};                         
+                        end
+                        `WR:
+                        begin
+                              r_col_cmd[i]		<= {r_BA4[i], r_col_addr[`COL_ADDR_WIDTH*i+1 +: 4], PAR, r_col_addr[`COL_ADDR_WIDTH*i], 1'b0, r_ba_addr[`BA_ADDR_WIDTH*i +: 4], CMD_WR};  
+                        end
+                        `WRA:
+                        begin
+                              r_col_cmd[i]		<= {r_BA4[i], r_col_addr[`COL_ADDR_WIDTH*i+1 +: 4], PAR, r_col_addr[`COL_ADDR_WIDTH*i], 1'b0, r_ba_addr[`BA_ADDR_WIDTH*i +: 4], CMD_WRA};  
+                        end
+                        // We don't support sending custom MRS commands from the user side in DRAM Bender
+                        default:
+                        begin
+                              r_col_cmd[i]		<= 16'hffff;
+                        end
+                    endcase
+	            end
+			end
+			default:
+			begin
+				r_col_cmd[0]		<= 16'hffff;
+				r_col_cmd[1]		<= 16'hffff;
+			end
+			endcase
+		end
+	end
+
+endmodule
+
+
diff --git a/projects/U50-HBM/verilog/cdc_HBM_to_rbe.v b/projects/U50-HBM/verilog/cdc_HBM_to_rbe.v
new file mode 100644
index 0000000..05a2164
--- /dev/null
+++ b/projects/U50-HBM/verilog/cdc_HBM_to_rbe.v
@@ -0,0 +1,88 @@
+// Since we are moving from a fast to slow clock domain, 
+// We need to implement this circuitry that will essentially "stretch" the signals coming from the fast clock domain
+// This will make sure that a pulse (in the worst case) will always be captured by the circuitry in the slow clock domain
+
+module cdc_HBM_to_rbe(
+        input dfi_clk,
+        input dfi_rst_n,
+        input fab_clk,
+        
+        // HBM TO DRAM BENDER INTERFACE
+        //input dfi_0_init_complete,
+        input [255 : 0] dfi_0_dw_rddata_p0,
+        input [255 : 0] dfi_0_dw_rddata_p1,
+        input [3:0] dfi_0_dw_rddata_valid,
+
+        output [255 : 0] o_dfi_0_dw_rddata_p0,
+        output [255 : 0] o_dfi_0_dw_rddata_p1,
+        output o_dfi_0_dw_rddata_valid
+        
+    );
+    
+    reg [255 : 0] dfi_0_dw_rddata_p0_r;
+    reg [255 : 0] dfi_0_dw_rddata_p1_r;
+    reg wr_en_r;
+
+    wire [255:0] w_dfi_0_dw_rddata_p0;
+    wire [255:0] w_dfi_0_dw_rddata_p1;
+    wire [511:0] w_dfi_0_dw_rddata;
+    wire w_wr_en;
+    
+    wire fifo_full;
+    wire fifo_empty;
+    wire fifo_valid;
+    
+    always @ (posedge dfi_clk)
+    begin
+        if (~dfi_rst_n) begin
+            dfi_0_dw_rddata_p0_r <= 0;
+            dfi_0_dw_rddata_p1_r <= 0;
+        end else begin
+            // for now I am assuming if rdvalid = 1111 we ignore the read
+            // But in this circuit, there will still be a chance a 1111 will be captured, fix this issue
+            // the thing is i don't know what 1111 is. It should be reading from both PC at the same time.
+            // But in the testbench I have seperated from DRAM Bender I cant replicate this
+            if ((dfi_0_dw_rddata_valid[1:0] == 2'b11) ^ (dfi_0_dw_rddata_valid[3:2] == 2'b11)) begin
+                if ((dfi_0_dw_rddata_valid == 4'b0011)) begin
+                    dfi_0_dw_rddata_p0_r <= {dfi_0_dw_rddata_p1[191:128], dfi_0_dw_rddata_p1[63:0], dfi_0_dw_rddata_p0[191:128], dfi_0_dw_rddata_p0[63:0]};
+                    dfi_0_dw_rddata_p1_r <= 0;
+                end else if ((dfi_0_dw_rddata_valid == 4'b1100)) begin
+                    dfi_0_dw_rddata_p0_r <= 0;
+                    dfi_0_dw_rddata_p1_r <= {dfi_0_dw_rddata_p1[255:192], dfi_0_dw_rddata_p1[127:64], dfi_0_dw_rddata_p0[255:192], dfi_0_dw_rddata_p0[127:64]};
+                end
+                wr_en_r <= 1'b1;
+            end else begin
+                dfi_0_dw_rddata_p0_r <= dfi_0_dw_rddata_p0_r;
+                dfi_0_dw_rddata_p1_r <= dfi_0_dw_rddata_p1_r;
+                wr_en_r <= 0;
+            end
+        end
+    end
+
+    assign w_dfi_0_dw_rddata_p0     = dfi_0_dw_rddata_p0_r;
+    assign w_dfi_0_dw_rddata_p1     = dfi_0_dw_rddata_p1_r;
+    assign w_wr_en                  = wr_en_r;
+    
+    assign o_dfi_0_dw_rddata_p0     = w_dfi_0_dw_rddata[255:0];
+    assign o_dfi_0_dw_rddata_p1     = w_dfi_0_dw_rddata[511:256];
+    assign o_dfi_0_dw_rddata_valid  = fifo_valid;
+    
+    
+    cdc_fifo cdc_fifo0 (
+        .srst(~dfi_rst_n),
+        .wr_clk(dfi_clk),
+        .rd_clk(fab_clk),
+        .din({w_dfi_0_dw_rddata_p1, w_dfi_0_dw_rddata_p0}),
+        .wr_en(w_wr_en),
+        .rd_en(1'b1), // not sure what to set this to
+        .dout(w_dfi_0_dw_rddata), // this is sent to the readback engine
+        .full(fifo_full),
+        .empty(fifo_empty),
+        .valid(fifo_valid)
+        //.wr_rst_busy(), // not needed
+        //.rd_rst_busy()
+    );
+    
+       
+        
+endmodule
diff --git a/projects/U50-HBM/verilog/channel_selector.v b/projects/U50-HBM/verilog/channel_selector.v
new file mode 100644
index 0000000..c51b6e2
--- /dev/null
+++ b/projects/U50-HBM/verilog/channel_selector.v
@@ -0,0 +1,497 @@
+`include "project.vh"
+`include "parameters.vh"
+
+
+module channel_selector (
+        // Input these to HBM adapter
+		input	[2*`ROW_ADDR_WIDTH-1:0]	    row_addr,
+		input	[2*`COL_ADDR_WIDTH-1:0]	    col_addr,
+		input	[2*`BA_ADDR_WIDTH-1:0]	    ba_addr,
+		input	[2*`WR_DATA_WIDTH-1:0]      i_wrdata,
+		input	[2*`CMD_TYPE_WIDTH-1:0]	    cmd_type,
+		input 	[2*`PC_WIDTH-1:0]		    BA4, // indicates target PC
+		input   [2*`HBM_CH_WIDTH-1:0]   channel_id,
+		
+		input            	dfi_clk,
+    	input           	dfi_rst_n,
+        
+        // CH0
+        /*input dfi_0_init_complete,
+		input [255 : 0] dfi_0_dw_rddata_p0,
+		input [255 : 0] dfi_0_dw_rddata_p1,
+		input [3 : 0] dfi_0_dw_rddata_valid,
+		input dfi_0_out_rst_n,
+		input ready_0,
+		
+		// CH1
+        input dfi_1_init_complete,
+		input [255 : 0] dfi_1_dw_rddata_p0,
+		input [255 : 0] dfi_1_dw_rddata_p1,
+		input [3 : 0] dfi_1_dw_rddata_valid,
+		input dfi_1_out_rst_n,
+		input ready_1,
+		
+		// CH2
+        input dfi_2_init_complete,
+		input [255 : 0] dfi_2_dw_rddata_p0,
+		input [255 : 0] dfi_2_dw_rddata_p1,
+		input [3 : 0] dfi_2_dw_rddata_valid,
+		input dfi_2_out_rst_n,
+		input ready_2,
+		
+		// CH3
+        input dfi_3_init_complete,
+		input [255 : 0] dfi_3_dw_rddata_p0,
+		input [255 : 0] dfi_3_dw_rddata_p1,
+		input [3 : 0] dfi_3_dw_rddata_valid,
+		input dfi_3_out_rst_n,
+		input ready_3,
+		
+		// CH4
+        input dfi_4_init_complete,
+		input [255 : 0] dfi_4_dw_rddata_p0,
+		input [255 : 0] dfi_4_dw_rddata_p1,
+		input [3 : 0] dfi_4_dw_rddata_valid,
+		input dfi_4_out_rst_n,
+		input ready_4,
+		
+		// CH5
+        input dfi_5_init_complete,
+		input [255 : 0] dfi_5_dw_rddata_p0,
+		input [255 : 0] dfi_5_dw_rddata_p1,
+		input [3 : 0] dfi_5_dw_rddata_valid,
+		input dfi_5_out_rst_n,
+		input ready_5,
+		
+		// CH6
+        input dfi_6_init_complete,
+		input [255 : 0] dfi_6_dw_rddata_p0,
+		input [255 : 0] dfi_6_dw_rddata_p1,
+		input [3 : 0] dfi_6_dw_rddata_valid,
+		input dfi_6_out_rst_n,
+		input ready_6,
+		
+		// CH7
+        input dfi_7_init_complete,
+		input [255 : 0] dfi_7_dw_rddata_p0,
+		input [255 : 0] dfi_7_dw_rddata_p1,
+		input [3 : 0] dfi_7_dw_rddata_valid,
+		input dfi_7_out_rst_n,
+		input ready_7,*/
+		
+		// CH8
+        input dfi_8_init_complete,
+		input [255 : 0] dfi_8_dw_rddata_p0,
+		input [255 : 0] dfi_8_dw_rddata_p1,
+		input [3 : 0] dfi_8_dw_rddata_valid,
+		input dfi_8_out_rst_n,
+		input ready_8,
+		
+		// CH9
+        input dfi_9_init_complete,
+		input [255 : 0] dfi_9_dw_rddata_p0,
+		input [255 : 0] dfi_9_dw_rddata_p1,
+		input [3 : 0] dfi_9_dw_rddata_valid,
+		input dfi_9_out_rst_n,
+		input ready_9,
+		
+		// CH10
+        input dfi_10_init_complete,
+		input [255 : 0] dfi_10_dw_rddata_p0,
+		input [255 : 0] dfi_10_dw_rddata_p1,
+		input [3 : 0] dfi_10_dw_rddata_valid,
+		input dfi_10_out_rst_n,
+		input ready_10,
+		
+		// CH11
+        input dfi_11_init_complete,
+		input [255 : 0] dfi_11_dw_rddata_p0,
+		input [255 : 0] dfi_11_dw_rddata_p1,
+		input [3 : 0] dfi_11_dw_rddata_valid,
+		input dfi_11_out_rst_n,
+		input ready_11,
+		
+		// CH12
+        input dfi_12_init_complete,
+		input [255 : 0] dfi_12_dw_rddata_p0,
+		input [255 : 0] dfi_12_dw_rddata_p1,
+		input [3 : 0] dfi_12_dw_rddata_valid,
+		input dfi_12_out_rst_n,
+		input ready_12,
+		
+		// CH13
+        input dfi_13_init_complete,
+		input [255 : 0] dfi_13_dw_rddata_p0,
+		input [255 : 0] dfi_13_dw_rddata_p1,
+		input [3 : 0] dfi_13_dw_rddata_valid,
+		input dfi_13_out_rst_n,
+		input ready_13,
+		
+		// CH14
+        input dfi_14_init_complete,
+		input [255 : 0] dfi_14_dw_rddata_p0,
+		input [255 : 0] dfi_14_dw_rddata_p1,
+		input [3 : 0] dfi_14_dw_rddata_valid,
+		input dfi_14_out_rst_n,
+		input ready_14,
+		
+		// CH15
+        input dfi_15_init_complete,
+		input [255 : 0] dfi_15_dw_rddata_p0,
+		input [255 : 0] dfi_15_dw_rddata_p1,
+		input [3 : 0] dfi_15_dw_rddata_valid,
+		input dfi_15_out_rst_n,
+		input ready_15,
+		
+		// output depending on channel chosen
+        output o_ch_dfi_init_complete,
+		output [255 : 0] o_ch_dfi_dw_rddata_p0,
+		output [255 : 0] o_ch_dfi_dw_rddata_p1,
+		output [3 : 0] o_ch_dfi_dw_rddata_valid,
+		output o_ch_dfi_out_rst_n,
+		output o_ch_ready,
+		
+		/*output [2*`CMD_TYPE_WIDTH-1:0] o_0_cmd_type,
+		output [2*`CMD_TYPE_WIDTH-1:0] o_1_cmd_type,
+		output [2*`CMD_TYPE_WIDTH-1:0] o_2_cmd_type,
+		output [2*`CMD_TYPE_WIDTH-1:0] o_3_cmd_type,
+		output [2*`CMD_TYPE_WIDTH-1:0] o_4_cmd_type,
+		output [2*`CMD_TYPE_WIDTH-1:0] o_5_cmd_type,
+		output [2*`CMD_TYPE_WIDTH-1:0] o_6_cmd_type,
+		output [2*`CMD_TYPE_WIDTH-1:0] o_7_cmd_type,*/
+		output [2*`CMD_TYPE_WIDTH-1:0] o_8_cmd_type,
+		output [2*`CMD_TYPE_WIDTH-1:0] o_9_cmd_type,
+		output [2*`CMD_TYPE_WIDTH-1:0] o_10_cmd_type,
+		output [2*`CMD_TYPE_WIDTH-1:0] o_11_cmd_type,
+		output [2*`CMD_TYPE_WIDTH-1:0] o_12_cmd_type,
+		output [2*`CMD_TYPE_WIDTH-1:0] o_13_cmd_type,
+		output [2*`CMD_TYPE_WIDTH-1:0] o_14_cmd_type,
+		output [2*`CMD_TYPE_WIDTH-1:0] o_15_cmd_type,
+		
+		output	[2*`ROW_ADDR_WIDTH-1:0]	    o_row_addr,
+		output	[2*`COL_ADDR_WIDTH-1:0]	    o_col_addr,
+		output	[2*`BA_ADDR_WIDTH-1:0]	    o_ba_addr,
+		output	[2*`WR_DATA_WIDTH-1:0]      o_i_wrdata,
+		output 	[2*`PC_WIDTH-1:0]		    o_BA4 // indicates target PC
+		
+    );
+    
+    /*reg [2*`CMD_TYPE_WIDTH-1:0] r_0_cmd_type, ns_0_cmd_type;
+	reg [2*`CMD_TYPE_WIDTH-1:0] r_1_cmd_type, ns_1_cmd_type;
+	reg [2*`CMD_TYPE_WIDTH-1:0] r_2_cmd_type, ns_2_cmd_type;
+	reg [2*`CMD_TYPE_WIDTH-1:0] r_3_cmd_type, ns_3_cmd_type;
+	reg [2*`CMD_TYPE_WIDTH-1:0] r_4_cmd_type, ns_4_cmd_type;
+	reg [2*`CMD_TYPE_WIDTH-1:0] r_5_cmd_type, ns_5_cmd_type;
+	reg [2*`CMD_TYPE_WIDTH-1:0] r_6_cmd_type, ns_6_cmd_type;
+	reg [2*`CMD_TYPE_WIDTH-1:0] r_7_cmd_type, ns_7_cmd_type;*/
+	reg [2*`CMD_TYPE_WIDTH-1:0] r_8_cmd_type, ns_8_cmd_type;
+	reg [2*`CMD_TYPE_WIDTH-1:0] r_9_cmd_type, ns_9_cmd_type;
+	reg [2*`CMD_TYPE_WIDTH-1:0] r_10_cmd_type, ns_10_cmd_type;
+	reg [2*`CMD_TYPE_WIDTH-1:0] r_11_cmd_type, ns_11_cmd_type;
+	reg [2*`CMD_TYPE_WIDTH-1:0] r_12_cmd_type, ns_12_cmd_type;
+	reg [2*`CMD_TYPE_WIDTH-1:0] r_13_cmd_type, ns_13_cmd_type;
+	reg [2*`CMD_TYPE_WIDTH-1:0] r_14_cmd_type, ns_14_cmd_type;
+	reg [2*`CMD_TYPE_WIDTH-1:0] r_15_cmd_type, ns_15_cmd_type;
+		
+    reg r_ch_dfi_init_complete, ns_ch_dfi_init_complete;
+	reg [255 : 0] r_ch_dfi_dw_rddata_p0, ns_ch_dfi_dw_rddata_p0;
+	reg [255 : 0] r_ch_dfi_dw_rddata_p1, ns_ch_dfi_dw_rddata_p1;
+	reg [3 : 0] r_ch_dfi_dw_rddata_valid, ns_ch_dfi_dw_rddata_valid;
+	reg r_ch_dfi_out_rst_n, ns_ch_dfi_out_rst_n;
+	reg r_ch_ready, ns_ch_ready;
+	
+	reg	[2*`ROW_ADDR_WIDTH-1:0]	    r_row_addr, ns_row_addr;
+    reg	[2*`COL_ADDR_WIDTH-1:0]	    r_col_addr, ns_col_addr;
+    reg	[2*`BA_ADDR_WIDTH-1:0]	    r_ba_addr, ns_ba_addr;
+    reg	[2*`WR_DATA_WIDTH-1:0]      r_i_wrdata, ns_i_wrdata;
+    reg [2*`PC_WIDTH-1:0]		    r_BA4, ns_BA4; // indicates target PC
+		
+		
+    always @* begin
+/*    	ns_0_cmd_type  = `RNOP & `RNOP;
+    	ns_1_cmd_type  = `RNOP & `RNOP;
+    	ns_2_cmd_type  = `RNOP & `RNOP;
+    	ns_3_cmd_type  = `RNOP & `RNOP;
+    	ns_4_cmd_type  = `RNOP & `RNOP;
+    	ns_5_cmd_type  = `RNOP & `RNOP;
+    	ns_6_cmd_type  = `RNOP & `RNOP;
+    	ns_7_cmd_type  = `RNOP & `RNOP;*/
+    	ns_8_cmd_type  = `RNOP & `RNOP;
+    	ns_9_cmd_type  = `RNOP & `RNOP;
+    	ns_10_cmd_type = `RNOP & `RNOP;
+    	ns_11_cmd_type = `RNOP & `RNOP;
+    	ns_12_cmd_type = `RNOP & `RNOP;
+    	ns_13_cmd_type = `RNOP & `RNOP;
+    	ns_14_cmd_type = `RNOP & `RNOP;
+    	ns_15_cmd_type = `RNOP & `RNOP;
+        
+        ns_row_addr = row_addr;
+        ns_col_addr = col_addr;
+        ns_ba_addr = ba_addr;
+        ns_i_wrdata = i_wrdata;
+        ns_BA4 = BA4;
+        
+    	case (channel_id)
+    		/*4'b0000 :  begin
+    			ns_ch_dfi_init_complete 		= dfi_0_init_complete;
+    			ns_ch_dfi_dw_rddata_p0  		= dfi_0_dw_rddata_p0;
+    			ns_ch_dfi_dw_rddata_p1  		= dfi_0_dw_rddata_p1;
+    			ns_ch_dfi_dw_rddata_valid 	= dfi_0_dw_rddata_valid;
+    			ns_ch_dfi_out_rst_n 			= dfi_0_out_rst_n;
+    			ns_ch_ready 					= ready_0;
+    			ns_0_cmd_type                = cmd_type;
+    		end
+    		4'b0001 :  begin
+    			ns_ch_dfi_init_complete 		= dfi_1_init_complete;
+    			ns_ch_dfi_dw_rddata_p0  		= dfi_1_dw_rddata_p0;
+    			ns_ch_dfi_dw_rddata_p1  		= dfi_1_dw_rddata_p1;
+    			ns_ch_dfi_dw_rddata_valid 	= dfi_1_dw_rddata_valid;
+    			ns_ch_dfi_out_rst_n 			= dfi_1_out_rst_n;
+    			ns_ch_ready 					= ready_1;
+    			ns_1_cmd_type                = cmd_type;
+    		end
+    		4'b0010 :  begin
+    			ns_ch_dfi_init_complete 		= dfi_2_init_complete;
+    			ns_ch_dfi_dw_rddata_p0  		= dfi_2_dw_rddata_p0;
+    			ns_ch_dfi_dw_rddata_p1  		= dfi_2_dw_rddata_p1;
+    			ns_ch_dfi_dw_rddata_valid 	= dfi_2_dw_rddata_valid;
+    			ns_ch_dfi_out_rst_n 			= dfi_2_out_rst_n;
+    			ns_ch_ready 					= ready_2;
+    			ns_2_cmd_type                = cmd_type;
+    		end
+    		4'b0011 :  begin
+    			ns_ch_dfi_init_complete 		= dfi_3_init_complete;
+    			ns_ch_dfi_dw_rddata_p0  		= dfi_3_dw_rddata_p0;
+    			ns_ch_dfi_dw_rddata_p1  		= dfi_3_dw_rddata_p1;
+    			ns_ch_dfi_dw_rddata_valid 	= dfi_3_dw_rddata_valid;
+    			ns_ch_dfi_out_rst_n 			= dfi_3_out_rst_n;
+    			ns_ch_ready 					= ready_3;
+    			ns_3_cmd_type                = cmd_type;
+    		end
+    		4'b0100 :  begin
+    			ns_ch_dfi_init_complete 		= dfi_4_init_complete;
+    			ns_ch_dfi_dw_rddata_p0  		= dfi_4_dw_rddata_p0;
+    			ns_ch_dfi_dw_rddata_p1  		= dfi_4_dw_rddata_p1;
+    			ns_ch_dfi_dw_rddata_valid 	= dfi_4_dw_rddata_valid;
+    			ns_ch_dfi_out_rst_n 			= dfi_4_out_rst_n;
+    			ns_ch_ready 					= ready_4;
+    			ns_4_cmd_type                = cmd_type;
+    		end
+    		4'b0101 :  begin
+    			ns_ch_dfi_init_complete 		= dfi_5_init_complete;
+    			ns_ch_dfi_dw_rddata_p0  		= dfi_5_dw_rddata_p0;
+    			ns_ch_dfi_dw_rddata_p1  		= dfi_5_dw_rddata_p1;
+    			ns_ch_dfi_dw_rddata_valid 	= dfi_5_dw_rddata_valid;
+    			ns_ch_dfi_out_rst_n 			= dfi_5_out_rst_n;
+    			ns_ch_ready 					= ready_5;
+    			ns_5_cmd_type                = cmd_type;
+    		end
+    		4'b0110 :  begin
+    			ns_ch_dfi_init_complete 		= dfi_6_init_complete;
+    			ns_ch_dfi_dw_rddata_p0  		= dfi_6_dw_rddata_p0;
+    			ns_ch_dfi_dw_rddata_p1  		= dfi_6_dw_rddata_p1;
+    			ns_ch_dfi_dw_rddata_valid 	= dfi_6_dw_rddata_valid;
+    			ns_ch_dfi_out_rst_n 			= dfi_6_out_rst_n;
+    			ns_ch_ready 					= ready_6;
+    			ns_6_cmd_type                = cmd_type;
+    		end
+    		4'b0111 :  begin
+    			ns_ch_dfi_init_complete 		= dfi_7_init_complete;
+    			ns_ch_dfi_dw_rddata_p0  		= dfi_7_dw_rddata_p0;
+    			ns_ch_dfi_dw_rddata_p1  		= dfi_7_dw_rddata_p1;
+    			ns_ch_dfi_dw_rddata_valid 	= dfi_7_dw_rddata_valid;
+    			ns_ch_dfi_out_rst_n 			= dfi_7_out_rst_n;
+    			ns_ch_ready 					= ready_7;
+    			ns_7_cmd_type                = cmd_type;
+    		end*/
+    		4'b1000 :  begin
+    			ns_ch_dfi_init_complete 		= dfi_8_init_complete;
+    			ns_ch_dfi_dw_rddata_p0  		= dfi_8_dw_rddata_p0;
+    			ns_ch_dfi_dw_rddata_p1  		= dfi_8_dw_rddata_p1;
+    			ns_ch_dfi_dw_rddata_valid 	= dfi_8_dw_rddata_valid;
+    			ns_ch_dfi_out_rst_n 			= dfi_8_out_rst_n;
+    			ns_ch_ready 					= ready_8;
+    			ns_8_cmd_type                = cmd_type;
+    		end
+    		4'b1001 :  begin
+    			ns_ch_dfi_init_complete 		= dfi_9_init_complete;
+    			ns_ch_dfi_dw_rddata_p0  		= dfi_9_dw_rddata_p0;
+    			ns_ch_dfi_dw_rddata_p1  		= dfi_9_dw_rddata_p1;
+    			ns_ch_dfi_dw_rddata_valid 	= dfi_9_dw_rddata_valid;
+    			ns_ch_dfi_out_rst_n 			= dfi_9_out_rst_n;
+    			ns_ch_ready 					= ready_9;
+    			ns_9_cmd_type                = cmd_type;
+    		end
+    		4'b1010 :  begin
+    			ns_ch_dfi_init_complete 		= dfi_10_init_complete;
+    			ns_ch_dfi_dw_rddata_p0  		= dfi_10_dw_rddata_p0;
+    			ns_ch_dfi_dw_rddata_p1  		= dfi_10_dw_rddata_p1;
+    			ns_ch_dfi_dw_rddata_valid 	= dfi_10_dw_rddata_valid;
+    			ns_ch_dfi_out_rst_n 			= dfi_10_out_rst_n;
+    			ns_ch_ready 					= ready_10;
+    			ns_10_cmd_type               = cmd_type;
+    		end
+    		4'b1011 :  begin
+    			ns_ch_dfi_init_complete 		= dfi_11_init_complete;
+    			ns_ch_dfi_dw_rddata_p0  		= dfi_11_dw_rddata_p0;
+    			ns_ch_dfi_dw_rddata_p1  		= dfi_11_dw_rddata_p1;
+    			ns_ch_dfi_dw_rddata_valid 	= dfi_11_dw_rddata_valid;
+    			ns_ch_dfi_out_rst_n 			= dfi_11_out_rst_n;
+    			ns_ch_ready 					= ready_11;
+    			ns_11_cmd_type               = cmd_type;
+    		end
+    		4'b1100 :  begin
+    			ns_ch_dfi_init_complete 		= dfi_12_init_complete;
+    			ns_ch_dfi_dw_rddata_p0  		= dfi_12_dw_rddata_p0;
+    			ns_ch_dfi_dw_rddata_p1  		= dfi_12_dw_rddata_p1;
+    			ns_ch_dfi_dw_rddata_valid 	= dfi_12_dw_rddata_valid;
+    			ns_ch_dfi_out_rst_n 			= dfi_12_out_rst_n;
+    			ns_ch_ready 					= ready_12;
+    			ns_12_cmd_type               = cmd_type;
+    		end
+    		4'b1101 :  begin
+    			ns_ch_dfi_init_complete 		= dfi_13_init_complete;
+    			ns_ch_dfi_dw_rddata_p0  		= dfi_13_dw_rddata_p0;
+    			ns_ch_dfi_dw_rddata_p1  		= dfi_13_dw_rddata_p1;
+    			ns_ch_dfi_dw_rddata_valid 	= dfi_13_dw_rddata_valid;
+    			ns_ch_dfi_out_rst_n 			= dfi_13_out_rst_n;
+    			ns_ch_ready 					= ready_13;
+    			ns_13_cmd_type               = cmd_type;
+    		end
+    		4'b1110 :  begin
+    			ns_ch_dfi_init_complete 		= dfi_14_init_complete;
+    			ns_ch_dfi_dw_rddata_p0  		= dfi_14_dw_rddata_p0;
+    			ns_ch_dfi_dw_rddata_p1  		= dfi_14_dw_rddata_p1;
+    			ns_ch_dfi_dw_rddata_valid 	= dfi_14_dw_rddata_valid;
+    			ns_ch_dfi_out_rst_n 			= dfi_14_out_rst_n;
+    			ns_ch_ready 					= ready_14;
+    			ns_14_cmd_type               = cmd_type;
+    		end
+    		4'b1111 :  begin
+    			ns_ch_dfi_init_complete 		= dfi_15_init_complete;
+    			ns_ch_dfi_dw_rddata_p0  		= dfi_15_dw_rddata_p0;
+    			ns_ch_dfi_dw_rddata_p1  		= dfi_15_dw_rddata_p1;
+    			ns_ch_dfi_dw_rddata_valid 	= dfi_15_dw_rddata_valid;
+    			ns_ch_dfi_out_rst_n 			= dfi_15_out_rst_n;
+    			ns_ch_ready 					= ready_15;
+    			ns_15_cmd_type               = cmd_type;
+    		end
+    		default :  begin
+    			ns_ch_dfi_init_complete 		= dfi_8_init_complete;
+    			ns_ch_dfi_dw_rddata_p0  		= dfi_8_dw_rddata_p0;
+    			ns_ch_dfi_dw_rddata_p1  		= dfi_8_dw_rddata_p1;
+    			ns_ch_dfi_dw_rddata_valid 	= dfi_8_dw_rddata_valid;
+    			ns_ch_dfi_out_rst_n 			= dfi_8_out_rst_n;
+    			ns_ch_ready 					= ready_8;
+    			ns_8_cmd_type                = cmd_type;
+    		/*	ns_0_cmd_type  = `RNOP & `RNOP;
+                ns_1_cmd_type  = `RNOP & `RNOP;
+                ns_2_cmd_type  = `RNOP & `RNOP;
+                ns_3_cmd_type  = `RNOP & `RNOP;
+                ns_4_cmd_type  = `RNOP & `RNOP;
+                ns_5_cmd_type  = `RNOP & `RNOP;
+                ns_6_cmd_type  = `RNOP & `RNOP;
+                ns_7_cmd_type  = `RNOP & `RNOP;*/
+           /*     ns_8_cmd_type  = `RNOP & `RNOP;
+                ns_9_cmd_type  = `RNOP & `RNOP;
+                ns_10_cmd_type = `RNOP & `RNOP;
+                ns_11_cmd_type = `RNOP & `RNOP;
+                ns_12_cmd_type = `RNOP & `RNOP;
+                ns_13_cmd_type = `RNOP & `RNOP;
+                ns_14_cmd_type = `RNOP & `RNOP;
+                ns_15_cmd_type = `RNOP & `RNOP;*/
+    		end
+    	endcase
+    end
+    
+    always @ (posedge dfi_clk) begin
+        if (!dfi_rst_n) begin
+            r_ch_dfi_init_complete 		= 0;
+            r_ch_dfi_dw_rddata_p0  		= 0;
+            r_ch_dfi_dw_rddata_p1  		= 0;
+            r_ch_dfi_dw_rddata_valid 	    = 0;
+            r_ch_dfi_out_rst_n 			= 0;
+            r_ch_ready 					= 0;
+      /*      r_0_cmd_type  = `RNOP & `RNOP;
+            r_1_cmd_type  = `RNOP & `RNOP;
+            r_2_cmd_type  = `RNOP & `RNOP;
+            r_3_cmd_type  = `RNOP & `RNOP;
+            r_4_cmd_type  = `RNOP & `RNOP;
+            r_5_cmd_type  = `RNOP & `RNOP;
+            r_6_cmd_type  = `RNOP & `RNOP;
+            r_7_cmd_type  = `RNOP & `RNOP;*/
+            r_8_cmd_type  = `RNOP & `RNOP;
+            r_9_cmd_type  = `RNOP & `RNOP;
+            r_10_cmd_type = `RNOP & `RNOP;
+            r_11_cmd_type = `RNOP & `RNOP;
+            r_12_cmd_type = `RNOP & `RNOP;
+            r_13_cmd_type = `RNOP & `RNOP;
+            r_14_cmd_type = `RNOP & `RNOP;
+            r_15_cmd_type = `RNOP & `RNOP;
+            r_row_addr = 0;
+            r_col_addr = 0;
+            r_ba_addr = 0;
+            r_i_wrdata = 0;
+            r_BA4 = 0;
+        end else begin
+            r_ch_dfi_init_complete 		= ns_ch_dfi_init_complete;
+            r_ch_dfi_dw_rddata_p0  		= ns_ch_dfi_dw_rddata_p0;
+            r_ch_dfi_dw_rddata_p1  		= ns_ch_dfi_dw_rddata_p1;
+            r_ch_dfi_dw_rddata_valid 	    = ns_ch_dfi_dw_rddata_valid;
+            r_ch_dfi_out_rst_n 			= ns_ch_dfi_out_rst_n;
+            r_ch_ready 					= ns_ch_ready;
+   /*         r_0_cmd_type  = ns_0_cmd_type;
+            r_1_cmd_type  = ns_1_cmd_type;
+            r_2_cmd_type  = ns_2_cmd_type;
+            r_3_cmd_type  = ns_3_cmd_type;
+            r_4_cmd_type  = ns_4_cmd_type;
+            r_5_cmd_type  = ns_5_cmd_type;
+            r_6_cmd_type  = ns_6_cmd_type;
+            r_7_cmd_type  = ns_7_cmd_type;*/
+            r_8_cmd_type  = ns_8_cmd_type;
+            r_9_cmd_type  = ns_9_cmd_type;
+            r_10_cmd_type = ns_10_cmd_type;
+            r_11_cmd_type = ns_11_cmd_type;
+            r_12_cmd_type = ns_12_cmd_type;
+            r_13_cmd_type = ns_13_cmd_type;
+            r_14_cmd_type = ns_14_cmd_type;
+            r_15_cmd_type = ns_15_cmd_type;
+            r_row_addr = ns_row_addr;
+            r_col_addr = ns_col_addr;
+            r_ba_addr = ns_ba_addr;
+            r_i_wrdata = ns_i_wrdata;
+            r_BA4 = ns_BA4;
+        end
+    end
+    
+    assign o_ch_dfi_init_complete = r_ch_dfi_init_complete;
+    assign o_ch_dfi_dw_rddata_p0 = r_ch_dfi_dw_rddata_p0;
+    assign o_ch_dfi_dw_rddata_p1 = r_ch_dfi_dw_rddata_p1;
+    assign o_ch_dfi_dw_rddata_valid = r_ch_dfi_dw_rddata_valid;
+    assign o_ch_dfi_out_rst_n = r_ch_dfi_out_rst_n;
+    assign o_ch_ready = r_ch_dfi_out_rst_n;
+/*    
+    assign o_0_cmd_type = r_0_cmd_type;
+    assign o_1_cmd_type = r_1_cmd_type;
+    assign o_2_cmd_type = r_2_cmd_type;
+    assign o_3_cmd_type = r_3_cmd_type;
+    assign o_4_cmd_type = r_4_cmd_type;
+    assign o_5_cmd_type = r_5_cmd_type;
+    assign o_6_cmd_type = r_6_cmd_type;
+    assign o_7_cmd_type = r_7_cmd_type;*/
+    assign o_8_cmd_type = r_8_cmd_type;
+    assign o_9_cmd_type = r_9_cmd_type;
+    assign o_10_cmd_type = r_10_cmd_type;
+    assign o_11_cmd_type = r_11_cmd_type;
+    assign o_12_cmd_type = r_12_cmd_type;
+    assign o_13_cmd_type = r_13_cmd_type;
+    assign o_14_cmd_type = r_14_cmd_type;
+    assign o_15_cmd_type = r_15_cmd_type;
+    
+    assign o_row_addr = r_row_addr;
+    assign o_col_addr = r_col_addr;
+    assign o_ba_addr = r_ba_addr;
+    assign o_i_wrdata = r_i_wrdata;
+    assign o_BA4 = r_BA4;
+    
+endmodule
diff --git a/projects/U50-HBM/verilog/cmd_gen.v b/projects/U50-HBM/verilog/cmd_gen.v
new file mode 100644
index 0000000..3893073
--- /dev/null
+++ b/projects/U50-HBM/verilog/cmd_gen.v
@@ -0,0 +1,189 @@
+`include "project.vh"
+`include "parameters.vh"
+
+// The DRAM Bender programmmable core that generates 4 DDR instructions per cycle and is clocked at 1/4 DDR4 memory clock
+// This is due to the fact that the DDR4 PHY interface can process 4 commands per dfi_clock cycle
+
+// Unlike the DDR4 PHY interface, the HBM PHY can process 2 commands per dfi_clock cycle
+// Since DRAM Bender is designed in a way to generate 4 DDR instructions, we will buffer 4 instructions per fab_clock cycle,
+// and clock the HBM_adapter at 2x fab_clock (e.g. dfi_clock = 2x fab_clock). And then we will have HBM_clock = 2x dfi_clock.
+// In this way, we will still be able to process 4 instructions per fab_clock cycle.
+
+module cmd_gen #(parameter CKE_WIDTH = 1, RANK_WIDTH = 1, DQ_WIDTH = 64, DRAM_CMD_SLOTS = 4,
+				 DATA_BUF_ADDR_WIDTH = 5, DBUF_WIDTH = 4, DQ_BURST = 8)
+	(
+      // common signals
+      input                                             clk,
+      input                                             rst,
+      //input                                             dfi_clk,
+      //input                                             dfi_rst_n,
+      
+      //other control signals
+      //input                                             init_calib_complete,
+      //input                                             process_iseq,
+      
+      // ddr_pipeline <-> outer module if
+      input [3:0]                 ddr_write,
+      input [3:0]                 ddr_read,
+      input [3:0]                 ddr_pre,
+      input [3:0]                 ddr_act,
+      input [3:0]                 ddr_ref,
+      input [3:0]                 hbm_sel_ch, // used for channel select
+      input [3:0]                 ddr_nop,
+      input [3:0]                 ddr_ap,
+    //input [3:0]                 ddr_half_bl,
+      input [3:0]                 ddr_rank, // can be used to indicate PC
+      input [3:0]                 ddr_pall,
+      input [4*`HBM_CH_WIDTH-1:0] hbm_ch,
+      input [4*`BG_WIDTH-1:0]     ddr_bg,
+      input [4*`BANK_WIDTH-1:0]   ddr_bank,
+      input [4*`COL_WIDTH-1:0]    ddr_col,
+      input [4*`ROW_WIDTH-1:0]    ddr_row,
+      input [511:0]               ddr_wdata,
+      
+      //output	[4*`ROW_ADDR_WIDTH-1:0]	   row_addr_4,
+      //output	[4*`COL_ADDR_WIDTH-1:0]	   col_addr_4,
+      //output	[4*`BA_ADDR_WIDTH-1:0]	   ba_addr_4,
+      //output	[511:0]                    wrdata_4,
+      //output	[4*`CMD_TYPE_WIDTH-1:0]	   cmd_type_4,
+      //output 	[4*`PC_WIDTH-1:0]		   BA4_4, // indicates target PC
+      
+      output [127:0]             fifo_data,
+      output [1023:0]            wrdata    // have one output of 1024 bit for fifo, the other signals are now wires. Make sure to layout data as needed.
+      
+    );
+    
+    reg	[4*`ROW_ADDR_WIDTH-1:0]	   row_addr_ns;
+    reg	[4*`COL_ADDR_WIDTH-1:0]	   col_addr_ns;
+    reg	[4*`BA_ADDR_WIDTH-1:0]	   ba_addr_ns;
+    reg	[511:0]                    wrdata_ns;
+    reg	[4*`CMD_TYPE_WIDTH-1:0]	   cmd_type_ns;
+    reg [4*`PC_WIDTH-1:0]	       BA4_ns;
+    reg [4*`HBM_CH_WIDTH-1:0]  channel_id_ns; 
+    
+    reg	[4*`ROW_ADDR_WIDTH-1:0]	   row_addr_r;
+    reg	[4*`COL_ADDR_WIDTH-1:0]	   col_addr_r;
+    reg	[4*`BA_ADDR_WIDTH-1:0]	   ba_addr_r;
+    reg	[511:0]                    wrdata_r;
+    reg	[4*`CMD_TYPE_WIDTH-1:0]	   cmd_type_r;
+    reg [4*`PC_WIDTH-1:0]	       BA4_r;
+    reg [4*`HBM_CH_WIDTH-1:0]  channel_id_r; 
+    
+    integer i;
+    
+    /*
+    assign row_addr_4 = row_addr_r;
+    assign col_addr_4 = col_addr_r;
+    assign ba_addr_4 = ba_addr_r;
+    assign wrdata_4 = wrdata_r;
+    assign cmd_type_4 = cmd_type_r;
+    assign BA4_4 = BA4_r;
+    */
+    
+    assign fifo_data[127:64]    =  {    channel_id_r[0 +: 2*`HBM_CH_WIDTH], 
+                                        BA4_r[0 +: 2*`PC_WIDTH],
+                                        ba_addr_r[0 +: 2*`BA_ADDR_WIDTH], 
+                                        col_addr_r[0 +: 2*`COL_ADDR_WIDTH], 
+                                        row_addr_r[0 +: 2*`ROW_ADDR_WIDTH],
+                                        cmd_type_r[0 +: 2*`CMD_TYPE_WIDTH]    };
+                                    
+    assign fifo_data[63:0]      =  {    channel_id_r[2*`HBM_CH_WIDTH +: 2*`HBM_CH_WIDTH], 
+                                        BA4_r[2*`PC_WIDTH +: 2*`PC_WIDTH], 
+                                        ba_addr_r[2*`BA_ADDR_WIDTH +: 2*`BA_ADDR_WIDTH], 
+                                        col_addr_r[2*`COL_ADDR_WIDTH +: 2*`COL_ADDR_WIDTH], 
+                                        row_addr_r[2*`ROW_ADDR_WIDTH +: 2*`ROW_ADDR_WIDTH],
+                                        cmd_type_r[2*`CMD_TYPE_WIDTH +: 2*`CMD_TYPE_WIDTH]    };
+                                    
+    assign wrdata[511:0]    = wrdata_r; // here we are writing double the data redundantly. If we can fix it its better.
+    assign wrdata[1023:512] = wrdata_r;
+    
+    
+    always @ (*)
+    begin
+        row_addr_ns = {4*`ROW_ADDR_WIDTH{1'b0}};
+        col_addr_ns = {4*`COL_ADDR_WIDTH{1'b0}};
+        ba_addr_ns = {4*`BA_ADDR_WIDTH{1'b0}};
+        cmd_type_ns = {4*`CMD_TYPE_WIDTH{1'b1}};
+        BA4_ns = {4*`PC_WIDTH{1'b0}};
+        wrdata_ns = {512{1'b0}};
+        channel_id_ns = {4*`HBM_CH_WIDTH{1'b0}};
+        
+        for(i = 0 ; i < 4 ; i = i + 1) begin
+            if (ddr_write[i]) begin
+            	if (ddr_ap[i])
+            		cmd_type_ns[`CMD_TYPE_WIDTH*i +: `CMD_TYPE_WIDTH] = `WRA;
+            	else
+            		cmd_type_ns[`CMD_TYPE_WIDTH*i +: `CMD_TYPE_WIDTH] = `WR;
+            end 
+            else if (ddr_read[i]) begin
+            	if (ddr_ap[i])
+            		cmd_type_ns[`CMD_TYPE_WIDTH*i +: `CMD_TYPE_WIDTH] = `RDA;
+            	else
+            		cmd_type_ns[`CMD_TYPE_WIDTH*i +: `CMD_TYPE_WIDTH] = `RD;
+            end
+            else if (ddr_pre[i]) begin
+            	if (ddr_pall[i])
+            		cmd_type_ns[`CMD_TYPE_WIDTH*i +: `CMD_TYPE_WIDTH] = `PREA;
+            	else
+            		cmd_type_ns[`CMD_TYPE_WIDTH*i +: `CMD_TYPE_WIDTH] = `PREE;
+            end
+            else if (ddr_act[i]) begin
+            	cmd_type_ns[`CMD_TYPE_WIDTH*i +: `CMD_TYPE_WIDTH] = `ACTT;
+            end
+            else if (ddr_ref[i]) begin
+            	cmd_type_ns[`CMD_TYPE_WIDTH*i +: `CMD_TYPE_WIDTH] = `REFF;
+            end
+            else if (ddr_nop[i]) begin
+            	cmd_type_ns[`CMD_TYPE_WIDTH*i +: `CMD_TYPE_WIDTH] = `RNOP;
+            end
+            else if (hbm_sel_ch[i]) begin // this is now a command to select channel
+            	cmd_type_ns[`CMD_TYPE_WIDTH*i +: `CMD_TYPE_WIDTH] = `RNOP;
+            	// duplicate channel ID four times. This would make it easier to appropriately select channel.
+            	// This is fine since we initially assume we would need to wait for some delay before switching between channels 
+            	channel_id_ns[0 +: `HBM_CH_WIDTH]                   = hbm_ch[`HBM_CH_WIDTH*i +: `HBM_CH_WIDTH];
+            	channel_id_ns[`HBM_CH_WIDTH +: `HBM_CH_WIDTH]   = hbm_ch[`HBM_CH_WIDTH*i +: `HBM_CH_WIDTH];
+            	channel_id_ns[`HBM_CH_WIDTH*2 +: `HBM_CH_WIDTH] = hbm_ch[`HBM_CH_WIDTH*i +: `HBM_CH_WIDTH];
+            	channel_id_ns[`HBM_CH_WIDTH*3 +: `HBM_CH_WIDTH] = hbm_ch[`HBM_CH_WIDTH*i +: `HBM_CH_WIDTH];
+            end
+            else begin
+            	cmd_type_ns[`CMD_TYPE_WIDTH*i +: `CMD_TYPE_WIDTH] = `RNOP;
+            end
+            
+            row_addr_ns[`ROW_ADDR_WIDTH*i +: `ROW_ADDR_WIDTH] = ddr_row[`ROW_WIDTH*i +: `ROW_ADDR_WIDTH];
+            col_addr_ns[`COL_ADDR_WIDTH*i +: `COL_ADDR_WIDTH] = ddr_col[`COL_WIDTH*i +: `COL_ADDR_WIDTH];
+            ba_addr_ns[`BA_ADDR_WIDTH*i + `BANK_WIDTH +: `BG_WIDTH] = ddr_bg[`BG_WIDTH*i +: `BG_WIDTH];
+            ba_addr_ns[`BA_ADDR_WIDTH*i +: `BANK_WIDTH] = ddr_bank[`BANK_WIDTH*i +: `BANK_WIDTH];
+            BA4_ns[i] = ddr_rank[i]; // In our case it represents the PC
+        end
+        
+        wrdata_ns = ddr_wdata;
+
+    end
+    
+    always @(posedge clk) begin // slow clock
+		if(rst) begin
+		  row_addr_r <= {4*`ROW_ADDR_WIDTH{1'b0}};
+		  col_addr_r <= {4*`COL_ADDR_WIDTH{1'b0}};
+		  ba_addr_r <= {4*`BA_ADDR_WIDTH{1'b0}};
+		  BA4_r <= {4*`PC_WIDTH{1'b0}};
+		  wrdata_r <= {512{1'b0}};
+		  cmd_type_r <= {4*`CMD_TYPE_WIDTH{1'b1}};
+		  channel_id_r <= {4*`HBM_CH_WIDTH{1'b0}};
+		end
+		else begin
+          row_addr_r <= row_addr_ns;
+          col_addr_r <= col_addr_ns;
+          ba_addr_r  <= ba_addr_ns;
+          BA4_r      <= BA4_ns;
+          wrdata_r   <= wrdata_ns;
+          cmd_type_r <= cmd_type_ns;
+          
+          if (hbm_sel_ch[3] | hbm_sel_ch[2] | hbm_sel_ch[1] | hbm_sel_ch[0]) begin // only update channel_id when we have a select channel command. It always needs to be the first command out of the 4.
+            channel_id_r <= channel_id_ns;
+          end else begin    // otherwise, keep value from last select channel command
+            channel_id_r <= channel_id_r;
+          end
+		end
+  	end
+    
+endmodule
diff --git a/projects/U50-HBM/verilog/controller_top.v b/projects/U50-HBM/verilog/controller_top.v
new file mode 100644
index 0000000..bddc113
--- /dev/null
+++ b/projects/U50-HBM/verilog/controller_top.v
@@ -0,0 +1,2820 @@
+`include "project.vh"
+`include "parameters.vh"
+
+module controller_top (
+		// Input these to HBM adapter
+		input	[2*`ROW_ADDR_WIDTH-1:0]	    row_addr,
+		input	[2*`COL_ADDR_WIDTH-1:0]	    col_addr,
+		input	[2*`BA_ADDR_WIDTH-1:0]	    ba_addr,
+		input	[2*`WR_DATA_WIDTH-1:0]      i_wrdata,
+		input	[2*`CMD_TYPE_WIDTH-1:0]	    cmd_type,
+		input 	[2*`PC_WIDTH-1:0]		    BA4, // indicates target PC
+		input   [2*`HBM_CH_WIDTH-1:0]   channel_id,
+		
+		input            	dfi_clk,
+    	input           	dfi_rst_n,
+    	
+    	// Input these to HBM PHY IP
+		input wire HBM_REF_CLK_0,
+		input wire HBM_REF_CLK_1,
+		input wire APB_0_PCLK,
+		input wire APB_0_PRESET_N,
+		input wire APB_1_PCLK,
+		input wire APB_1_PRESET_N,
+		
+		output dfi_0_init_complete,
+		output [255 : 0] dfi_0_dw_rddata_p0,
+		output [255 : 0] dfi_0_dw_rddata_p1,
+		output [3 : 0] dfi_0_dw_rddata_valid,
+		output dfi_0_out_rst_n,
+		output ready,
+		
+		output [6:0] hbm0_temp,
+		output [6:0] hbm1_temp
+    );
+    
+
+    // CHANNEL 0
+	/*wire dfi_0_init_start;
+	wire [1 : 0] dfi_0_aw_ck_p0;
+	wire [1 : 0] dfi_0_aw_cke_p0;
+	wire [11 : 0] dfi_0_aw_row_p0;
+	wire [15 : 0] dfi_0_aw_col_p0;
+	wire [255 : 0] dfi_0_dw_wrdata_p0;
+	wire [31 : 0] dfi_0_dw_wrdata_mask_p0;
+	wire [31 : 0] dfi_0_dw_wrdata_dbi_p0;
+	wire [7 : 0] dfi_0_dw_wrdata_par_p0;
+	wire [7 : 0] dfi_0_dw_wrdata_dq_en_p0;
+	wire [7 : 0] dfi_0_dw_wrdata_par_en_p0;
+	wire [1 : 0] dfi_0_aw_ck_p1;
+	wire [1 : 0] dfi_0_aw_cke_p1;
+	wire [11 : 0] dfi_0_aw_row_p1;
+	wire [15 : 0] dfi_0_aw_col_p1;
+	wire [255 : 0] dfi_0_dw_wrdata_p1;
+	wire [31 : 0] dfi_0_dw_wrdata_mask_p1;
+	wire [31 : 0] dfi_0_dw_wrdata_dbi_p1;
+	wire [7 : 0] dfi_0_dw_wrdata_par_p1;
+	wire [7 : 0] dfi_0_dw_wrdata_dq_en_p1;
+	wire [7 : 0] dfi_0_dw_wrdata_par_en_p1;
+	wire dfi_0_aw_ck_dis;
+	wire dfi_0_lp_pwr_e_req;
+	wire dfi_0_lp_sr_e_req;
+	wire dfi_0_lp_pwr_x_req;
+	wire dfi_0_aw_tx_indx_ld;
+	wire dfi_0_dw_tx_indx_ld;
+	wire dfi_0_dw_rx_indx_ld;
+	wire dfi_0_ctrlupd_ack;
+	wire dfi_0_phyupd_req;
+	
+	wire [255 : 0] w_dfi_0_dw_rddata_p0;
+	wire [31 : 0] dfi_0_dw_rddata_dm_p0;
+	wire [31 : 0] dfi_0_dw_rddata_dbi_p0;
+	wire [7 : 0] dfi_0_dw_rddata_par_p0;
+	wire [255 : 0] w_dfi_0_dw_rddata_p1;
+	wire [31 : 0] dfi_0_dw_rddata_dm_p1;
+	wire [31 : 0] dfi_0_dw_rddata_dbi_p1;
+	wire [7 : 0] dfi_0_dw_rddata_par_p1;
+	//wire [15 : 0] dfi_0_dbi_byte_disable;
+	wire [3 : 0] w_dfi_0_dw_rddata_valid;
+	//wire [7 : 0] dfi_0_dw_derr_n;
+	//wire [1 : 0] dfi_0_aw_aerr_n;
+	wire dfi_0_ctrlupd_req;
+	wire dfi_0_phyupd_ack;
+	//wire dfi_0_clk_init;
+	wire w_dfi_0_init_complete;
+	wire w_dfi_0_out_rst_n;
+	
+	
+	// CHANNEL 1
+	wire dfi_1_init_start;
+	wire [1 : 0] dfi_1_aw_ck_p0;
+	wire [1 : 0] dfi_1_aw_cke_p0;
+	wire [11 : 0] dfi_1_aw_row_p0;
+	wire [15 : 0] dfi_1_aw_col_p0;
+	wire [255 : 0] dfi_1_dw_wrdata_p0;
+	wire [31 : 0] dfi_1_dw_wrdata_mask_p0;
+	wire [31 : 0] dfi_1_dw_wrdata_dbi_p0;
+	wire [7 : 0] dfi_1_dw_wrdata_par_p0;
+	wire [7 : 0] dfi_1_dw_wrdata_dq_en_p0;
+	wire [7 : 0] dfi_1_dw_wrdata_par_en_p0;
+	wire [1 : 0] dfi_1_aw_ck_p1;
+	wire [1 : 0] dfi_1_aw_cke_p1;
+	wire [11 : 0] dfi_1_aw_row_p1;
+	wire [15 : 0] dfi_1_aw_col_p1;
+	wire [255 : 0] dfi_1_dw_wrdata_p1;
+	wire [31 : 0] dfi_1_dw_wrdata_mask_p1;
+	wire [31 : 0] dfi_1_dw_wrdata_dbi_p1;
+	wire [7 : 0] dfi_1_dw_wrdata_par_p1;
+	wire [7 : 0] dfi_1_dw_wrdata_dq_en_p1;
+	wire [7 : 0] dfi_1_dw_wrdata_par_en_p1;
+	wire dfi_1_aw_ck_dis;
+	wire dfi_1_lp_pwr_e_req;
+	wire dfi_1_lp_sr_e_req;
+	wire dfi_1_lp_pwr_x_req;
+	wire dfi_1_aw_tx_indx_ld;
+	wire dfi_1_dw_tx_indx_ld;
+	wire dfi_1_dw_rx_indx_ld;
+	wire dfi_1_ctrlupd_ack;
+	wire dfi_1_phyupd_req;
+	
+	wire [255 : 0] w_dfi_1_dw_rddata_p0;
+	wire [31 : 0] dfi_1_dw_rddata_dm_p0;
+	wire [31 : 0] dfi_1_dw_rddata_dbi_p0;
+	wire [7 : 0] dfi_1_dw_rddata_par_p0;
+	wire [255 : 0] w_dfi_1_dw_rddata_p1;
+	wire [31 : 0] dfi_1_dw_rddata_dm_p1;
+	wire [31 : 0] dfi_1_dw_rddata_dbi_p1;
+	wire [7 : 0] dfi_1_dw_rddata_par_p1;
+	//wire [15 : 0] dfi_1_dbi_byte_disable;
+	wire [3 : 0] w_dfi_1_dw_rddata_valid;
+	//wire [7 : 0] dfi_1_dw_derr_n;
+	//wire [1 : 0] dfi_1_aw_aerr_n;
+	wire dfi_1_ctrlupd_req;
+	wire dfi_1_phyupd_ack;
+	//wire dfi_1_clk_init;
+	wire w_dfi_1_init_complete;
+	wire w_dfi_1_out_rst_n;
+	
+	
+	// CHANNEL 2
+	wire dfi_2_init_start;
+	wire [1 : 0] dfi_2_aw_ck_p0;
+	wire [1 : 0] dfi_2_aw_cke_p0;
+	wire [11 : 0] dfi_2_aw_row_p0;
+	wire [15 : 0] dfi_2_aw_col_p0;
+	wire [255 : 0] dfi_2_dw_wrdata_p0;
+	wire [31 : 0] dfi_2_dw_wrdata_mask_p0;
+	wire [31 : 0] dfi_2_dw_wrdata_dbi_p0;
+	wire [7 : 0] dfi_2_dw_wrdata_par_p0;
+	wire [7 : 0] dfi_2_dw_wrdata_dq_en_p0;
+	wire [7 : 0] dfi_2_dw_wrdata_par_en_p0;
+	wire [1 : 0] dfi_2_aw_ck_p1;
+	wire [1 : 0] dfi_2_aw_cke_p1;
+	wire [11 : 0] dfi_2_aw_row_p1;
+	wire [15 : 0] dfi_2_aw_col_p1;
+	wire [255 : 0] dfi_2_dw_wrdata_p1;
+	wire [31 : 0] dfi_2_dw_wrdata_mask_p1;
+	wire [31 : 0] dfi_2_dw_wrdata_dbi_p1;
+	wire [7 : 0] dfi_2_dw_wrdata_par_p1;
+	wire [7 : 0] dfi_2_dw_wrdata_dq_en_p1;
+	wire [7 : 0] dfi_2_dw_wrdata_par_en_p1;
+	wire dfi_2_aw_ck_dis;
+	wire dfi_2_lp_pwr_e_req;
+	wire dfi_2_lp_sr_e_req;
+	wire dfi_2_lp_pwr_x_req;
+	wire dfi_2_aw_tx_indx_ld;
+	wire dfi_2_dw_tx_indx_ld;
+	wire dfi_2_dw_rx_indx_ld;
+	wire dfi_2_ctrlupd_ack;
+	wire dfi_2_phyupd_req;
+	
+	wire [255 : 0] w_dfi_2_dw_rddata_p0;
+	wire [31 : 0] dfi_2_dw_rddata_dm_p0;
+	wire [31 : 0] dfi_2_dw_rddata_dbi_p0;
+	wire [7 : 0] dfi_2_dw_rddata_par_p0;
+	wire [255 : 0] w_dfi_2_dw_rddata_p1;
+	wire [31 : 0] dfi_2_dw_rddata_dm_p1;
+	wire [31 : 0] dfi_2_dw_rddata_dbi_p1;
+	wire [7 : 0] dfi_2_dw_rddata_par_p1;
+	//wire [15 : 0] dfi_2_dbi_byte_disable;
+	wire [3 : 0] w_dfi_2_dw_rddata_valid;
+	//wire [7 : 0] dfi_2_dw_derr_n;
+	//wire [1 : 0] dfi_2_aw_aerr_n;
+	wire dfi_2_ctrlupd_req;
+	wire dfi_2_phyupd_ack;
+	//wire dfi_2_clk_init;
+	wire w_dfi_2_init_complete;
+	wire w_dfi_2_out_rst_n;
+	
+	
+	// CHANNEL 3
+	wire dfi_3_init_start;
+	wire [1 : 0] dfi_3_aw_ck_p0;
+	wire [1 : 0] dfi_3_aw_cke_p0;
+	wire [11 : 0] dfi_3_aw_row_p0;
+	wire [15 : 0] dfi_3_aw_col_p0;
+	wire [255 : 0] dfi_3_dw_wrdata_p0;
+	wire [31 : 0] dfi_3_dw_wrdata_mask_p0;
+	wire [31 : 0] dfi_3_dw_wrdata_dbi_p0;
+	wire [7 : 0] dfi_3_dw_wrdata_par_p0;
+	wire [7 : 0] dfi_3_dw_wrdata_dq_en_p0;
+	wire [7 : 0] dfi_3_dw_wrdata_par_en_p0;
+	wire [1 : 0] dfi_3_aw_ck_p1;
+	wire [1 : 0] dfi_3_aw_cke_p1;
+	wire [11 : 0] dfi_3_aw_row_p1;
+	wire [15 : 0] dfi_3_aw_col_p1;
+	wire [255 : 0] dfi_3_dw_wrdata_p1;
+	wire [31 : 0] dfi_3_dw_wrdata_mask_p1;
+	wire [31 : 0] dfi_3_dw_wrdata_dbi_p1;
+	wire [7 : 0] dfi_3_dw_wrdata_par_p1;
+	wire [7 : 0] dfi_3_dw_wrdata_dq_en_p1;
+	wire [7 : 0] dfi_3_dw_wrdata_par_en_p1;
+	wire dfi_3_aw_ck_dis;
+	wire dfi_3_lp_pwr_e_req;
+	wire dfi_3_lp_sr_e_req;
+	wire dfi_3_lp_pwr_x_req;
+	wire dfi_3_aw_tx_indx_ld;
+	wire dfi_3_dw_tx_indx_ld;
+	wire dfi_3_dw_rx_indx_ld;
+	wire dfi_3_ctrlupd_ack;
+	wire dfi_3_phyupd_req;
+	
+	wire [255 : 0] w_dfi_3_dw_rddata_p0;
+	wire [31 : 0] dfi_3_dw_rddata_dm_p0;
+	wire [31 : 0] dfi_3_dw_rddata_dbi_p0;
+	wire [7 : 0] dfi_3_dw_rddata_par_p0;
+	wire [255 : 0] w_dfi_3_dw_rddata_p1;
+	wire [31 : 0] dfi_3_dw_rddata_dm_p1;
+	wire [31 : 0] dfi_3_dw_rddata_dbi_p1;
+	wire [7 : 0] dfi_3_dw_rddata_par_p1;
+	//wire [15 : 0] dfi_3_dbi_byte_disable;
+	wire [3 : 0] w_dfi_3_dw_rddata_valid;
+	//wire [7 : 0] dfi_3_dw_derr_n;
+	//wire [1 : 0] dfi_3_aw_aerr_n;
+	wire dfi_3_ctrlupd_req;
+	wire dfi_3_phyupd_ack;
+	//wire dfi_3_clk_init;
+	wire w_dfi_3_init_complete;
+	wire w_dfi_3_out_rst_n;
+	
+	
+	// CHANNEL 4
+	wire dfi_4_init_start;
+	wire [1 : 0] dfi_4_aw_ck_p0;
+	wire [1 : 0] dfi_4_aw_cke_p0;
+	wire [11 : 0] dfi_4_aw_row_p0;
+	wire [15 : 0] dfi_4_aw_col_p0;
+	wire [255 : 0] dfi_4_dw_wrdata_p0;
+	wire [31 : 0] dfi_4_dw_wrdata_mask_p0;
+	wire [31 : 0] dfi_4_dw_wrdata_dbi_p0;
+	wire [7 : 0] dfi_4_dw_wrdata_par_p0;
+	wire [7 : 0] dfi_4_dw_wrdata_dq_en_p0;
+	wire [7 : 0] dfi_4_dw_wrdata_par_en_p0;
+	wire [1 : 0] dfi_4_aw_ck_p1;
+	wire [1 : 0] dfi_4_aw_cke_p1;
+	wire [11 : 0] dfi_4_aw_row_p1;
+	wire [15 : 0] dfi_4_aw_col_p1;
+	wire [255 : 0] dfi_4_dw_wrdata_p1;
+	wire [31 : 0] dfi_4_dw_wrdata_mask_p1;
+	wire [31 : 0] dfi_4_dw_wrdata_dbi_p1;
+	wire [7 : 0] dfi_4_dw_wrdata_par_p1;
+	wire [7 : 0] dfi_4_dw_wrdata_dq_en_p1;
+	wire [7 : 0] dfi_4_dw_wrdata_par_en_p1;
+	wire dfi_4_aw_ck_dis;
+	wire dfi_4_lp_pwr_e_req;
+	wire dfi_4_lp_sr_e_req;
+	wire dfi_4_lp_pwr_x_req;
+	wire dfi_4_aw_tx_indx_ld;
+	wire dfi_4_dw_tx_indx_ld;
+	wire dfi_4_dw_rx_indx_ld;
+	wire dfi_4_ctrlupd_ack;
+	wire dfi_4_phyupd_req;
+	
+	wire [255 : 0] w_dfi_4_dw_rddata_p0;
+	wire [31 : 0] dfi_4_dw_rddata_dm_p0;
+	wire [31 : 0] dfi_4_dw_rddata_dbi_p0;
+	wire [7 : 0] dfi_4_dw_rddata_par_p0;
+	wire [255 : 0] w_dfi_4_dw_rddata_p1;
+	wire [31 : 0] dfi_4_dw_rddata_dm_p1;
+	wire [31 : 0] dfi_4_dw_rddata_dbi_p1;
+	wire [7 : 0] dfi_4_dw_rddata_par_p1;
+	//wire [15 : 0] dfi_4_dbi_byte_disable;
+	wire [3 : 0] w_dfi_4_dw_rddata_valid;
+	//wire [7 : 0] dfi_4_dw_derr_n;
+	//wire [1 : 0] dfi_4_aw_aerr_n;
+	wire dfi_4_ctrlupd_req;
+	wire dfi_4_phyupd_ack;
+	//wire dfi_4_clk_init;
+	wire w_dfi_4_init_complete;
+	wire w_dfi_4_out_rst_n;
+	
+	// CHANNEL 5
+	wire dfi_5_init_start;
+	wire [1 : 0] dfi_5_aw_ck_p0;
+	wire [1 : 0] dfi_5_aw_cke_p0;
+	wire [11 : 0] dfi_5_aw_row_p0;
+	wire [15 : 0] dfi_5_aw_col_p0;
+	wire [255 : 0] dfi_5_dw_wrdata_p0;
+	wire [31 : 0] dfi_5_dw_wrdata_mask_p0;
+	wire [31 : 0] dfi_5_dw_wrdata_dbi_p0;
+	wire [7 : 0] dfi_5_dw_wrdata_par_p0;
+	wire [7 : 0] dfi_5_dw_wrdata_dq_en_p0;
+	wire [7 : 0] dfi_5_dw_wrdata_par_en_p0;
+	wire [1 : 0] dfi_5_aw_ck_p1;
+	wire [1 : 0] dfi_5_aw_cke_p1;
+	wire [11 : 0] dfi_5_aw_row_p1;
+	wire [15 : 0] dfi_5_aw_col_p1;
+	wire [255 : 0] dfi_5_dw_wrdata_p1;
+	wire [31 : 0] dfi_5_dw_wrdata_mask_p1;
+	wire [31 : 0] dfi_5_dw_wrdata_dbi_p1;
+	wire [7 : 0] dfi_5_dw_wrdata_par_p1;
+	wire [7 : 0] dfi_5_dw_wrdata_dq_en_p1;
+	wire [7 : 0] dfi_5_dw_wrdata_par_en_p1;
+	wire dfi_5_aw_ck_dis;
+	wire dfi_5_lp_pwr_e_req;
+	wire dfi_5_lp_sr_e_req;
+	wire dfi_5_lp_pwr_x_req;
+	wire dfi_5_aw_tx_indx_ld;
+	wire dfi_5_dw_tx_indx_ld;
+	wire dfi_5_dw_rx_indx_ld;
+	wire dfi_5_ctrlupd_ack;
+	wire dfi_5_phyupd_req;
+	
+	wire [255 : 0] w_dfi_5_dw_rddata_p0;
+	wire [31 : 0] dfi_5_dw_rddata_dm_p0;
+	wire [31 : 0] dfi_5_dw_rddata_dbi_p0;
+	wire [7 : 0] dfi_5_dw_rddata_par_p0;
+	wire [255 : 0] w_dfi_5_dw_rddata_p1;
+	wire [31 : 0] dfi_5_dw_rddata_dm_p1;
+	wire [31 : 0] dfi_5_dw_rddata_dbi_p1;
+	wire [7 : 0] dfi_5_dw_rddata_par_p1;
+	//wire [15 : 0] dfi_5_dbi_byte_disable;
+	wire [3 : 0] w_dfi_5_dw_rddata_valid;
+	//wire [7 : 0] dfi_5_dw_derr_n;
+	//wire [1 : 0] dfi_5_aw_aerr_n;
+	wire dfi_5_ctrlupd_req;
+	wire dfi_5_phyupd_ack;
+	//wire dfi_5_clk_init;
+	wire w_dfi_5_init_complete;
+	wire w_dfi_5_out_rst_n;
+	
+	
+	// CHANNEL 6
+	wire dfi_6_init_start;
+	wire [1 : 0] dfi_6_aw_ck_p0;
+	wire [1 : 0] dfi_6_aw_cke_p0;
+	wire [11 : 0] dfi_6_aw_row_p0;
+	wire [15 : 0] dfi_6_aw_col_p0;
+	wire [255 : 0] dfi_6_dw_wrdata_p0;
+	wire [31 : 0] dfi_6_dw_wrdata_mask_p0;
+	wire [31 : 0] dfi_6_dw_wrdata_dbi_p0;
+	wire [7 : 0] dfi_6_dw_wrdata_par_p0;
+	wire [7 : 0] dfi_6_dw_wrdata_dq_en_p0;
+	wire [7 : 0] dfi_6_dw_wrdata_par_en_p0;
+	wire [1 : 0] dfi_6_aw_ck_p1;
+	wire [1 : 0] dfi_6_aw_cke_p1;
+	wire [11 : 0] dfi_6_aw_row_p1;
+	wire [15 : 0] dfi_6_aw_col_p1;
+	wire [255 : 0] dfi_6_dw_wrdata_p1;
+	wire [31 : 0] dfi_6_dw_wrdata_mask_p1;
+	wire [31 : 0] dfi_6_dw_wrdata_dbi_p1;
+	wire [7 : 0] dfi_6_dw_wrdata_par_p1;
+	wire [7 : 0] dfi_6_dw_wrdata_dq_en_p1;
+	wire [7 : 0] dfi_6_dw_wrdata_par_en_p1;
+	wire dfi_6_aw_ck_dis;
+	wire dfi_6_lp_pwr_e_req;
+	wire dfi_6_lp_sr_e_req;
+	wire dfi_6_lp_pwr_x_req;
+	wire dfi_6_aw_tx_indx_ld;
+	wire dfi_6_dw_tx_indx_ld;
+	wire dfi_6_dw_rx_indx_ld;
+	wire dfi_6_ctrlupd_ack;
+	wire dfi_6_phyupd_req;
+	
+	wire [255 : 0] w_dfi_6_dw_rddata_p0;
+	wire [31 : 0] dfi_6_dw_rddata_dm_p0;
+	wire [31 : 0] dfi_6_dw_rddata_dbi_p0;
+	wire [7 : 0] dfi_6_dw_rddata_par_p0;
+	wire [255 : 0] w_dfi_6_dw_rddata_p1;
+	wire [31 : 0] dfi_6_dw_rddata_dm_p1;
+	wire [31 : 0] dfi_6_dw_rddata_dbi_p1;
+	wire [7 : 0] dfi_6_dw_rddata_par_p1;
+	//wire [15 : 0] dfi_6_dbi_byte_disable;
+	wire [3 : 0] w_dfi_6_dw_rddata_valid;
+	//wire [7 : 0] dfi_6_dw_derr_n;
+	//wire [1 : 0] dfi_6_aw_aerr_n;
+	wire dfi_6_ctrlupd_req;
+	wire dfi_6_phyupd_ack;
+	//wire dfi_6_clk_init;
+	wire w_dfi_6_init_complete;
+	wire w_dfi_6_out_rst_n;
+	
+	
+	// CHANNEL 7
+	wire dfi_7_init_start;
+	wire [1 : 0] dfi_7_aw_ck_p0;
+	wire [1 : 0] dfi_7_aw_cke_p0;
+	wire [11 : 0] dfi_7_aw_row_p0;
+	wire [15 : 0] dfi_7_aw_col_p0;
+	wire [255 : 0] dfi_7_dw_wrdata_p0;
+	wire [31 : 0] dfi_7_dw_wrdata_mask_p0;
+	wire [31 : 0] dfi_7_dw_wrdata_dbi_p0;
+	wire [7 : 0] dfi_7_dw_wrdata_par_p0;
+	wire [7 : 0] dfi_7_dw_wrdata_dq_en_p0;
+	wire [7 : 0] dfi_7_dw_wrdata_par_en_p0;
+	wire [1 : 0] dfi_7_aw_ck_p1;
+	wire [1 : 0] dfi_7_aw_cke_p1;
+	wire [11 : 0] dfi_7_aw_row_p1;
+	wire [15 : 0] dfi_7_aw_col_p1;
+	wire [255 : 0] dfi_7_dw_wrdata_p1;
+	wire [31 : 0] dfi_7_dw_wrdata_mask_p1;
+	wire [31 : 0] dfi_7_dw_wrdata_dbi_p1;
+	wire [7 : 0] dfi_7_dw_wrdata_par_p1;
+	wire [7 : 0] dfi_7_dw_wrdata_dq_en_p1;
+	wire [7 : 0] dfi_7_dw_wrdata_par_en_p1;
+	wire dfi_7_aw_ck_dis;
+	wire dfi_7_lp_pwr_e_req;
+	wire dfi_7_lp_sr_e_req;
+	wire dfi_7_lp_pwr_x_req;
+	wire dfi_7_aw_tx_indx_ld;
+	wire dfi_7_dw_tx_indx_ld;
+	wire dfi_7_dw_rx_indx_ld;
+	wire dfi_7_ctrlupd_ack;
+	wire dfi_7_phyupd_req;
+	
+	wire [255 : 0] w_dfi_7_dw_rddata_p0;
+	wire [31 : 0] dfi_7_dw_rddata_dm_p0;
+	wire [31 : 0] dfi_7_dw_rddata_dbi_p0;
+	wire [7 : 0] dfi_7_dw_rddata_par_p0;
+	wire [255 : 0] w_dfi_7_dw_rddata_p1;
+	wire [31 : 0] dfi_7_dw_rddata_dm_p1;
+	wire [31 : 0] dfi_7_dw_rddata_dbi_p1;
+	wire [7 : 0] dfi_7_dw_rddata_par_p1;
+	//wire [15 : 0] dfi_7_dbi_byte_disable;
+	wire [3 : 0] w_dfi_7_dw_rddata_valid;
+	//wire [7 : 0] dfi_7_dw_derr_n;
+	//wire [1 : 0] dfi_7_aw_aerr_n;
+	wire dfi_7_ctrlupd_req;
+	wire dfi_7_phyupd_ack;
+	//wire dfi_7_clk_init;
+	wire w_dfi_7_init_complete;
+	wire w_dfi_7_out_rst_n;*/
+	
+	
+	// CHANNEL 8
+	wire dfi_8_init_start;
+	wire [1 : 0] dfi_8_aw_ck_p0;
+	wire [1 : 0] dfi_8_aw_cke_p0;
+	wire [11 : 0] dfi_8_aw_row_p0;
+	wire [15 : 0] dfi_8_aw_col_p0;
+	wire [255 : 0] dfi_8_dw_wrdata_p0;
+	wire [31 : 0] dfi_8_dw_wrdata_mask_p0;
+	wire [31 : 0] dfi_8_dw_wrdata_dbi_p0;
+	wire [7 : 0] dfi_8_dw_wrdata_par_p0;
+	wire [7 : 0] dfi_8_dw_wrdata_dq_en_p0;
+	wire [7 : 0] dfi_8_dw_wrdata_par_en_p0;
+	wire [1 : 0] dfi_8_aw_ck_p1;
+	wire [1 : 0] dfi_8_aw_cke_p1;
+	wire [11 : 0] dfi_8_aw_row_p1;
+	wire [15 : 0] dfi_8_aw_col_p1;
+	wire [255 : 0] dfi_8_dw_wrdata_p1;
+	wire [31 : 0] dfi_8_dw_wrdata_mask_p1;
+	wire [31 : 0] dfi_8_dw_wrdata_dbi_p1;
+	wire [7 : 0] dfi_8_dw_wrdata_par_p1;
+	wire [7 : 0] dfi_8_dw_wrdata_dq_en_p1;
+	wire [7 : 0] dfi_8_dw_wrdata_par_en_p1;
+	wire dfi_8_aw_ck_dis;
+	wire dfi_8_lp_pwr_e_req;
+	wire dfi_8_lp_sr_e_req;
+	wire dfi_8_lp_pwr_x_req;
+	wire dfi_8_aw_tx_indx_ld;
+	wire dfi_8_dw_tx_indx_ld;
+	wire dfi_8_dw_rx_indx_ld;
+	wire dfi_8_ctrlupd_ack;
+	wire dfi_8_phyupd_req;
+	
+	wire [255 : 0] w_dfi_8_dw_rddata_p0;
+	wire [31 : 0] dfi_8_dw_rddata_dm_p0;
+	wire [31 : 0] dfi_8_dw_rddata_dbi_p0;
+	wire [7 : 0] dfi_8_dw_rddata_par_p0;
+	wire [255 : 0] w_dfi_8_dw_rddata_p1;
+	wire [31 : 0] dfi_8_dw_rddata_dm_p1;
+	wire [31 : 0] dfi_8_dw_rddata_dbi_p1;
+	wire [7 : 0] dfi_8_dw_rddata_par_p1;
+	//wire [15 : 0] dfi_8_dbi_byte_disable;
+	wire [3 : 0] w_dfi_8_dw_rddata_valid;
+	//wire [7 : 0] dfi_8_dw_derr_n;
+	//wire [1 : 0] dfi_8_aw_aerr_n;
+	wire dfi_8_ctrlupd_req;
+	wire dfi_8_phyupd_ack;
+	//wire dfi_8_clk_init;
+	wire w_dfi_8_init_complete;
+	wire w_dfi_8_out_rst_n;
+	
+	
+	// CHANNEL 9
+	wire dfi_9_init_start;
+	wire [1 : 0] dfi_9_aw_ck_p0;
+	wire [1 : 0] dfi_9_aw_cke_p0;
+	wire [11 : 0] dfi_9_aw_row_p0;
+	wire [15 : 0] dfi_9_aw_col_p0;
+	wire [255 : 0] dfi_9_dw_wrdata_p0;
+	wire [31 : 0] dfi_9_dw_wrdata_mask_p0;
+	wire [31 : 0] dfi_9_dw_wrdata_dbi_p0;
+	wire [7 : 0] dfi_9_dw_wrdata_par_p0;
+	wire [7 : 0] dfi_9_dw_wrdata_dq_en_p0;
+	wire [7 : 0] dfi_9_dw_wrdata_par_en_p0;
+	wire [1 : 0] dfi_9_aw_ck_p1;
+	wire [1 : 0] dfi_9_aw_cke_p1;
+	wire [11 : 0] dfi_9_aw_row_p1;
+	wire [15 : 0] dfi_9_aw_col_p1;
+	wire [255 : 0] dfi_9_dw_wrdata_p1;
+	wire [31 : 0] dfi_9_dw_wrdata_mask_p1;
+	wire [31 : 0] dfi_9_dw_wrdata_dbi_p1;
+	wire [7 : 0] dfi_9_dw_wrdata_par_p1;
+	wire [7 : 0] dfi_9_dw_wrdata_dq_en_p1;
+	wire [7 : 0] dfi_9_dw_wrdata_par_en_p1;
+	wire dfi_9_aw_ck_dis;
+	wire dfi_9_lp_pwr_e_req;
+	wire dfi_9_lp_sr_e_req;
+	wire dfi_9_lp_pwr_x_req;
+	wire dfi_9_aw_tx_indx_ld;
+	wire dfi_9_dw_tx_indx_ld;
+	wire dfi_9_dw_rx_indx_ld;
+	wire dfi_9_ctrlupd_ack;
+	wire dfi_9_phyupd_req;
+	
+	wire [255 : 0] w_dfi_9_dw_rddata_p0;
+	wire [31 : 0] dfi_9_dw_rddata_dm_p0;
+	wire [31 : 0] dfi_9_dw_rddata_dbi_p0;
+	wire [7 : 0] dfi_9_dw_rddata_par_p0;
+	wire [255 : 0] w_dfi_9_dw_rddata_p1;
+	wire [31 : 0] dfi_9_dw_rddata_dm_p1;
+	wire [31 : 0] dfi_9_dw_rddata_dbi_p1;
+	wire [7 : 0] dfi_9_dw_rddata_par_p1;
+	//wire [15 : 0] dfi_9_dbi_byte_disable;
+	wire [3 : 0] w_dfi_9_dw_rddata_valid;
+	//wire [7 : 0] dfi_9_dw_derr_n;
+	//wire [1 : 0] dfi_9_aw_aerr_n;
+	wire dfi_9_ctrlupd_req;
+	wire dfi_9_phyupd_ack;
+	//wire dfi_9_clk_init;
+	wire w_dfi_9_init_complete;
+	wire w_dfi_9_out_rst_n;
+	
+	
+	// CHANNEL 10
+	wire dfi_10_init_start;
+	wire [1 : 0] dfi_10_aw_ck_p0;
+	wire [1 : 0] dfi_10_aw_cke_p0;
+	wire [11 : 0] dfi_10_aw_row_p0;
+	wire [15 : 0] dfi_10_aw_col_p0;
+	wire [255 : 0] dfi_10_dw_wrdata_p0;
+	wire [31 : 0] dfi_10_dw_wrdata_mask_p0;
+	wire [31 : 0] dfi_10_dw_wrdata_dbi_p0;
+	wire [7 : 0] dfi_10_dw_wrdata_par_p0;
+	wire [7 : 0] dfi_10_dw_wrdata_dq_en_p0;
+	wire [7 : 0] dfi_10_dw_wrdata_par_en_p0;
+	wire [1 : 0] dfi_10_aw_ck_p1;
+	wire [1 : 0] dfi_10_aw_cke_p1;
+	wire [11 : 0] dfi_10_aw_row_p1;
+	wire [15 : 0] dfi_10_aw_col_p1;
+	wire [255 : 0] dfi_10_dw_wrdata_p1;
+	wire [31 : 0] dfi_10_dw_wrdata_mask_p1;
+	wire [31 : 0] dfi_10_dw_wrdata_dbi_p1;
+	wire [7 : 0] dfi_10_dw_wrdata_par_p1;
+	wire [7 : 0] dfi_10_dw_wrdata_dq_en_p1;
+	wire [7 : 0] dfi_10_dw_wrdata_par_en_p1;
+	wire dfi_10_aw_ck_dis;
+	wire dfi_10_lp_pwr_e_req;
+	wire dfi_10_lp_sr_e_req;
+	wire dfi_10_lp_pwr_x_req;
+	wire dfi_10_aw_tx_indx_ld;
+	wire dfi_10_dw_tx_indx_ld;
+	wire dfi_10_dw_rx_indx_ld;
+	wire dfi_10_ctrlupd_ack;
+	wire dfi_10_phyupd_req;
+	
+	wire [255 : 0] w_dfi_10_dw_rddata_p0;
+	wire [31 : 0] dfi_10_dw_rddata_dm_p0;
+	wire [31 : 0] dfi_10_dw_rddata_dbi_p0;
+	wire [7 : 0] dfi_10_dw_rddata_par_p0;
+	wire [255 : 0] w_dfi_10_dw_rddata_p1;
+	wire [31 : 0] dfi_10_dw_rddata_dm_p1;
+	wire [31 : 0] dfi_10_dw_rddata_dbi_p1;
+	wire [7 : 0] dfi_10_dw_rddata_par_p1;
+	//wire [15 : 0] dfi_10_dbi_byte_disable;
+	wire [3 : 0] w_dfi_10_dw_rddata_valid;
+	//wire [7 : 0] dfi_10_dw_derr_n;
+	//wire [1 : 0] dfi_10_aw_aerr_n;
+	wire dfi_10_ctrlupd_req;
+	wire dfi_10_phyupd_ack;
+	//wire dfi_10_clk_init;
+	wire w_dfi_10_init_complete;
+	wire w_dfi_10_out_rst_n;
+	
+	
+	// CHANNEL 11
+	wire dfi_11_init_start;
+	wire [1 : 0] dfi_11_aw_ck_p0;
+	wire [1 : 0] dfi_11_aw_cke_p0;
+	wire [11 : 0] dfi_11_aw_row_p0;
+	wire [15 : 0] dfi_11_aw_col_p0;
+	wire [255 : 0] dfi_11_dw_wrdata_p0;
+	wire [31 : 0] dfi_11_dw_wrdata_mask_p0;
+	wire [31 : 0] dfi_11_dw_wrdata_dbi_p0;
+	wire [7 : 0] dfi_11_dw_wrdata_par_p0;
+	wire [7 : 0] dfi_11_dw_wrdata_dq_en_p0;
+	wire [7 : 0] dfi_11_dw_wrdata_par_en_p0;
+	wire [1 : 0] dfi_11_aw_ck_p1;
+	wire [1 : 0] dfi_11_aw_cke_p1;
+	wire [11 : 0] dfi_11_aw_row_p1;
+	wire [15 : 0] dfi_11_aw_col_p1;
+	wire [255 : 0] dfi_11_dw_wrdata_p1;
+	wire [31 : 0] dfi_11_dw_wrdata_mask_p1;
+	wire [31 : 0] dfi_11_dw_wrdata_dbi_p1;
+	wire [7 : 0] dfi_11_dw_wrdata_par_p1;
+	wire [7 : 0] dfi_11_dw_wrdata_dq_en_p1;
+	wire [7 : 0] dfi_11_dw_wrdata_par_en_p1;
+	wire dfi_11_aw_ck_dis;
+	wire dfi_11_lp_pwr_e_req;
+	wire dfi_11_lp_sr_e_req;
+	wire dfi_11_lp_pwr_x_req;
+	wire dfi_11_aw_tx_indx_ld;
+	wire dfi_11_dw_tx_indx_ld;
+	wire dfi_11_dw_rx_indx_ld;
+	wire dfi_11_ctrlupd_ack;
+	wire dfi_11_phyupd_req;
+	
+	wire [255 : 0] w_dfi_11_dw_rddata_p0;
+	wire [31 : 0] dfi_11_dw_rddata_dm_p0;
+	wire [31 : 0] dfi_11_dw_rddata_dbi_p0;
+	wire [7 : 0] dfi_11_dw_rddata_par_p0;
+	wire [255 : 0] w_dfi_11_dw_rddata_p1;
+	wire [31 : 0] dfi_11_dw_rddata_dm_p1;
+	wire [31 : 0] dfi_11_dw_rddata_dbi_p1;
+	wire [7 : 0] dfi_11_dw_rddata_par_p1;
+	//wire [15 : 0] dfi_11_dbi_byte_disable;
+	wire [3 : 0] w_dfi_11_dw_rddata_valid;
+	//wire [7 : 0] dfi_11_dw_derr_n;
+	//wire [1 : 0] dfi_11_aw_aerr_n;
+	wire dfi_11_ctrlupd_req;
+	wire dfi_11_phyupd_ack;
+	//wire dfi_11_clk_init;
+	wire w_dfi_11_init_complete;
+	wire w_dfi_11_out_rst_n;
+	
+	
+	// CHANNEL 12
+	wire dfi_12_init_start;
+	wire [1 : 0] dfi_12_aw_ck_p0;
+	wire [1 : 0] dfi_12_aw_cke_p0;
+	wire [11 : 0] dfi_12_aw_row_p0;
+	wire [15 : 0] dfi_12_aw_col_p0;
+	wire [255 : 0] dfi_12_dw_wrdata_p0;
+	wire [31 : 0] dfi_12_dw_wrdata_mask_p0;
+	wire [31 : 0] dfi_12_dw_wrdata_dbi_p0;
+	wire [7 : 0] dfi_12_dw_wrdata_par_p0;
+	wire [7 : 0] dfi_12_dw_wrdata_dq_en_p0;
+	wire [7 : 0] dfi_12_dw_wrdata_par_en_p0;
+	wire [1 : 0] dfi_12_aw_ck_p1;
+	wire [1 : 0] dfi_12_aw_cke_p1;
+	wire [11 : 0] dfi_12_aw_row_p1;
+	wire [15 : 0] dfi_12_aw_col_p1;
+	wire [255 : 0] dfi_12_dw_wrdata_p1;
+	wire [31 : 0] dfi_12_dw_wrdata_mask_p1;
+	wire [31 : 0] dfi_12_dw_wrdata_dbi_p1;
+	wire [7 : 0] dfi_12_dw_wrdata_par_p1;
+	wire [7 : 0] dfi_12_dw_wrdata_dq_en_p1;
+	wire [7 : 0] dfi_12_dw_wrdata_par_en_p1;
+	wire dfi_12_aw_ck_dis;
+	wire dfi_12_lp_pwr_e_req;
+	wire dfi_12_lp_sr_e_req;
+	wire dfi_12_lp_pwr_x_req;
+	wire dfi_12_aw_tx_indx_ld;
+	wire dfi_12_dw_tx_indx_ld;
+	wire dfi_12_dw_rx_indx_ld;
+	wire dfi_12_ctrlupd_ack;
+	wire dfi_12_phyupd_req;
+	
+	wire [255 : 0] w_dfi_12_dw_rddata_p0;
+	wire [31 : 0] dfi_12_dw_rddata_dm_p0;
+	wire [31 : 0] dfi_12_dw_rddata_dbi_p0;
+	wire [7 : 0] dfi_12_dw_rddata_par_p0;
+	wire [255 : 0] w_dfi_12_dw_rddata_p1;
+	wire [31 : 0] dfi_12_dw_rddata_dm_p1;
+	wire [31 : 0] dfi_12_dw_rddata_dbi_p1;
+	wire [7 : 0] dfi_12_dw_rddata_par_p1;
+	//wire [15 : 0] dfi_12_dbi_byte_disable;
+	wire [3 : 0] w_dfi_12_dw_rddata_valid;
+	//wire [7 : 0] dfi_12_dw_derr_n;
+	//wire [1 : 0] dfi_12_aw_aerr_n;
+	wire dfi_12_ctrlupd_req;
+	wire dfi_12_phyupd_ack;
+	//wire dfi_12_clk_init;
+	wire w_dfi_12_init_complete;
+	wire w_dfi_12_out_rst_n;
+	
+	
+	// CHANNEL 13
+	wire dfi_13_init_start;
+	wire [1 : 0] dfi_13_aw_ck_p0;
+	wire [1 : 0] dfi_13_aw_cke_p0;
+	wire [11 : 0] dfi_13_aw_row_p0;
+	wire [15 : 0] dfi_13_aw_col_p0;
+	wire [255 : 0] dfi_13_dw_wrdata_p0;
+	wire [31 : 0] dfi_13_dw_wrdata_mask_p0;
+	wire [31 : 0] dfi_13_dw_wrdata_dbi_p0;
+	wire [7 : 0] dfi_13_dw_wrdata_par_p0;
+	wire [7 : 0] dfi_13_dw_wrdata_dq_en_p0;
+	wire [7 : 0] dfi_13_dw_wrdata_par_en_p0;
+	wire [1 : 0] dfi_13_aw_ck_p1;
+	wire [1 : 0] dfi_13_aw_cke_p1;
+	wire [11 : 0] dfi_13_aw_row_p1;
+	wire [15 : 0] dfi_13_aw_col_p1;
+	wire [255 : 0] dfi_13_dw_wrdata_p1;
+	wire [31 : 0] dfi_13_dw_wrdata_mask_p1;
+	wire [31 : 0] dfi_13_dw_wrdata_dbi_p1;
+	wire [7 : 0] dfi_13_dw_wrdata_par_p1;
+	wire [7 : 0] dfi_13_dw_wrdata_dq_en_p1;
+	wire [7 : 0] dfi_13_dw_wrdata_par_en_p1;
+	wire dfi_13_aw_ck_dis;
+	wire dfi_13_lp_pwr_e_req;
+	wire dfi_13_lp_sr_e_req;
+	wire dfi_13_lp_pwr_x_req;
+	wire dfi_13_aw_tx_indx_ld;
+	wire dfi_13_dw_tx_indx_ld;
+	wire dfi_13_dw_rx_indx_ld;
+	wire dfi_13_ctrlupd_ack;
+	wire dfi_13_phyupd_req;
+	
+	wire [255 : 0] w_dfi_13_dw_rddata_p0;
+	wire [31 : 0] dfi_13_dw_rddata_dm_p0;
+	wire [31 : 0] dfi_13_dw_rddata_dbi_p0;
+	wire [7 : 0] dfi_13_dw_rddata_par_p0;
+	wire [255 : 0] w_dfi_13_dw_rddata_p1;
+	wire [31 : 0] dfi_13_dw_rddata_dm_p1;
+	wire [31 : 0] dfi_13_dw_rddata_dbi_p1;
+	wire [7 : 0] dfi_13_dw_rddata_par_p1;
+	//wire [15 : 0] dfi_13_dbi_byte_disable;
+	wire [3 : 0] w_dfi_13_dw_rddata_valid;
+	//wire [7 : 0] dfi_13_dw_derr_n;
+	//wire [1 : 0] dfi_13_aw_aerr_n;
+	wire dfi_13_ctrlupd_req;
+	wire dfi_13_phyupd_ack;
+	//wire dfi_13_clk_init;
+	wire w_dfi_13_init_complete;
+	wire w_dfi_13_out_rst_n;
+	
+	
+	// CHANNEL 14
+	wire dfi_14_init_start;
+	wire [1 : 0] dfi_14_aw_ck_p0;
+	wire [1 : 0] dfi_14_aw_cke_p0;
+	wire [11 : 0] dfi_14_aw_row_p0;
+	wire [15 : 0] dfi_14_aw_col_p0;
+	wire [255 : 0] dfi_14_dw_wrdata_p0;
+	wire [31 : 0] dfi_14_dw_wrdata_mask_p0;
+	wire [31 : 0] dfi_14_dw_wrdata_dbi_p0;
+	wire [7 : 0] dfi_14_dw_wrdata_par_p0;
+	wire [7 : 0] dfi_14_dw_wrdata_dq_en_p0;
+	wire [7 : 0] dfi_14_dw_wrdata_par_en_p0;
+	wire [1 : 0] dfi_14_aw_ck_p1;
+	wire [1 : 0] dfi_14_aw_cke_p1;
+	wire [11 : 0] dfi_14_aw_row_p1;
+	wire [15 : 0] dfi_14_aw_col_p1;
+	wire [255 : 0] dfi_14_dw_wrdata_p1;
+	wire [31 : 0] dfi_14_dw_wrdata_mask_p1;
+	wire [31 : 0] dfi_14_dw_wrdata_dbi_p1;
+	wire [7 : 0] dfi_14_dw_wrdata_par_p1;
+	wire [7 : 0] dfi_14_dw_wrdata_dq_en_p1;
+	wire [7 : 0] dfi_14_dw_wrdata_par_en_p1;
+	wire dfi_14_aw_ck_dis;
+	wire dfi_14_lp_pwr_e_req;
+	wire dfi_14_lp_sr_e_req;
+	wire dfi_14_lp_pwr_x_req;
+	wire dfi_14_aw_tx_indx_ld;
+	wire dfi_14_dw_tx_indx_ld;
+	wire dfi_14_dw_rx_indx_ld;
+	wire dfi_14_ctrlupd_ack;
+	wire dfi_14_phyupd_req;
+	
+	wire [255 : 0] w_dfi_14_dw_rddata_p0;
+	wire [31 : 0] dfi_14_dw_rddata_dm_p0;
+	wire [31 : 0] dfi_14_dw_rddata_dbi_p0;
+	wire [7 : 0] dfi_14_dw_rddata_par_p0;
+	wire [255 : 0] w_dfi_14_dw_rddata_p1;
+	wire [31 : 0] dfi_14_dw_rddata_dm_p1;
+	wire [31 : 0] dfi_14_dw_rddata_dbi_p1;
+	wire [7 : 0] dfi_14_dw_rddata_par_p1;
+	//wire [15 : 0] dfi_14_dbi_byte_disable;
+	wire [3 : 0] w_dfi_14_dw_rddata_valid;
+	//wire [7 : 0] dfi_14_dw_derr_n;
+	//wire [1 : 0] dfi_14_aw_aerr_n;
+	wire dfi_14_ctrlupd_req;
+	wire dfi_14_phyupd_ack;
+	//wire dfi_14_clk_init;
+	wire w_dfi_14_init_complete;
+	wire w_dfi_14_out_rst_n;
+	
+	
+	// CHANNEL 15
+	wire dfi_15_init_start;
+	wire [1 : 0] dfi_15_aw_ck_p0;
+	wire [1 : 0] dfi_15_aw_cke_p0;
+	wire [11 : 0] dfi_15_aw_row_p0;
+	wire [15 : 0] dfi_15_aw_col_p0;
+	wire [255 : 0] dfi_15_dw_wrdata_p0;
+	wire [31 : 0] dfi_15_dw_wrdata_mask_p0;
+	wire [31 : 0] dfi_15_dw_wrdata_dbi_p0;
+	wire [7 : 0] dfi_15_dw_wrdata_par_p0;
+	wire [7 : 0] dfi_15_dw_wrdata_dq_en_p0;
+	wire [7 : 0] dfi_15_dw_wrdata_par_en_p0;
+	wire [1 : 0] dfi_15_aw_ck_p1;
+	wire [1 : 0] dfi_15_aw_cke_p1;
+	wire [11 : 0] dfi_15_aw_row_p1;
+	wire [15 : 0] dfi_15_aw_col_p1;
+	wire [255 : 0] dfi_15_dw_wrdata_p1;
+	wire [31 : 0] dfi_15_dw_wrdata_mask_p1;
+	wire [31 : 0] dfi_15_dw_wrdata_dbi_p1;
+	wire [7 : 0] dfi_15_dw_wrdata_par_p1;
+	wire [7 : 0] dfi_15_dw_wrdata_dq_en_p1;
+	wire [7 : 0] dfi_15_dw_wrdata_par_en_p1;
+	wire dfi_15_aw_ck_dis;
+	wire dfi_15_lp_pwr_e_req;
+	wire dfi_15_lp_sr_e_req;
+	wire dfi_15_lp_pwr_x_req;
+	wire dfi_15_aw_tx_indx_ld;
+	wire dfi_15_dw_tx_indx_ld;
+	wire dfi_15_dw_rx_indx_ld;
+	wire dfi_15_ctrlupd_ack;
+	wire dfi_15_phyupd_req;
+	
+	wire [255 : 0] w_dfi_15_dw_rddata_p0;
+	wire [31 : 0] dfi_15_dw_rddata_dm_p0;
+	wire [31 : 0] dfi_15_dw_rddata_dbi_p0;
+	wire [7 : 0] dfi_15_dw_rddata_par_p0;
+	wire [255 : 0] w_dfi_15_dw_rddata_p1;
+	wire [31 : 0] dfi_15_dw_rddata_dm_p1;
+	wire [31 : 0] dfi_15_dw_rddata_dbi_p1;
+	wire [7 : 0] dfi_15_dw_rddata_par_p1;
+	//wire [15 : 0] dfi_15_dbi_byte_disable;
+	wire [3 : 0] w_dfi_15_dw_rddata_valid;
+	//wire [7 : 0] dfi_15_dw_derr_n;
+	//wire [1 : 0] dfi_15_aw_aerr_n;
+	wire dfi_15_ctrlupd_req;
+	wire dfi_15_phyupd_ack;
+	//wire dfi_15_clk_init;
+	wire w_dfi_15_init_complete;
+	wire w_dfi_15_out_rst_n;
+	
+	wire apb_complete_0;
+	wire apb_complete_1;
+	wire DRAM_0_STAT_CATTRIP;
+	wire [6 : 0] DRAM_0_STAT_TEMP;
+	wire DRAM_1_STAT_CATTRIP;
+	wire [6 : 0] DRAM_1_STAT_TEMP;
+	
+	assign hbm0_temp = DRAM_0_STAT_TEMP;
+	assign hbm1_temp = DRAM_1_STAT_TEMP;
+	
+	/*wire w_0_ready;
+	wire w_1_ready;
+	wire w_2_ready;
+	wire w_3_ready;
+	wire w_4_ready;
+	wire w_5_ready;
+	wire w_6_ready;
+	wire w_7_ready;*/
+	wire w_8_ready;
+	wire w_9_ready;
+	wire w_10_ready;
+	wire w_11_ready;
+	wire w_12_ready;
+	wire w_13_ready;
+	wire w_14_ready;
+	wire w_15_ready;
+	
+	/*wire [2*`CMD_TYPE_WIDTH-1:0]	w_0_cmd_type;
+	wire [2*`CMD_TYPE_WIDTH-1:0]	w_1_cmd_type;
+	wire [2*`CMD_TYPE_WIDTH-1:0]	w_2_cmd_type;
+	wire [2*`CMD_TYPE_WIDTH-1:0]	w_3_cmd_type;
+	wire [2*`CMD_TYPE_WIDTH-1:0]	w_4_cmd_type;
+	wire [2*`CMD_TYPE_WIDTH-1:0]	w_5_cmd_type;
+	wire [2*`CMD_TYPE_WIDTH-1:0]	w_6_cmd_type;
+	wire [2*`CMD_TYPE_WIDTH-1:0]	w_7_cmd_type;*/
+	wire [2*`CMD_TYPE_WIDTH-1:0]	w_8_cmd_type;
+	wire [2*`CMD_TYPE_WIDTH-1:0]	w_9_cmd_type;
+	wire [2*`CMD_TYPE_WIDTH-1:0]	w_10_cmd_type;
+	wire [2*`CMD_TYPE_WIDTH-1:0]	w_11_cmd_type;
+	wire [2*`CMD_TYPE_WIDTH-1:0]	w_12_cmd_type;
+	wire [2*`CMD_TYPE_WIDTH-1:0]	w_13_cmd_type;
+	wire [2*`CMD_TYPE_WIDTH-1:0]	w_14_cmd_type;
+	wire [2*`CMD_TYPE_WIDTH-1:0]	w_15_cmd_type;
+	
+	wire w_ch_dfi_init_complete;
+	wire [255 : 0] w_ch_dfi_dw_rddata_p0;
+	wire [255 : 0] w_ch_dfi_dw_rddata_p1;
+	wire [3 : 0] w_ch_dfi_dw_rddata_valid;
+	wire w_ch_dfi_out_rst_n;
+	wire w_ch_ready;
+	
+	wire	[2*`ROW_ADDR_WIDTH-1:0]	    o_row_addr;
+	wire	[2*`COL_ADDR_WIDTH-1:0]	    o_col_addr;
+	wire	[2*`BA_ADDR_WIDTH-1:0]	    o_ba_addr;
+	wire	[2*`WR_DATA_WIDTH-1:0]      o_i_wrdata;
+	wire 	[2*`PC_WIDTH-1:0]		    o_BA4; // indicates target PC
+	
+	assign dfi_0_init_complete     = w_ch_dfi_init_complete;
+	assign dfi_0_dw_rddata_p0      = w_ch_dfi_dw_rddata_p0;
+	assign dfi_0_dw_rddata_p1      = w_ch_dfi_dw_rddata_p1;
+	assign dfi_0_dw_rddata_valid   = w_ch_dfi_dw_rddata_valid;
+	assign dfi_0_out_rst_n         = w_ch_dfi_out_rst_n;
+	assign ready                   = w_ch_ready;
+	
+	channel_selector ch_sel (
+        .row_addr(row_addr),
+		.col_addr(col_addr),
+		.ba_addr(ba_addr),
+		.i_wrdata(i_wrdata),
+		.cmd_type(cmd_type),
+		.BA4(BA4), // indicates target PC
+		.channel_id(channel_id[3:0]),
+		
+		.dfi_clk(dfi_clk),
+    	.dfi_rst_n(dfi_rst_n),
+        
+        /*.dfi_0_init_complete(w_dfi_0_init_complete),
+		.dfi_0_dw_rddata_p0(w_dfi_0_dw_rddata_p0),
+		.dfi_0_dw_rddata_p1(w_dfi_0_dw_rddata_p1),
+		.dfi_0_dw_rddata_valid(w_dfi_0_dw_rddata_valid),
+		.dfi_0_out_rst_n(w_dfi_0_out_rst_n),
+	    .ready_0(w_0_ready),
+	    
+	    .dfi_1_init_complete(w_dfi_1_init_complete),
+		.dfi_1_dw_rddata_p0(w_dfi_1_dw_rddata_p0),
+		.dfi_1_dw_rddata_p1(w_dfi_1_dw_rddata_p1),
+		.dfi_1_dw_rddata_valid(w_dfi_1_dw_rddata_valid),
+		.dfi_1_out_rst_n(w_dfi_1_out_rst_n),
+	    .ready_1(w_1_ready),
+	    
+	    .dfi_2_init_complete(w_dfi_2_init_complete),
+		.dfi_2_dw_rddata_p0(w_dfi_2_dw_rddata_p0),
+		.dfi_2_dw_rddata_p1(w_dfi_2_dw_rddata_p1),
+		.dfi_2_dw_rddata_valid(w_dfi_2_dw_rddata_valid),
+		.dfi_2_out_rst_n(w_dfi_2_out_rst_n),
+	    .ready_2(w_2_ready),
+	    
+	    .dfi_3_init_complete(w_dfi_3_init_complete),
+		.dfi_3_dw_rddata_p0(w_dfi_3_dw_rddata_p0),
+		.dfi_3_dw_rddata_p1(w_dfi_3_dw_rddata_p1),
+		.dfi_3_dw_rddata_valid(w_dfi_3_dw_rddata_valid),
+		.dfi_3_out_rst_n(w_dfi_3_out_rst_n),
+	    .ready_3(w_3_ready),
+	    
+	    .dfi_4_init_complete(w_dfi_4_init_complete),
+		.dfi_4_dw_rddata_p0(w_dfi_4_dw_rddata_p0),
+		.dfi_4_dw_rddata_p1(w_dfi_4_dw_rddata_p1),
+		.dfi_4_dw_rddata_valid(w_dfi_4_dw_rddata_valid),
+		.dfi_4_out_rst_n(w_dfi_4_out_rst_n),
+	    .ready_4(w_4_ready),
+	    
+	    .dfi_5_init_complete(w_dfi_5_init_complete),
+		.dfi_5_dw_rddata_p0(w_dfi_5_dw_rddata_p0),
+		.dfi_5_dw_rddata_p1(w_dfi_5_dw_rddata_p1),
+		.dfi_5_dw_rddata_valid(w_dfi_5_dw_rddata_valid),
+		.dfi_5_out_rst_n(w_dfi_5_out_rst_n),
+	    .ready_5(w_5_ready),
+	    
+	    .dfi_6_init_complete(w_dfi_6_init_complete),
+		.dfi_6_dw_rddata_p0(w_dfi_6_dw_rddata_p0),
+		.dfi_6_dw_rddata_p1(w_dfi_6_dw_rddata_p1),
+		.dfi_6_dw_rddata_valid(w_dfi_6_dw_rddata_valid),
+		.dfi_6_out_rst_n(w_dfi_6_out_rst_n),
+	    .ready_6(w_6_ready),
+	    
+	    .dfi_7_init_complete(w_dfi_7_init_complete),
+		.dfi_7_dw_rddata_p0(w_dfi_7_dw_rddata_p0),
+		.dfi_7_dw_rddata_p1(w_dfi_7_dw_rddata_p1),
+		.dfi_7_dw_rddata_valid(w_dfi_7_dw_rddata_valid),
+		.dfi_7_out_rst_n(w_dfi_7_out_rst_n),
+	    .ready_7(w_7_ready),*/
+	    
+	    .dfi_8_init_complete(w_dfi_8_init_complete),
+		.dfi_8_dw_rddata_p0(w_dfi_8_dw_rddata_p0),
+		.dfi_8_dw_rddata_p1(w_dfi_8_dw_rddata_p1),
+		.dfi_8_dw_rddata_valid(w_dfi_8_dw_rddata_valid),
+		.dfi_8_out_rst_n(w_dfi_8_out_rst_n),
+	    .ready_8(w_8_ready),
+	    
+	    .dfi_9_init_complete(w_dfi_9_init_complete),
+		.dfi_9_dw_rddata_p0(w_dfi_9_dw_rddata_p0),
+		.dfi_9_dw_rddata_p1(w_dfi_9_dw_rddata_p1),
+		.dfi_9_dw_rddata_valid(w_dfi_9_dw_rddata_valid),
+		.dfi_9_out_rst_n(w_dfi_9_out_rst_n),
+	    .ready_9(w_9_ready),
+	    
+	    .dfi_10_init_complete(w_dfi_10_init_complete),
+		.dfi_10_dw_rddata_p0(w_dfi_10_dw_rddata_p0),
+		.dfi_10_dw_rddata_p1(w_dfi_10_dw_rddata_p1),
+		.dfi_10_dw_rddata_valid(w_dfi_10_dw_rddata_valid),
+		.dfi_10_out_rst_n(w_dfi_10_out_rst_n),
+	    .ready_10(w_10_ready),
+	    
+	    .dfi_11_init_complete(w_dfi_11_init_complete),
+		.dfi_11_dw_rddata_p0(w_dfi_11_dw_rddata_p0),
+		.dfi_11_dw_rddata_p1(w_dfi_11_dw_rddata_p1),
+		.dfi_11_dw_rddata_valid(w_dfi_11_dw_rddata_valid),
+		.dfi_11_out_rst_n(w_dfi_11_out_rst_n),
+	    .ready_11(w_11_ready),
+	    
+	    .dfi_12_init_complete(w_dfi_12_init_complete),
+		.dfi_12_dw_rddata_p0(w_dfi_12_dw_rddata_p0),
+		.dfi_12_dw_rddata_p1(w_dfi_12_dw_rddata_p1),
+		.dfi_12_dw_rddata_valid(w_dfi_12_dw_rddata_valid),
+		.dfi_12_out_rst_n(w_dfi_12_out_rst_n),
+	    .ready_12(w_12_ready),
+	    
+	    .dfi_13_init_complete(w_dfi_13_init_complete),
+		.dfi_13_dw_rddata_p0(w_dfi_13_dw_rddata_p0),
+		.dfi_13_dw_rddata_p1(w_dfi_13_dw_rddata_p1),
+		.dfi_13_dw_rddata_valid(w_dfi_13_dw_rddata_valid),
+		.dfi_13_out_rst_n(w_dfi_13_out_rst_n),
+	    .ready_13(w_13_ready),
+	    
+	    .dfi_14_init_complete(w_dfi_14_init_complete),
+		.dfi_14_dw_rddata_p0(w_dfi_14_dw_rddata_p0),
+		.dfi_14_dw_rddata_p1(w_dfi_14_dw_rddata_p1),
+		.dfi_14_dw_rddata_valid(w_dfi_14_dw_rddata_valid),
+		.dfi_14_out_rst_n(w_dfi_14_out_rst_n),
+	    .ready_14(w_14_ready),
+	    
+	    .dfi_15_init_complete(w_dfi_15_init_complete),
+		.dfi_15_dw_rddata_p0(w_dfi_15_dw_rddata_p0),
+		.dfi_15_dw_rddata_p1(w_dfi_15_dw_rddata_p1),
+		.dfi_15_dw_rddata_valid(w_dfi_15_dw_rddata_valid),
+		.dfi_15_out_rst_n(w_dfi_15_out_rst_n),
+	    .ready_15(w_15_ready),
+	    
+	    .o_ch_dfi_init_complete(w_ch_dfi_init_complete),
+		.o_ch_dfi_dw_rddata_p0(w_ch_dfi_dw_rddata_p0),
+		.o_ch_dfi_dw_rddata_p1(w_ch_dfi_dw_rddata_p1),
+		.o_ch_dfi_dw_rddata_valid(w_ch_dfi_dw_rddata_valid),
+		.o_ch_dfi_out_rst_n(w_ch_dfi_out_rst_n),
+		.o_ch_ready(w_ch_ready),
+		
+		/*.o_0_cmd_type(w_0_cmd_type),
+		.o_1_cmd_type(w_1_cmd_type),
+		.o_2_cmd_type(w_2_cmd_type),
+		.o_3_cmd_type(w_3_cmd_type),
+		.o_4_cmd_type(w_4_cmd_type),
+		.o_5_cmd_type(w_5_cmd_type),
+		.o_6_cmd_type(w_6_cmd_type),
+		.o_7_cmd_type(w_7_cmd_type),*/
+		.o_8_cmd_type(w_8_cmd_type),
+		.o_9_cmd_type(w_9_cmd_type),
+		.o_10_cmd_type(w_10_cmd_type),
+		.o_11_cmd_type(w_11_cmd_type),
+		.o_12_cmd_type(w_12_cmd_type),
+		.o_13_cmd_type(w_13_cmd_type),
+		.o_14_cmd_type(w_14_cmd_type),
+		.o_15_cmd_type(w_15_cmd_type),
+		
+		.o_row_addr(o_row_addr),
+		.o_col_addr(o_col_addr),
+		.o_ba_addr(o_ba_addr),
+		.o_i_wrdata(o_i_wrdata),
+		.o_BA4(o_BA4) // indicates target PC
+    );
+    
+    /*HBM_interface HBM_interface_CH0 (
+		.row_addr					    	   (o_row_addr),
+		.col_addr							   (o_col_addr),
+		.ba_addr							   (o_ba_addr),
+		.i_wrdata							   (o_i_wrdata),
+		.cmd_type							   (w_0_cmd_type),
+		.BA4								   (o_BA4),
+		
+		.dfi_clk							   (dfi_clk),
+		.dfi_rst_n							   (dfi_rst_n),
+		.dfi_rst_buf_n						   (w_dfi_0_out_rst_n), // this was dfi_0_out_rst_n
+		.dfi_ctrlupd_req					   (dfi_0_ctrlupd_req),
+		.dfi_phyupd_ack						   (dfi_0_phyupd_ack),
+		.dfi_init_complete					   (w_dfi_0_init_complete),
+		
+		.apb_complete_0                        (apb_complete_0),
+	  	.apb_complete_1                        (apb_complete_1),
+	  	.DRAM_0_STAT_CATTRIP                   (DRAM_0_STAT_CATTRIP),
+	  	.DRAM_0_STAT_TEMP                      (DRAM_0_STAT_TEMP   ),
+	  	.DRAM_1_STAT_CATTRIP                   (DRAM_1_STAT_CATTRIP),
+	  	.DRAM_1_STAT_TEMP                      (DRAM_1_STAT_TEMP   ),
+	  	
+		.dfi_init_start 					   (dfi_0_init_start),
+		.dfi_aw_ck_p0            			   (dfi_0_aw_ck_p0),
+		.dfi_aw_cke_p0           			   (dfi_0_aw_cke_p0),
+		.dfi_aw_row_p0                         (dfi_0_aw_row_p0),
+		.dfi_aw_col_p0                         (dfi_0_aw_col_p0),
+		.dfi_dw_wrdata_p0              	       (dfi_0_dw_wrdata_p0),
+		.dfi_dw_wrdata_mask_p0                 (dfi_0_dw_wrdata_mask_p0),
+		.dfi_dw_wrdata_dbi_p0                  (dfi_0_dw_wrdata_dbi_p0),
+		.dfi_dw_wrdata_par_p0                  (dfi_0_dw_wrdata_par_p0),
+		.dfi_dw_wrdata_dq_en_p0                (dfi_0_dw_wrdata_dq_en_p0),
+		.dfi_dw_wrdata_par_en_p0               (dfi_0_dw_wrdata_par_en_p0),
+		.dfi_aw_ck_p1            			   (dfi_0_aw_ck_p1),
+		.dfi_aw_cke_p1           			   (dfi_0_aw_cke_p1),
+		.dfi_aw_row_p1                         (dfi_0_aw_row_p1),
+		.dfi_aw_col_p1                         (dfi_0_aw_col_p1),
+		.dfi_dw_wrdata_p1              	       (dfi_0_dw_wrdata_p1),
+		.dfi_dw_wrdata_mask_p1                 (dfi_0_dw_wrdata_mask_p1),
+		.dfi_dw_wrdata_dbi_p1                  (dfi_0_dw_wrdata_dbi_p1),
+		.dfi_dw_wrdata_par_p1                  (dfi_0_dw_wrdata_par_p1),
+		.dfi_dw_wrdata_dq_en_p1                (dfi_0_dw_wrdata_dq_en_p1),
+		.dfi_dw_wrdata_par_en_p1               (dfi_0_dw_wrdata_par_en_p1),
+		.dfi_aw_ck_dis                         (dfi_0_aw_ck_dis),
+		.dfi_lp_pwr_e_req                      (dfi_0_lp_pwr_e_req),
+		.dfi_lp_sr_e_req                       (dfi_0_lp_sr_e_req),
+		.dfi_lp_pwr_x_e_req                    (dfi_0_lp_pwr_x_e_req),
+		.dfi_aw_tx_indx_ld                     (dfi_0_aw_tx_indx_ld),
+		.dfi_dw_tx_indx_ld                     (dfi_0_dw_tx_indx_ld),
+		.dfi_dw_rx_indx_ld                     (dfi_0_dw_rx_indx_ld),
+		.dfi_ctrlupd_ack                       (dfi_0_ctrlupd_ack),
+    	.dfi_phyupd_req                        (dfi_0_phyupd_req),
+    	.ready                                 (w_0_ready)
+    );
+    
+    
+    HBM_interface HBM_interface_CH1 (
+		.row_addr					    	   (o_row_addr),
+		.col_addr							   (o_col_addr),
+		.ba_addr							   (o_ba_addr),
+		.i_wrdata							   (o_i_wrdata),
+		.cmd_type							   (w_1_cmd_type),
+		.BA4								   (o_BA4),
+		
+		.dfi_clk							   (dfi_clk),
+		.dfi_rst_n							   (dfi_rst_n),
+		.dfi_rst_buf_n						   (w_dfi_1_out_rst_n), // this was dfi_1_out_rst_n
+		.dfi_ctrlupd_req					   (dfi_1_ctrlupd_req),
+		.dfi_phyupd_ack						   (dfi_1_phyupd_ack),
+		.dfi_init_complete					   (w_dfi_1_init_complete),
+		
+		.apb_complete_0                        (apb_complete_0),
+	  	.apb_complete_1                        (apb_complete_1),
+	  	.DRAM_0_STAT_CATTRIP                   (DRAM_0_STAT_CATTRIP),
+	  	.DRAM_0_STAT_TEMP                      (DRAM_0_STAT_TEMP   ),
+	  	.DRAM_1_STAT_CATTRIP                   (DRAM_1_STAT_CATTRIP),
+	  	.DRAM_1_STAT_TEMP                      (DRAM_1_STAT_TEMP   ),
+	  	
+		.dfi_init_start 					   (dfi_1_init_start),
+		.dfi_aw_ck_p0            			   (dfi_1_aw_ck_p0),
+		.dfi_aw_cke_p0           			   (dfi_1_aw_cke_p0),
+		.dfi_aw_row_p0                         (dfi_1_aw_row_p0),
+		.dfi_aw_col_p0                         (dfi_1_aw_col_p0),
+		.dfi_dw_wrdata_p0              	       (dfi_1_dw_wrdata_p0),
+		.dfi_dw_wrdata_mask_p0                 (dfi_1_dw_wrdata_mask_p0),
+		.dfi_dw_wrdata_dbi_p0                  (dfi_1_dw_wrdata_dbi_p0),
+		.dfi_dw_wrdata_par_p0                  (dfi_1_dw_wrdata_par_p0),
+		.dfi_dw_wrdata_dq_en_p0                (dfi_1_dw_wrdata_dq_en_p0),
+		.dfi_dw_wrdata_par_en_p0               (dfi_1_dw_wrdata_par_en_p0),
+		.dfi_aw_ck_p1            			   (dfi_1_aw_ck_p1),
+		.dfi_aw_cke_p1           			   (dfi_1_aw_cke_p1),
+		.dfi_aw_row_p1                         (dfi_1_aw_row_p1),
+		.dfi_aw_col_p1                         (dfi_1_aw_col_p1),
+		.dfi_dw_wrdata_p1              	       (dfi_1_dw_wrdata_p1),
+		.dfi_dw_wrdata_mask_p1                 (dfi_1_dw_wrdata_mask_p1),
+		.dfi_dw_wrdata_dbi_p1                  (dfi_1_dw_wrdata_dbi_p1),
+		.dfi_dw_wrdata_par_p1                  (dfi_1_dw_wrdata_par_p1),
+		.dfi_dw_wrdata_dq_en_p1                (dfi_1_dw_wrdata_dq_en_p1),
+		.dfi_dw_wrdata_par_en_p1               (dfi_1_dw_wrdata_par_en_p1),
+		.dfi_aw_ck_dis                         (dfi_1_aw_ck_dis),
+		.dfi_lp_pwr_e_req                      (dfi_1_lp_pwr_e_req),
+		.dfi_lp_sr_e_req                       (dfi_1_lp_sr_e_req),
+		.dfi_lp_pwr_x_e_req                    (dfi_1_lp_pwr_x_e_req),
+		.dfi_aw_tx_indx_ld                     (dfi_1_aw_tx_indx_ld),
+		.dfi_dw_tx_indx_ld                     (dfi_1_dw_tx_indx_ld),
+		.dfi_dw_rx_indx_ld                     (dfi_1_dw_rx_indx_ld),
+		.dfi_ctrlupd_ack                       (dfi_1_ctrlupd_ack),
+    	.dfi_phyupd_req                        (dfi_1_phyupd_req),
+    	.ready                                 (w_1_ready)
+    );
+    
+    HBM_interface HBM_interface_CH2 (
+		.row_addr					    	   (o_row_addr),
+		.col_addr							   (o_col_addr),
+		.ba_addr							   (o_ba_addr),
+		.i_wrdata							   (o_i_wrdata),
+		.cmd_type							   (w_2_cmd_type),
+		.BA4								   (o_BA4),
+		
+		.dfi_clk							   (dfi_clk),
+		.dfi_rst_n							   (dfi_rst_n),
+		.dfi_rst_buf_n						   (w_dfi_2_out_rst_n), // this was dfi_2_out_rst_n
+		.dfi_ctrlupd_req					   (dfi_2_ctrlupd_req),
+		.dfi_phyupd_ack						   (dfi_2_phyupd_ack),
+		.dfi_init_complete					   (w_dfi_2_init_complete),
+		
+		.apb_complete_0                        (apb_complete_0),
+	  	.apb_complete_1                        (apb_complete_1),
+	  	.DRAM_0_STAT_CATTRIP                   (DRAM_0_STAT_CATTRIP),
+	  	.DRAM_0_STAT_TEMP                      (DRAM_0_STAT_TEMP   ),
+	  	.DRAM_1_STAT_CATTRIP                   (DRAM_1_STAT_CATTRIP),
+	  	.DRAM_1_STAT_TEMP                      (DRAM_1_STAT_TEMP   ),
+	  	
+		.dfi_init_start 					   (dfi_2_init_start),
+		.dfi_aw_ck_p0            			   (dfi_2_aw_ck_p0),
+		.dfi_aw_cke_p0           			   (dfi_2_aw_cke_p0),
+		.dfi_aw_row_p0                         (dfi_2_aw_row_p0),
+		.dfi_aw_col_p0                         (dfi_2_aw_col_p0),
+		.dfi_dw_wrdata_p0              	       (dfi_2_dw_wrdata_p0),
+		.dfi_dw_wrdata_mask_p0                 (dfi_2_dw_wrdata_mask_p0),
+		.dfi_dw_wrdata_dbi_p0                  (dfi_2_dw_wrdata_dbi_p0),
+		.dfi_dw_wrdata_par_p0                  (dfi_2_dw_wrdata_par_p0),
+		.dfi_dw_wrdata_dq_en_p0                (dfi_2_dw_wrdata_dq_en_p0),
+		.dfi_dw_wrdata_par_en_p0               (dfi_2_dw_wrdata_par_en_p0),
+		.dfi_aw_ck_p1            			   (dfi_2_aw_ck_p1),
+		.dfi_aw_cke_p1           			   (dfi_2_aw_cke_p1),
+		.dfi_aw_row_p1                         (dfi_2_aw_row_p1),
+		.dfi_aw_col_p1                         (dfi_2_aw_col_p1),
+		.dfi_dw_wrdata_p1              	       (dfi_2_dw_wrdata_p1),
+		.dfi_dw_wrdata_mask_p1                 (dfi_2_dw_wrdata_mask_p1),
+		.dfi_dw_wrdata_dbi_p1                  (dfi_2_dw_wrdata_dbi_p1),
+		.dfi_dw_wrdata_par_p1                  (dfi_2_dw_wrdata_par_p1),
+		.dfi_dw_wrdata_dq_en_p1                (dfi_2_dw_wrdata_dq_en_p1),
+		.dfi_dw_wrdata_par_en_p1               (dfi_2_dw_wrdata_par_en_p1),
+		.dfi_aw_ck_dis                         (dfi_2_aw_ck_dis),
+		.dfi_lp_pwr_e_req                      (dfi_2_lp_pwr_e_req),
+		.dfi_lp_sr_e_req                       (dfi_2_lp_sr_e_req),
+		.dfi_lp_pwr_x_e_req                    (dfi_2_lp_pwr_x_e_req),
+		.dfi_aw_tx_indx_ld                     (dfi_2_aw_tx_indx_ld),
+		.dfi_dw_tx_indx_ld                     (dfi_2_dw_tx_indx_ld),
+		.dfi_dw_rx_indx_ld                     (dfi_2_dw_rx_indx_ld),
+		.dfi_ctrlupd_ack                       (dfi_2_ctrlupd_ack),
+    	.dfi_phyupd_req                        (dfi_2_phyupd_req),
+    	.ready                                 (w_2_ready)
+    );
+    
+    HBM_interface HBM_interface_CH3 (
+		.row_addr					    	   (o_row_addr),
+		.col_addr							   (o_col_addr),
+		.ba_addr							   (o_ba_addr),
+		.i_wrdata							   (o_i_wrdata),
+		.cmd_type							   (w_3_cmd_type),
+		.BA4								   (o_BA4),
+		
+		.dfi_clk							   (dfi_clk),
+		.dfi_rst_n							   (dfi_rst_n),
+		.dfi_rst_buf_n						   (w_dfi_3_out_rst_n), // this was dfi_3_out_rst_n
+		.dfi_ctrlupd_req					   (dfi_3_ctrlupd_req),
+		.dfi_phyupd_ack						   (dfi_3_phyupd_ack),
+		.dfi_init_complete					   (w_dfi_3_init_complete),
+		
+		.apb_complete_0                        (apb_complete_0),
+	  	.apb_complete_1                        (apb_complete_1),
+	  	.DRAM_0_STAT_CATTRIP                   (DRAM_0_STAT_CATTRIP),
+	  	.DRAM_0_STAT_TEMP                      (DRAM_0_STAT_TEMP   ),
+	  	.DRAM_1_STAT_CATTRIP                   (DRAM_1_STAT_CATTRIP),
+	  	.DRAM_1_STAT_TEMP                      (DRAM_1_STAT_TEMP   ),
+	  	
+		.dfi_init_start 					   (dfi_3_init_start),
+		.dfi_aw_ck_p0            			   (dfi_3_aw_ck_p0),
+		.dfi_aw_cke_p0           			   (dfi_3_aw_cke_p0),
+		.dfi_aw_row_p0                         (dfi_3_aw_row_p0),
+		.dfi_aw_col_p0                         (dfi_3_aw_col_p0),
+		.dfi_dw_wrdata_p0              	       (dfi_3_dw_wrdata_p0),
+		.dfi_dw_wrdata_mask_p0                 (dfi_3_dw_wrdata_mask_p0),
+		.dfi_dw_wrdata_dbi_p0                  (dfi_3_dw_wrdata_dbi_p0),
+		.dfi_dw_wrdata_par_p0                  (dfi_3_dw_wrdata_par_p0),
+		.dfi_dw_wrdata_dq_en_p0                (dfi_3_dw_wrdata_dq_en_p0),
+		.dfi_dw_wrdata_par_en_p0               (dfi_3_dw_wrdata_par_en_p0),
+		.dfi_aw_ck_p1            			   (dfi_3_aw_ck_p1),
+		.dfi_aw_cke_p1           			   (dfi_3_aw_cke_p1),
+		.dfi_aw_row_p1                         (dfi_3_aw_row_p1),
+		.dfi_aw_col_p1                         (dfi_3_aw_col_p1),
+		.dfi_dw_wrdata_p1              	       (dfi_3_dw_wrdata_p1),
+		.dfi_dw_wrdata_mask_p1                 (dfi_3_dw_wrdata_mask_p1),
+		.dfi_dw_wrdata_dbi_p1                  (dfi_3_dw_wrdata_dbi_p1),
+		.dfi_dw_wrdata_par_p1                  (dfi_3_dw_wrdata_par_p1),
+		.dfi_dw_wrdata_dq_en_p1                (dfi_3_dw_wrdata_dq_en_p1),
+		.dfi_dw_wrdata_par_en_p1               (dfi_3_dw_wrdata_par_en_p1),
+		.dfi_aw_ck_dis                         (dfi_3_aw_ck_dis),
+		.dfi_lp_pwr_e_req                      (dfi_3_lp_pwr_e_req),
+		.dfi_lp_sr_e_req                       (dfi_3_lp_sr_e_req),
+		.dfi_lp_pwr_x_e_req                    (dfi_3_lp_pwr_x_e_req),
+		.dfi_aw_tx_indx_ld                     (dfi_3_aw_tx_indx_ld),
+		.dfi_dw_tx_indx_ld                     (dfi_3_dw_tx_indx_ld),
+		.dfi_dw_rx_indx_ld                     (dfi_3_dw_rx_indx_ld),
+		.dfi_ctrlupd_ack                       (dfi_3_ctrlupd_ack),
+    	.dfi_phyupd_req                        (dfi_3_phyupd_req),
+    	.ready                                 (w_3_ready)
+    );
+    
+    HBM_interface HBM_interface_CH4 (
+		.row_addr					    	   (o_row_addr),
+		.col_addr							   (o_col_addr),
+		.ba_addr							   (o_ba_addr),
+		.i_wrdata							   (o_i_wrdata),
+		.cmd_type							   (w_4_cmd_type),
+		.BA4								   (o_BA4),
+		
+		.dfi_clk							   (dfi_clk),
+		.dfi_rst_n							   (dfi_rst_n),
+		.dfi_rst_buf_n						   (w_dfi_4_out_rst_n), // this was dfi_4_out_rst_n
+		.dfi_ctrlupd_req					   (dfi_4_ctrlupd_req),
+		.dfi_phyupd_ack						   (dfi_4_phyupd_ack),
+		.dfi_init_complete					   (w_dfi_4_init_complete),
+		
+		.apb_complete_0                        (apb_complete_0),
+	  	.apb_complete_1                        (apb_complete_1),
+	  	.DRAM_0_STAT_CATTRIP                   (DRAM_0_STAT_CATTRIP),
+	  	.DRAM_0_STAT_TEMP                      (DRAM_0_STAT_TEMP   ),
+	  	.DRAM_1_STAT_CATTRIP                   (DRAM_1_STAT_CATTRIP),
+	  	.DRAM_1_STAT_TEMP                      (DRAM_1_STAT_TEMP   ),
+	  	
+		.dfi_init_start 					   (dfi_4_init_start),
+		.dfi_aw_ck_p0            			   (dfi_4_aw_ck_p0),
+		.dfi_aw_cke_p0           			   (dfi_4_aw_cke_p0),
+		.dfi_aw_row_p0                         (dfi_4_aw_row_p0),
+		.dfi_aw_col_p0                         (dfi_4_aw_col_p0),
+		.dfi_dw_wrdata_p0              	       (dfi_4_dw_wrdata_p0),
+		.dfi_dw_wrdata_mask_p0                 (dfi_4_dw_wrdata_mask_p0),
+		.dfi_dw_wrdata_dbi_p0                  (dfi_4_dw_wrdata_dbi_p0),
+		.dfi_dw_wrdata_par_p0                  (dfi_4_dw_wrdata_par_p0),
+		.dfi_dw_wrdata_dq_en_p0                (dfi_4_dw_wrdata_dq_en_p0),
+		.dfi_dw_wrdata_par_en_p0               (dfi_4_dw_wrdata_par_en_p0),
+		.dfi_aw_ck_p1            			   (dfi_4_aw_ck_p1),
+		.dfi_aw_cke_p1           			   (dfi_4_aw_cke_p1),
+		.dfi_aw_row_p1                         (dfi_4_aw_row_p1),
+		.dfi_aw_col_p1                         (dfi_4_aw_col_p1),
+		.dfi_dw_wrdata_p1              	       (dfi_4_dw_wrdata_p1),
+		.dfi_dw_wrdata_mask_p1                 (dfi_4_dw_wrdata_mask_p1),
+		.dfi_dw_wrdata_dbi_p1                  (dfi_4_dw_wrdata_dbi_p1),
+		.dfi_dw_wrdata_par_p1                  (dfi_4_dw_wrdata_par_p1),
+		.dfi_dw_wrdata_dq_en_p1                (dfi_4_dw_wrdata_dq_en_p1),
+		.dfi_dw_wrdata_par_en_p1               (dfi_4_dw_wrdata_par_en_p1),
+		.dfi_aw_ck_dis                         (dfi_4_aw_ck_dis),
+		.dfi_lp_pwr_e_req                      (dfi_4_lp_pwr_e_req),
+		.dfi_lp_sr_e_req                       (dfi_4_lp_sr_e_req),
+		.dfi_lp_pwr_x_e_req                    (dfi_4_lp_pwr_x_e_req),
+		.dfi_aw_tx_indx_ld                     (dfi_4_aw_tx_indx_ld),
+		.dfi_dw_tx_indx_ld                     (dfi_4_dw_tx_indx_ld),
+		.dfi_dw_rx_indx_ld                     (dfi_4_dw_rx_indx_ld),
+		.dfi_ctrlupd_ack                       (dfi_4_ctrlupd_ack),
+    	.dfi_phyupd_req                        (dfi_4_phyupd_req),
+    	.ready                                 (w_4_ready)
+    );
+    
+    HBM_interface HBM_interface_CH5 (
+		.row_addr					    	   (o_row_addr),
+		.col_addr							   (o_col_addr),
+		.ba_addr							   (o_ba_addr),
+		.i_wrdata							   (o_i_wrdata),
+		.cmd_type							   (w_5_cmd_type),
+		.BA4								   (o_BA4),
+		
+		.dfi_clk							   (dfi_clk),
+		.dfi_rst_n							   (dfi_rst_n),
+		.dfi_rst_buf_n						   (w_dfi_5_out_rst_n), // this was dfi_5_out_rst_n
+		.dfi_ctrlupd_req					   (dfi_5_ctrlupd_req),
+		.dfi_phyupd_ack						   (dfi_5_phyupd_ack),
+		.dfi_init_complete					   (w_dfi_5_init_complete),
+		
+		.apb_complete_0                        (apb_complete_0),
+	  	.apb_complete_1                        (apb_complete_1),
+	  	.DRAM_0_STAT_CATTRIP                   (DRAM_0_STAT_CATTRIP),
+	  	.DRAM_0_STAT_TEMP                      (DRAM_0_STAT_TEMP   ),
+	  	.DRAM_1_STAT_CATTRIP                   (DRAM_1_STAT_CATTRIP),
+	  	.DRAM_1_STAT_TEMP                      (DRAM_1_STAT_TEMP   ),
+	  	
+		.dfi_init_start 					   (dfi_5_init_start),
+		.dfi_aw_ck_p0            			   (dfi_5_aw_ck_p0),
+		.dfi_aw_cke_p0           			   (dfi_5_aw_cke_p0),
+		.dfi_aw_row_p0                         (dfi_5_aw_row_p0),
+		.dfi_aw_col_p0                         (dfi_5_aw_col_p0),
+		.dfi_dw_wrdata_p0              	       (dfi_5_dw_wrdata_p0),
+		.dfi_dw_wrdata_mask_p0                 (dfi_5_dw_wrdata_mask_p0),
+		.dfi_dw_wrdata_dbi_p0                  (dfi_5_dw_wrdata_dbi_p0),
+		.dfi_dw_wrdata_par_p0                  (dfi_5_dw_wrdata_par_p0),
+		.dfi_dw_wrdata_dq_en_p0                (dfi_5_dw_wrdata_dq_en_p0),
+		.dfi_dw_wrdata_par_en_p0               (dfi_5_dw_wrdata_par_en_p0),
+		.dfi_aw_ck_p1            			   (dfi_5_aw_ck_p1),
+		.dfi_aw_cke_p1           			   (dfi_5_aw_cke_p1),
+		.dfi_aw_row_p1                         (dfi_5_aw_row_p1),
+		.dfi_aw_col_p1                         (dfi_5_aw_col_p1),
+		.dfi_dw_wrdata_p1              	       (dfi_5_dw_wrdata_p1),
+		.dfi_dw_wrdata_mask_p1                 (dfi_5_dw_wrdata_mask_p1),
+		.dfi_dw_wrdata_dbi_p1                  (dfi_5_dw_wrdata_dbi_p1),
+		.dfi_dw_wrdata_par_p1                  (dfi_5_dw_wrdata_par_p1),
+		.dfi_dw_wrdata_dq_en_p1                (dfi_5_dw_wrdata_dq_en_p1),
+		.dfi_dw_wrdata_par_en_p1               (dfi_5_dw_wrdata_par_en_p1),
+		.dfi_aw_ck_dis                         (dfi_5_aw_ck_dis),
+		.dfi_lp_pwr_e_req                      (dfi_5_lp_pwr_e_req),
+		.dfi_lp_sr_e_req                       (dfi_5_lp_sr_e_req),
+		.dfi_lp_pwr_x_e_req                    (dfi_5_lp_pwr_x_e_req),
+		.dfi_aw_tx_indx_ld                     (dfi_5_aw_tx_indx_ld),
+		.dfi_dw_tx_indx_ld                     (dfi_5_dw_tx_indx_ld),
+		.dfi_dw_rx_indx_ld                     (dfi_5_dw_rx_indx_ld),
+		.dfi_ctrlupd_ack                       (dfi_5_ctrlupd_ack),
+    	.dfi_phyupd_req                        (dfi_5_phyupd_req),
+    	.ready                                 (w_5_ready)
+    );
+    
+    HBM_interface HBM_interface_CH6 (
+		.row_addr					    	   (o_row_addr),
+		.col_addr							   (o_col_addr),
+		.ba_addr							   (o_ba_addr),
+		.i_wrdata							   (o_i_wrdata),
+		.cmd_type							   (w_6_cmd_type),
+		.BA4								   (o_BA4),
+		
+		.dfi_clk							   (dfi_clk),
+		.dfi_rst_n							   (dfi_rst_n),
+		.dfi_rst_buf_n						   (w_dfi_6_out_rst_n), // this was dfi_6_out_rst_n
+		.dfi_ctrlupd_req					   (dfi_6_ctrlupd_req),
+		.dfi_phyupd_ack						   (dfi_6_phyupd_ack),
+		.dfi_init_complete					   (w_dfi_6_init_complete),
+		
+		.apb_complete_0                        (apb_complete_0),
+	  	.apb_complete_1                        (apb_complete_1),
+	  	.DRAM_0_STAT_CATTRIP                   (DRAM_0_STAT_CATTRIP),
+	  	.DRAM_0_STAT_TEMP                      (DRAM_0_STAT_TEMP   ),
+	  	.DRAM_1_STAT_CATTRIP                   (DRAM_1_STAT_CATTRIP),
+	  	.DRAM_1_STAT_TEMP                      (DRAM_1_STAT_TEMP   ),
+	  	
+		.dfi_init_start 					   (dfi_6_init_start),
+		.dfi_aw_ck_p0            			   (dfi_6_aw_ck_p0),
+		.dfi_aw_cke_p0           			   (dfi_6_aw_cke_p0),
+		.dfi_aw_row_p0                         (dfi_6_aw_row_p0),
+		.dfi_aw_col_p0                         (dfi_6_aw_col_p0),
+		.dfi_dw_wrdata_p0              	       (dfi_6_dw_wrdata_p0),
+		.dfi_dw_wrdata_mask_p0                 (dfi_6_dw_wrdata_mask_p0),
+		.dfi_dw_wrdata_dbi_p0                  (dfi_6_dw_wrdata_dbi_p0),
+		.dfi_dw_wrdata_par_p0                  (dfi_6_dw_wrdata_par_p0),
+		.dfi_dw_wrdata_dq_en_p0                (dfi_6_dw_wrdata_dq_en_p0),
+		.dfi_dw_wrdata_par_en_p0               (dfi_6_dw_wrdata_par_en_p0),
+		.dfi_aw_ck_p1            			   (dfi_6_aw_ck_p1),
+		.dfi_aw_cke_p1           			   (dfi_6_aw_cke_p1),
+		.dfi_aw_row_p1                         (dfi_6_aw_row_p1),
+		.dfi_aw_col_p1                         (dfi_6_aw_col_p1),
+		.dfi_dw_wrdata_p1              	       (dfi_6_dw_wrdata_p1),
+		.dfi_dw_wrdata_mask_p1                 (dfi_6_dw_wrdata_mask_p1),
+		.dfi_dw_wrdata_dbi_p1                  (dfi_6_dw_wrdata_dbi_p1),
+		.dfi_dw_wrdata_par_p1                  (dfi_6_dw_wrdata_par_p1),
+		.dfi_dw_wrdata_dq_en_p1                (dfi_6_dw_wrdata_dq_en_p1),
+		.dfi_dw_wrdata_par_en_p1               (dfi_6_dw_wrdata_par_en_p1),
+		.dfi_aw_ck_dis                         (dfi_6_aw_ck_dis),
+		.dfi_lp_pwr_e_req                      (dfi_6_lp_pwr_e_req),
+		.dfi_lp_sr_e_req                       (dfi_6_lp_sr_e_req),
+		.dfi_lp_pwr_x_e_req                    (dfi_6_lp_pwr_x_e_req),
+		.dfi_aw_tx_indx_ld                     (dfi_6_aw_tx_indx_ld),
+		.dfi_dw_tx_indx_ld                     (dfi_6_dw_tx_indx_ld),
+		.dfi_dw_rx_indx_ld                     (dfi_6_dw_rx_indx_ld),
+		.dfi_ctrlupd_ack                       (dfi_6_ctrlupd_ack),
+    	.dfi_phyupd_req                        (dfi_6_phyupd_req),
+    	.ready                                 (w_6_ready)
+    );
+    
+    HBM_interface HBM_interface_CH7 (
+		.row_addr					    	   (o_row_addr),
+		.col_addr							   (o_col_addr),
+		.ba_addr							   (o_ba_addr),
+		.i_wrdata							   (o_i_wrdata),
+		.cmd_type							   (w_7_cmd_type),
+		.BA4								   (o_BA4),
+		
+		.dfi_clk							   (dfi_clk),
+		.dfi_rst_n							   (dfi_rst_n),
+		.dfi_rst_buf_n						   (w_dfi_7_out_rst_n), // this was dfi_7_out_rst_n
+		.dfi_ctrlupd_req					   (dfi_7_ctrlupd_req),
+		.dfi_phyupd_ack						   (dfi_7_phyupd_ack),
+		.dfi_init_complete					   (w_dfi_7_init_complete),
+		
+		.apb_complete_0                        (apb_complete_0),
+	  	.apb_complete_1                        (apb_complete_1),
+	  	.DRAM_0_STAT_CATTRIP                   (DRAM_0_STAT_CATTRIP),
+	  	.DRAM_0_STAT_TEMP                      (DRAM_0_STAT_TEMP   ),
+	  	.DRAM_1_STAT_CATTRIP                   (DRAM_1_STAT_CATTRIP),
+	  	.DRAM_1_STAT_TEMP                      (DRAM_1_STAT_TEMP   ),
+	  	
+		.dfi_init_start 					   (dfi_7_init_start),
+		.dfi_aw_ck_p0            			   (dfi_7_aw_ck_p0),
+		.dfi_aw_cke_p0           			   (dfi_7_aw_cke_p0),
+		.dfi_aw_row_p0                         (dfi_7_aw_row_p0),
+		.dfi_aw_col_p0                         (dfi_7_aw_col_p0),
+		.dfi_dw_wrdata_p0              	       (dfi_7_dw_wrdata_p0),
+		.dfi_dw_wrdata_mask_p0                 (dfi_7_dw_wrdata_mask_p0),
+		.dfi_dw_wrdata_dbi_p0                  (dfi_7_dw_wrdata_dbi_p0),
+		.dfi_dw_wrdata_par_p0                  (dfi_7_dw_wrdata_par_p0),
+		.dfi_dw_wrdata_dq_en_p0                (dfi_7_dw_wrdata_dq_en_p0),
+		.dfi_dw_wrdata_par_en_p0               (dfi_7_dw_wrdata_par_en_p0),
+		.dfi_aw_ck_p1            			   (dfi_7_aw_ck_p1),
+		.dfi_aw_cke_p1           			   (dfi_7_aw_cke_p1),
+		.dfi_aw_row_p1                         (dfi_7_aw_row_p1),
+		.dfi_aw_col_p1                         (dfi_7_aw_col_p1),
+		.dfi_dw_wrdata_p1              	       (dfi_7_dw_wrdata_p1),
+		.dfi_dw_wrdata_mask_p1                 (dfi_7_dw_wrdata_mask_p1),
+		.dfi_dw_wrdata_dbi_p1                  (dfi_7_dw_wrdata_dbi_p1),
+		.dfi_dw_wrdata_par_p1                  (dfi_7_dw_wrdata_par_p1),
+		.dfi_dw_wrdata_dq_en_p1                (dfi_7_dw_wrdata_dq_en_p1),
+		.dfi_dw_wrdata_par_en_p1               (dfi_7_dw_wrdata_par_en_p1),
+		.dfi_aw_ck_dis                         (dfi_7_aw_ck_dis),
+		.dfi_lp_pwr_e_req                      (dfi_7_lp_pwr_e_req),
+		.dfi_lp_sr_e_req                       (dfi_7_lp_sr_e_req),
+		.dfi_lp_pwr_x_e_req                    (dfi_7_lp_pwr_x_e_req),
+		.dfi_aw_tx_indx_ld                     (dfi_7_aw_tx_indx_ld),
+		.dfi_dw_tx_indx_ld                     (dfi_7_dw_tx_indx_ld),
+		.dfi_dw_rx_indx_ld                     (dfi_7_dw_rx_indx_ld),
+		.dfi_ctrlupd_ack                       (dfi_7_ctrlupd_ack),
+    	.dfi_phyupd_req                        (dfi_7_phyupd_req),
+    	.ready                                 (w_7_ready)
+    );*/
+    
+    HBM_interface HBM_interface_CH8 (
+		.row_addr					    	   (o_row_addr),
+		.col_addr							   (o_col_addr),
+		.ba_addr							   (o_ba_addr),
+		.i_wrdata							   (o_i_wrdata),
+		.cmd_type							   (w_8_cmd_type),
+		.BA4								   (o_BA4),
+		
+		.dfi_clk							   (dfi_clk),
+		.dfi_rst_n							   (dfi_rst_n),
+		.dfi_rst_buf_n						   (w_dfi_8_out_rst_n), // this was dfi_8_out_rst_n
+		.dfi_ctrlupd_req					   (dfi_8_ctrlupd_req),
+		.dfi_phyupd_ack						   (dfi_8_phyupd_ack),
+		.dfi_init_complete					   (w_dfi_8_init_complete),
+		
+		.apb_complete_0                        (apb_complete_0),
+	  	.apb_complete_1                        (apb_complete_1),
+	  	.DRAM_0_STAT_CATTRIP                   (DRAM_0_STAT_CATTRIP),
+	  	.DRAM_0_STAT_TEMP                      (DRAM_0_STAT_TEMP   ),
+	  	.DRAM_1_STAT_CATTRIP                   (DRAM_1_STAT_CATTRIP),
+	  	.DRAM_1_STAT_TEMP                      (DRAM_1_STAT_TEMP   ),
+	  	
+		.dfi_init_start 					   (dfi_8_init_start),
+		.dfi_aw_ck_p0            			   (dfi_8_aw_ck_p0),
+		.dfi_aw_cke_p0           			   (dfi_8_aw_cke_p0),
+		.dfi_aw_row_p0                         (dfi_8_aw_row_p0),
+		.dfi_aw_col_p0                         (dfi_8_aw_col_p0),
+		.dfi_dw_wrdata_p0              	       (dfi_8_dw_wrdata_p0),
+		.dfi_dw_wrdata_mask_p0                 (dfi_8_dw_wrdata_mask_p0),
+		.dfi_dw_wrdata_dbi_p0                  (dfi_8_dw_wrdata_dbi_p0),
+		.dfi_dw_wrdata_par_p0                  (dfi_8_dw_wrdata_par_p0),
+		.dfi_dw_wrdata_dq_en_p0                (dfi_8_dw_wrdata_dq_en_p0),
+		.dfi_dw_wrdata_par_en_p0               (dfi_8_dw_wrdata_par_en_p0),
+		.dfi_aw_ck_p1            			   (dfi_8_aw_ck_p1),
+		.dfi_aw_cke_p1           			   (dfi_8_aw_cke_p1),
+		.dfi_aw_row_p1                         (dfi_8_aw_row_p1),
+		.dfi_aw_col_p1                         (dfi_8_aw_col_p1),
+		.dfi_dw_wrdata_p1              	       (dfi_8_dw_wrdata_p1),
+		.dfi_dw_wrdata_mask_p1                 (dfi_8_dw_wrdata_mask_p1),
+		.dfi_dw_wrdata_dbi_p1                  (dfi_8_dw_wrdata_dbi_p1),
+		.dfi_dw_wrdata_par_p1                  (dfi_8_dw_wrdata_par_p1),
+		.dfi_dw_wrdata_dq_en_p1                (dfi_8_dw_wrdata_dq_en_p1),
+		.dfi_dw_wrdata_par_en_p1               (dfi_8_dw_wrdata_par_en_p1),
+		.dfi_aw_ck_dis                         (dfi_8_aw_ck_dis),
+		.dfi_lp_pwr_e_req                      (dfi_8_lp_pwr_e_req),
+		.dfi_lp_sr_e_req                       (dfi_8_lp_sr_e_req),
+		.dfi_lp_pwr_x_e_req                    (dfi_8_lp_pwr_x_e_req),
+		.dfi_aw_tx_indx_ld                     (dfi_8_aw_tx_indx_ld),
+		.dfi_dw_tx_indx_ld                     (dfi_8_dw_tx_indx_ld),
+		.dfi_dw_rx_indx_ld                     (dfi_8_dw_rx_indx_ld),
+		.dfi_ctrlupd_ack                       (dfi_8_ctrlupd_ack),
+    	.dfi_phyupd_req                        (dfi_8_phyupd_req),
+    	.ready                                 (w_8_ready)
+    );
+    
+    HBM_interface HBM_interface_CH9 (
+		.row_addr					    	   (o_row_addr),
+		.col_addr							   (o_col_addr),
+		.ba_addr							   (o_ba_addr),
+		.i_wrdata							   (o_i_wrdata),
+		.cmd_type							   (w_9_cmd_type),
+		.BA4								   (o_BA4),
+		
+		.dfi_clk							   (dfi_clk),
+		.dfi_rst_n							   (dfi_rst_n),
+		.dfi_rst_buf_n						   (w_dfi_9_out_rst_n), // this was dfi_9_out_rst_n
+		.dfi_ctrlupd_req					   (dfi_9_ctrlupd_req),
+		.dfi_phyupd_ack						   (dfi_9_phyupd_ack),
+		.dfi_init_complete					   (w_dfi_9_init_complete),
+		
+		.apb_complete_0                        (apb_complete_0),
+	  	.apb_complete_1                        (apb_complete_1),
+	  	.DRAM_0_STAT_CATTRIP                   (DRAM_0_STAT_CATTRIP),
+	  	.DRAM_0_STAT_TEMP                      (DRAM_0_STAT_TEMP   ),
+	  	.DRAM_1_STAT_CATTRIP                   (DRAM_1_STAT_CATTRIP),
+	  	.DRAM_1_STAT_TEMP                      (DRAM_1_STAT_TEMP   ),
+	  	
+		.dfi_init_start 					   (dfi_9_init_start),
+		.dfi_aw_ck_p0            			   (dfi_9_aw_ck_p0),
+		.dfi_aw_cke_p0           			   (dfi_9_aw_cke_p0),
+		.dfi_aw_row_p0                         (dfi_9_aw_row_p0),
+		.dfi_aw_col_p0                         (dfi_9_aw_col_p0),
+		.dfi_dw_wrdata_p0              	       (dfi_9_dw_wrdata_p0),
+		.dfi_dw_wrdata_mask_p0                 (dfi_9_dw_wrdata_mask_p0),
+		.dfi_dw_wrdata_dbi_p0                  (dfi_9_dw_wrdata_dbi_p0),
+		.dfi_dw_wrdata_par_p0                  (dfi_9_dw_wrdata_par_p0),
+		.dfi_dw_wrdata_dq_en_p0                (dfi_9_dw_wrdata_dq_en_p0),
+		.dfi_dw_wrdata_par_en_p0               (dfi_9_dw_wrdata_par_en_p0),
+		.dfi_aw_ck_p1            			   (dfi_9_aw_ck_p1),
+		.dfi_aw_cke_p1           			   (dfi_9_aw_cke_p1),
+		.dfi_aw_row_p1                         (dfi_9_aw_row_p1),
+		.dfi_aw_col_p1                         (dfi_9_aw_col_p1),
+		.dfi_dw_wrdata_p1              	       (dfi_9_dw_wrdata_p1),
+		.dfi_dw_wrdata_mask_p1                 (dfi_9_dw_wrdata_mask_p1),
+		.dfi_dw_wrdata_dbi_p1                  (dfi_9_dw_wrdata_dbi_p1),
+		.dfi_dw_wrdata_par_p1                  (dfi_9_dw_wrdata_par_p1),
+		.dfi_dw_wrdata_dq_en_p1                (dfi_9_dw_wrdata_dq_en_p1),
+		.dfi_dw_wrdata_par_en_p1               (dfi_9_dw_wrdata_par_en_p1),
+		.dfi_aw_ck_dis                         (dfi_9_aw_ck_dis),
+		.dfi_lp_pwr_e_req                      (dfi_9_lp_pwr_e_req),
+		.dfi_lp_sr_e_req                       (dfi_9_lp_sr_e_req),
+		.dfi_lp_pwr_x_e_req                    (dfi_9_lp_pwr_x_e_req),
+		.dfi_aw_tx_indx_ld                     (dfi_9_aw_tx_indx_ld),
+		.dfi_dw_tx_indx_ld                     (dfi_9_dw_tx_indx_ld),
+		.dfi_dw_rx_indx_ld                     (dfi_9_dw_rx_indx_ld),
+		.dfi_ctrlupd_ack                       (dfi_9_ctrlupd_ack),
+    	.dfi_phyupd_req                        (dfi_9_phyupd_req),
+    	.ready                                 (w_9_ready)
+    );
+    
+    HBM_interface HBM_interface_CH10 (
+		.row_addr					    	   (o_row_addr),
+		.col_addr							   (o_col_addr),
+		.ba_addr							   (o_ba_addr),
+		.i_wrdata							   (o_i_wrdata),
+		.cmd_type							   (w_10_cmd_type),
+		.BA4								   (o_BA4),
+		
+		.dfi_clk							   (dfi_clk),
+		.dfi_rst_n							   (dfi_rst_n),
+		.dfi_rst_buf_n						   (w_dfi_10_out_rst_n), // this was dfi_10_out_rst_n
+		.dfi_ctrlupd_req					   (dfi_10_ctrlupd_req),
+		.dfi_phyupd_ack						   (dfi_10_phyupd_ack),
+		.dfi_init_complete					   (w_dfi_10_init_complete),
+		
+		.apb_complete_0                        (apb_complete_0),
+	  	.apb_complete_1                        (apb_complete_1),
+	  	.DRAM_0_STAT_CATTRIP                   (DRAM_0_STAT_CATTRIP),
+	  	.DRAM_0_STAT_TEMP                      (DRAM_0_STAT_TEMP   ),
+	  	.DRAM_1_STAT_CATTRIP                   (DRAM_1_STAT_CATTRIP),
+	  	.DRAM_1_STAT_TEMP                      (DRAM_1_STAT_TEMP   ),
+	  	
+		.dfi_init_start 					   (dfi_10_init_start),
+		.dfi_aw_ck_p0            			   (dfi_10_aw_ck_p0),
+		.dfi_aw_cke_p0           			   (dfi_10_aw_cke_p0),
+		.dfi_aw_row_p0                         (dfi_10_aw_row_p0),
+		.dfi_aw_col_p0                         (dfi_10_aw_col_p0),
+		.dfi_dw_wrdata_p0              	       (dfi_10_dw_wrdata_p0),
+		.dfi_dw_wrdata_mask_p0                 (dfi_10_dw_wrdata_mask_p0),
+		.dfi_dw_wrdata_dbi_p0                  (dfi_10_dw_wrdata_dbi_p0),
+		.dfi_dw_wrdata_par_p0                  (dfi_10_dw_wrdata_par_p0),
+		.dfi_dw_wrdata_dq_en_p0                (dfi_10_dw_wrdata_dq_en_p0),
+		.dfi_dw_wrdata_par_en_p0               (dfi_10_dw_wrdata_par_en_p0),
+		.dfi_aw_ck_p1            			   (dfi_10_aw_ck_p1),
+		.dfi_aw_cke_p1           			   (dfi_10_aw_cke_p1),
+		.dfi_aw_row_p1                         (dfi_10_aw_row_p1),
+		.dfi_aw_col_p1                         (dfi_10_aw_col_p1),
+		.dfi_dw_wrdata_p1              	       (dfi_10_dw_wrdata_p1),
+		.dfi_dw_wrdata_mask_p1                 (dfi_10_dw_wrdata_mask_p1),
+		.dfi_dw_wrdata_dbi_p1                  (dfi_10_dw_wrdata_dbi_p1),
+		.dfi_dw_wrdata_par_p1                  (dfi_10_dw_wrdata_par_p1),
+		.dfi_dw_wrdata_dq_en_p1                (dfi_10_dw_wrdata_dq_en_p1),
+		.dfi_dw_wrdata_par_en_p1               (dfi_10_dw_wrdata_par_en_p1),
+		.dfi_aw_ck_dis                         (dfi_10_aw_ck_dis),
+		.dfi_lp_pwr_e_req                      (dfi_10_lp_pwr_e_req),
+		.dfi_lp_sr_e_req                       (dfi_10_lp_sr_e_req),
+		.dfi_lp_pwr_x_e_req                    (dfi_10_lp_pwr_x_e_req),
+		.dfi_aw_tx_indx_ld                     (dfi_10_aw_tx_indx_ld),
+		.dfi_dw_tx_indx_ld                     (dfi_10_dw_tx_indx_ld),
+		.dfi_dw_rx_indx_ld                     (dfi_10_dw_rx_indx_ld),
+		.dfi_ctrlupd_ack                       (dfi_10_ctrlupd_ack),
+    	.dfi_phyupd_req                        (dfi_10_phyupd_req),
+    	.ready                                 (w_10_ready)
+    );
+    
+    HBM_interface HBM_interface_CH11 (
+		.row_addr					    	   (o_row_addr),
+		.col_addr							   (o_col_addr),
+		.ba_addr							   (o_ba_addr),
+		.i_wrdata							   (o_i_wrdata),
+		.cmd_type							   (w_11_cmd_type),
+		.BA4								   (o_BA4),
+		
+		.dfi_clk							   (dfi_clk),
+		.dfi_rst_n							   (dfi_rst_n),
+		.dfi_rst_buf_n						   (w_dfi_11_out_rst_n), // this was dfi_11_out_rst_n
+		.dfi_ctrlupd_req					   (dfi_11_ctrlupd_req),
+		.dfi_phyupd_ack						   (dfi_11_phyupd_ack),
+		.dfi_init_complete					   (w_dfi_11_init_complete),
+		
+		.apb_complete_0                        (apb_complete_0),
+	  	.apb_complete_1                        (apb_complete_1),
+	  	.DRAM_0_STAT_CATTRIP                   (DRAM_0_STAT_CATTRIP),
+	  	.DRAM_0_STAT_TEMP                      (DRAM_0_STAT_TEMP   ),
+	  	.DRAM_1_STAT_CATTRIP                   (DRAM_1_STAT_CATTRIP),
+	  	.DRAM_1_STAT_TEMP                      (DRAM_1_STAT_TEMP   ),
+	  	
+		.dfi_init_start 					   (dfi_11_init_start),
+		.dfi_aw_ck_p0            			   (dfi_11_aw_ck_p0),
+		.dfi_aw_cke_p0           			   (dfi_11_aw_cke_p0),
+		.dfi_aw_row_p0                         (dfi_11_aw_row_p0),
+		.dfi_aw_col_p0                         (dfi_11_aw_col_p0),
+		.dfi_dw_wrdata_p0              	       (dfi_11_dw_wrdata_p0),
+		.dfi_dw_wrdata_mask_p0                 (dfi_11_dw_wrdata_mask_p0),
+		.dfi_dw_wrdata_dbi_p0                  (dfi_11_dw_wrdata_dbi_p0),
+		.dfi_dw_wrdata_par_p0                  (dfi_11_dw_wrdata_par_p0),
+		.dfi_dw_wrdata_dq_en_p0                (dfi_11_dw_wrdata_dq_en_p0),
+		.dfi_dw_wrdata_par_en_p0               (dfi_11_dw_wrdata_par_en_p0),
+		.dfi_aw_ck_p1            			   (dfi_11_aw_ck_p1),
+		.dfi_aw_cke_p1           			   (dfi_11_aw_cke_p1),
+		.dfi_aw_row_p1                         (dfi_11_aw_row_p1),
+		.dfi_aw_col_p1                         (dfi_11_aw_col_p1),
+		.dfi_dw_wrdata_p1              	       (dfi_11_dw_wrdata_p1),
+		.dfi_dw_wrdata_mask_p1                 (dfi_11_dw_wrdata_mask_p1),
+		.dfi_dw_wrdata_dbi_p1                  (dfi_11_dw_wrdata_dbi_p1),
+		.dfi_dw_wrdata_par_p1                  (dfi_11_dw_wrdata_par_p1),
+		.dfi_dw_wrdata_dq_en_p1                (dfi_11_dw_wrdata_dq_en_p1),
+		.dfi_dw_wrdata_par_en_p1               (dfi_11_dw_wrdata_par_en_p1),
+		.dfi_aw_ck_dis                         (dfi_11_aw_ck_dis),
+		.dfi_lp_pwr_e_req                      (dfi_11_lp_pwr_e_req),
+		.dfi_lp_sr_e_req                       (dfi_11_lp_sr_e_req),
+		.dfi_lp_pwr_x_e_req                    (dfi_11_lp_pwr_x_e_req),
+		.dfi_aw_tx_indx_ld                     (dfi_11_aw_tx_indx_ld),
+		.dfi_dw_tx_indx_ld                     (dfi_11_dw_tx_indx_ld),
+		.dfi_dw_rx_indx_ld                     (dfi_11_dw_rx_indx_ld),
+		.dfi_ctrlupd_ack                       (dfi_11_ctrlupd_ack),
+    	.dfi_phyupd_req                        (dfi_11_phyupd_req),
+    	.ready                                 (w_11_ready)
+    );
+    
+    HBM_interface HBM_interface_CH12 (
+		.row_addr					    	   (o_row_addr),
+		.col_addr							   (o_col_addr),
+		.ba_addr							   (o_ba_addr),
+		.i_wrdata							   (o_i_wrdata),
+		.cmd_type							   (w_12_cmd_type),
+		.BA4								   (o_BA4),
+		
+		.dfi_clk							   (dfi_clk),
+		.dfi_rst_n							   (dfi_rst_n),
+		.dfi_rst_buf_n						   (w_dfi_12_out_rst_n), // this was dfi_12_out_rst_n
+		.dfi_ctrlupd_req					   (dfi_12_ctrlupd_req),
+		.dfi_phyupd_ack						   (dfi_12_phyupd_ack),
+		.dfi_init_complete					   (w_dfi_12_init_complete),
+		
+		.apb_complete_0                        (apb_complete_0),
+	  	.apb_complete_1                        (apb_complete_1),
+	  	.DRAM_0_STAT_CATTRIP                   (DRAM_0_STAT_CATTRIP),
+	  	.DRAM_0_STAT_TEMP                      (DRAM_0_STAT_TEMP   ),
+	  	.DRAM_1_STAT_CATTRIP                   (DRAM_1_STAT_CATTRIP),
+	  	.DRAM_1_STAT_TEMP                      (DRAM_1_STAT_TEMP   ),
+	  	
+		.dfi_init_start 					   (dfi_12_init_start),
+		.dfi_aw_ck_p0            			   (dfi_12_aw_ck_p0),
+		.dfi_aw_cke_p0           			   (dfi_12_aw_cke_p0),
+		.dfi_aw_row_p0                         (dfi_12_aw_row_p0),
+		.dfi_aw_col_p0                         (dfi_12_aw_col_p0),
+		.dfi_dw_wrdata_p0              	       (dfi_12_dw_wrdata_p0),
+		.dfi_dw_wrdata_mask_p0                 (dfi_12_dw_wrdata_mask_p0),
+		.dfi_dw_wrdata_dbi_p0                  (dfi_12_dw_wrdata_dbi_p0),
+		.dfi_dw_wrdata_par_p0                  (dfi_12_dw_wrdata_par_p0),
+		.dfi_dw_wrdata_dq_en_p0                (dfi_12_dw_wrdata_dq_en_p0),
+		.dfi_dw_wrdata_par_en_p0               (dfi_12_dw_wrdata_par_en_p0),
+		.dfi_aw_ck_p1            			   (dfi_12_aw_ck_p1),
+		.dfi_aw_cke_p1           			   (dfi_12_aw_cke_p1),
+		.dfi_aw_row_p1                         (dfi_12_aw_row_p1),
+		.dfi_aw_col_p1                         (dfi_12_aw_col_p1),
+		.dfi_dw_wrdata_p1              	       (dfi_12_dw_wrdata_p1),
+		.dfi_dw_wrdata_mask_p1                 (dfi_12_dw_wrdata_mask_p1),
+		.dfi_dw_wrdata_dbi_p1                  (dfi_12_dw_wrdata_dbi_p1),
+		.dfi_dw_wrdata_par_p1                  (dfi_12_dw_wrdata_par_p1),
+		.dfi_dw_wrdata_dq_en_p1                (dfi_12_dw_wrdata_dq_en_p1),
+		.dfi_dw_wrdata_par_en_p1               (dfi_12_dw_wrdata_par_en_p1),
+		.dfi_aw_ck_dis                         (dfi_12_aw_ck_dis),
+		.dfi_lp_pwr_e_req                      (dfi_12_lp_pwr_e_req),
+		.dfi_lp_sr_e_req                       (dfi_12_lp_sr_e_req),
+		.dfi_lp_pwr_x_e_req                    (dfi_12_lp_pwr_x_e_req),
+		.dfi_aw_tx_indx_ld                     (dfi_12_aw_tx_indx_ld),
+		.dfi_dw_tx_indx_ld                     (dfi_12_dw_tx_indx_ld),
+		.dfi_dw_rx_indx_ld                     (dfi_12_dw_rx_indx_ld),
+		.dfi_ctrlupd_ack                       (dfi_12_ctrlupd_ack),
+    	.dfi_phyupd_req                        (dfi_12_phyupd_req),
+    	.ready                                 (w_12_ready)
+    );
+    
+    HBM_interface HBM_interface_CH13 (
+		.row_addr					    	   (o_row_addr),
+		.col_addr							   (o_col_addr),
+		.ba_addr							   (o_ba_addr),
+		.i_wrdata							   (o_i_wrdata),
+		.cmd_type							   (w_13_cmd_type),
+		.BA4								   (o_BA4),
+		
+		.dfi_clk							   (dfi_clk),
+		.dfi_rst_n							   (dfi_rst_n),
+		.dfi_rst_buf_n						   (w_dfi_13_out_rst_n), // this was dfi_13_out_rst_n
+		.dfi_ctrlupd_req					   (dfi_13_ctrlupd_req),
+		.dfi_phyupd_ack						   (dfi_13_phyupd_ack),
+		.dfi_init_complete					   (w_dfi_13_init_complete),
+		
+		.apb_complete_0                        (apb_complete_0),
+	  	.apb_complete_1                        (apb_complete_1),
+	  	.DRAM_0_STAT_CATTRIP                   (DRAM_0_STAT_CATTRIP),
+	  	.DRAM_0_STAT_TEMP                      (DRAM_0_STAT_TEMP   ),
+	  	.DRAM_1_STAT_CATTRIP                   (DRAM_1_STAT_CATTRIP),
+	  	.DRAM_1_STAT_TEMP                      (DRAM_1_STAT_TEMP   ),
+	  	
+		.dfi_init_start 					   (dfi_13_init_start),
+		.dfi_aw_ck_p0            			   (dfi_13_aw_ck_p0),
+		.dfi_aw_cke_p0           			   (dfi_13_aw_cke_p0),
+		.dfi_aw_row_p0                         (dfi_13_aw_row_p0),
+		.dfi_aw_col_p0                         (dfi_13_aw_col_p0),
+		.dfi_dw_wrdata_p0              	       (dfi_13_dw_wrdata_p0),
+		.dfi_dw_wrdata_mask_p0                 (dfi_13_dw_wrdata_mask_p0),
+		.dfi_dw_wrdata_dbi_p0                  (dfi_13_dw_wrdata_dbi_p0),
+		.dfi_dw_wrdata_par_p0                  (dfi_13_dw_wrdata_par_p0),
+		.dfi_dw_wrdata_dq_en_p0                (dfi_13_dw_wrdata_dq_en_p0),
+		.dfi_dw_wrdata_par_en_p0               (dfi_13_dw_wrdata_par_en_p0),
+		.dfi_aw_ck_p1            			   (dfi_13_aw_ck_p1),
+		.dfi_aw_cke_p1           			   (dfi_13_aw_cke_p1),
+		.dfi_aw_row_p1                         (dfi_13_aw_row_p1),
+		.dfi_aw_col_p1                         (dfi_13_aw_col_p1),
+		.dfi_dw_wrdata_p1              	       (dfi_13_dw_wrdata_p1),
+		.dfi_dw_wrdata_mask_p1                 (dfi_13_dw_wrdata_mask_p1),
+		.dfi_dw_wrdata_dbi_p1                  (dfi_13_dw_wrdata_dbi_p1),
+		.dfi_dw_wrdata_par_p1                  (dfi_13_dw_wrdata_par_p1),
+		.dfi_dw_wrdata_dq_en_p1                (dfi_13_dw_wrdata_dq_en_p1),
+		.dfi_dw_wrdata_par_en_p1               (dfi_13_dw_wrdata_par_en_p1),
+		.dfi_aw_ck_dis                         (dfi_13_aw_ck_dis),
+		.dfi_lp_pwr_e_req                      (dfi_13_lp_pwr_e_req),
+		.dfi_lp_sr_e_req                       (dfi_13_lp_sr_e_req),
+		.dfi_lp_pwr_x_e_req                    (dfi_13_lp_pwr_x_e_req),
+		.dfi_aw_tx_indx_ld                     (dfi_13_aw_tx_indx_ld),
+		.dfi_dw_tx_indx_ld                     (dfi_13_dw_tx_indx_ld),
+		.dfi_dw_rx_indx_ld                     (dfi_13_dw_rx_indx_ld),
+		.dfi_ctrlupd_ack                       (dfi_13_ctrlupd_ack),
+    	.dfi_phyupd_req                        (dfi_13_phyupd_req),
+    	.ready                                 (w_13_ready)
+    );
+    
+    HBM_interface HBM_interface_CH14 (
+		.row_addr					    	   (o_row_addr),
+		.col_addr							   (o_col_addr),
+		.ba_addr							   (o_ba_addr),
+		.i_wrdata							   (o_i_wrdata),
+		.cmd_type							   (w_14_cmd_type),
+		.BA4								   (o_BA4),
+		
+		.dfi_clk							   (dfi_clk),
+		.dfi_rst_n							   (dfi_rst_n),
+		.dfi_rst_buf_n						   (w_dfi_14_out_rst_n), // this was dfi_14_out_rst_n
+		.dfi_ctrlupd_req					   (dfi_14_ctrlupd_req),
+		.dfi_phyupd_ack						   (dfi_14_phyupd_ack),
+		.dfi_init_complete					   (w_dfi_14_init_complete),
+		
+		.apb_complete_0                        (apb_complete_0),
+	  	.apb_complete_1                        (apb_complete_1),
+	  	.DRAM_0_STAT_CATTRIP                   (DRAM_0_STAT_CATTRIP),
+	  	.DRAM_0_STAT_TEMP                      (DRAM_0_STAT_TEMP   ),
+	  	.DRAM_1_STAT_CATTRIP                   (DRAM_1_STAT_CATTRIP),
+	  	.DRAM_1_STAT_TEMP                      (DRAM_1_STAT_TEMP   ),
+	  	
+		.dfi_init_start 					   (dfi_14_init_start),
+		.dfi_aw_ck_p0            			   (dfi_14_aw_ck_p0),
+		.dfi_aw_cke_p0           			   (dfi_14_aw_cke_p0),
+		.dfi_aw_row_p0                         (dfi_14_aw_row_p0),
+		.dfi_aw_col_p0                         (dfi_14_aw_col_p0),
+		.dfi_dw_wrdata_p0              	       (dfi_14_dw_wrdata_p0),
+		.dfi_dw_wrdata_mask_p0                 (dfi_14_dw_wrdata_mask_p0),
+		.dfi_dw_wrdata_dbi_p0                  (dfi_14_dw_wrdata_dbi_p0),
+		.dfi_dw_wrdata_par_p0                  (dfi_14_dw_wrdata_par_p0),
+		.dfi_dw_wrdata_dq_en_p0                (dfi_14_dw_wrdata_dq_en_p0),
+		.dfi_dw_wrdata_par_en_p0               (dfi_14_dw_wrdata_par_en_p0),
+		.dfi_aw_ck_p1            			   (dfi_14_aw_ck_p1),
+		.dfi_aw_cke_p1           			   (dfi_14_aw_cke_p1),
+		.dfi_aw_row_p1                         (dfi_14_aw_row_p1),
+		.dfi_aw_col_p1                         (dfi_14_aw_col_p1),
+		.dfi_dw_wrdata_p1              	       (dfi_14_dw_wrdata_p1),
+		.dfi_dw_wrdata_mask_p1                 (dfi_14_dw_wrdata_mask_p1),
+		.dfi_dw_wrdata_dbi_p1                  (dfi_14_dw_wrdata_dbi_p1),
+		.dfi_dw_wrdata_par_p1                  (dfi_14_dw_wrdata_par_p1),
+		.dfi_dw_wrdata_dq_en_p1                (dfi_14_dw_wrdata_dq_en_p1),
+		.dfi_dw_wrdata_par_en_p1               (dfi_14_dw_wrdata_par_en_p1),
+		.dfi_aw_ck_dis                         (dfi_14_aw_ck_dis),
+		.dfi_lp_pwr_e_req                      (dfi_14_lp_pwr_e_req),
+		.dfi_lp_sr_e_req                       (dfi_14_lp_sr_e_req),
+		.dfi_lp_pwr_x_e_req                    (dfi_14_lp_pwr_x_e_req),
+		.dfi_aw_tx_indx_ld                     (dfi_14_aw_tx_indx_ld),
+		.dfi_dw_tx_indx_ld                     (dfi_14_dw_tx_indx_ld),
+		.dfi_dw_rx_indx_ld                     (dfi_14_dw_rx_indx_ld),
+		.dfi_ctrlupd_ack                       (dfi_14_ctrlupd_ack),
+    	.dfi_phyupd_req                        (dfi_14_phyupd_req),
+    	.ready                                 (w_14_ready)
+    );
+    
+    HBM_interface HBM_interface_CH15 (
+		.row_addr					    	   (o_row_addr),
+		.col_addr							   (o_col_addr),
+		.ba_addr							   (o_ba_addr),
+		.i_wrdata							   (o_i_wrdata),
+		.cmd_type							   (w_15_cmd_type),
+		.BA4								   (o_BA4),
+		
+		.dfi_clk							   (dfi_clk),
+		.dfi_rst_n							   (dfi_rst_n),
+		.dfi_rst_buf_n						   (w_dfi_15_out_rst_n), // this was dfi_15_out_rst_n
+		.dfi_ctrlupd_req					   (dfi_15_ctrlupd_req),
+		.dfi_phyupd_ack						   (dfi_15_phyupd_ack),
+		.dfi_init_complete					   (w_dfi_15_init_complete),
+		
+		.apb_complete_0                        (apb_complete_0),
+	  	.apb_complete_1                        (apb_complete_1),
+	  	.DRAM_0_STAT_CATTRIP                   (DRAM_0_STAT_CATTRIP),
+	  	.DRAM_0_STAT_TEMP                      (DRAM_0_STAT_TEMP   ),
+	  	.DRAM_1_STAT_CATTRIP                   (DRAM_1_STAT_CATTRIP),
+	  	.DRAM_1_STAT_TEMP                      (DRAM_1_STAT_TEMP   ),
+	  	
+		.dfi_init_start 					   (dfi_15_init_start),
+		.dfi_aw_ck_p0            			   (dfi_15_aw_ck_p0),
+		.dfi_aw_cke_p0           			   (dfi_15_aw_cke_p0),
+		.dfi_aw_row_p0                         (dfi_15_aw_row_p0),
+		.dfi_aw_col_p0                         (dfi_15_aw_col_p0),
+		.dfi_dw_wrdata_p0              	       (dfi_15_dw_wrdata_p0),
+		.dfi_dw_wrdata_mask_p0                 (dfi_15_dw_wrdata_mask_p0),
+		.dfi_dw_wrdata_dbi_p0                  (dfi_15_dw_wrdata_dbi_p0),
+		.dfi_dw_wrdata_par_p0                  (dfi_15_dw_wrdata_par_p0),
+		.dfi_dw_wrdata_dq_en_p0                (dfi_15_dw_wrdata_dq_en_p0),
+		.dfi_dw_wrdata_par_en_p0               (dfi_15_dw_wrdata_par_en_p0),
+		.dfi_aw_ck_p1            			   (dfi_15_aw_ck_p1),
+		.dfi_aw_cke_p1           			   (dfi_15_aw_cke_p1),
+		.dfi_aw_row_p1                         (dfi_15_aw_row_p1),
+		.dfi_aw_col_p1                         (dfi_15_aw_col_p1),
+		.dfi_dw_wrdata_p1              	       (dfi_15_dw_wrdata_p1),
+		.dfi_dw_wrdata_mask_p1                 (dfi_15_dw_wrdata_mask_p1),
+		.dfi_dw_wrdata_dbi_p1                  (dfi_15_dw_wrdata_dbi_p1),
+		.dfi_dw_wrdata_par_p1                  (dfi_15_dw_wrdata_par_p1),
+		.dfi_dw_wrdata_dq_en_p1                (dfi_15_dw_wrdata_dq_en_p1),
+		.dfi_dw_wrdata_par_en_p1               (dfi_15_dw_wrdata_par_en_p1),
+		.dfi_aw_ck_dis                         (dfi_15_aw_ck_dis),
+		.dfi_lp_pwr_e_req                      (dfi_15_lp_pwr_e_req),
+		.dfi_lp_sr_e_req                       (dfi_15_lp_sr_e_req),
+		.dfi_lp_pwr_x_e_req                    (dfi_15_lp_pwr_x_e_req),
+		.dfi_aw_tx_indx_ld                     (dfi_15_aw_tx_indx_ld),
+		.dfi_dw_tx_indx_ld                     (dfi_15_dw_tx_indx_ld),
+		.dfi_dw_rx_indx_ld                     (dfi_15_dw_rx_indx_ld),
+		.dfi_ctrlupd_ack                       (dfi_15_ctrlupd_ack),
+    	.dfi_phyupd_req                        (dfi_15_phyupd_req),
+    	.ready                                 (w_15_ready)
+    );
+    
+    
+    
+    hbm_0 hbm_inst (
+        .HBM_REF_CLK_0                 (HBM_REF_CLK_0)
+	  	,.HBM_REF_CLK_1                (HBM_REF_CLK_1)
+	  	
+
+	  	/*,.dfi_0_clk                    (dfi_clk)
+	  	,.dfi_0_rst_n                  (dfi_rst_n   )
+	  	,.dfi_0_init_start             (dfi_0_init_start         )
+	  	,.dfi_0_aw_ck_p0               (dfi_0_aw_ck_p0           )
+	  	,.dfi_0_aw_cke_p0              (dfi_0_aw_cke_p0          )
+	  	,.dfi_0_aw_row_p0              (dfi_0_aw_row_p0          )
+	  	,.dfi_0_aw_col_p0              (dfi_0_aw_col_p0          )
+	  	,.dfi_0_dw_wrdata_p0           (dfi_0_dw_wrdata_p0       )
+	  	,.dfi_0_dw_wrdata_mask_p0      (dfi_0_dw_wrdata_mask_p0  )
+	  	,.dfi_0_dw_wrdata_dbi_p0       (dfi_0_dw_wrdata_dbi_p0   )
+	  	,.dfi_0_dw_wrdata_par_p0       (dfi_0_dw_wrdata_par_p0   )
+	  	,.dfi_0_dw_wrdata_dq_en_p0     (dfi_0_dw_wrdata_dq_en_p0 )
+	  	,.dfi_0_dw_wrdata_par_en_p0    (dfi_0_dw_wrdata_par_en_p0)
+	  	,.dfi_0_aw_ck_p1               (dfi_0_aw_ck_p1           )
+	  	,.dfi_0_aw_cke_p1              (dfi_0_aw_cke_p1          )
+	  	,.dfi_0_aw_row_p1              (dfi_0_aw_row_p1          )
+	  	,.dfi_0_aw_col_p1              (dfi_0_aw_col_p1          )
+	  	,.dfi_0_dw_wrdata_p1           (dfi_0_dw_wrdata_p1       )
+	  	,.dfi_0_dw_wrdata_mask_p1      (dfi_0_dw_wrdata_mask_p1  )
+	  	,.dfi_0_dw_wrdata_dbi_p1       (dfi_0_dw_wrdata_dbi_p1   )
+	  	,.dfi_0_dw_wrdata_par_p1       (dfi_0_dw_wrdata_par_p1   )
+	  	,.dfi_0_dw_wrdata_dq_en_p1     (dfi_0_dw_wrdata_dq_en_p1 )
+	  	,.dfi_0_dw_wrdata_par_en_p1    (dfi_0_dw_wrdata_par_en_p1)
+	  	,.dfi_0_aw_ck_dis              (dfi_0_aw_ck_dis          )
+	  	,.dfi_0_lp_pwr_e_req           (dfi_0_lp_pwr_e_req       )
+	  	,.dfi_0_lp_sr_e_req            (dfi_0_lp_sr_e_req        )
+	  	,.dfi_0_lp_pwr_x_req           (dfi_0_lp_pwr_x_e_req     )
+	  	,.dfi_0_aw_tx_indx_ld          (dfi_0_aw_tx_indx_ld      )
+	  	,.dfi_0_dw_tx_indx_ld          (dfi_0_dw_tx_indx_ld      )
+	  	,.dfi_0_dw_rx_indx_ld          (dfi_0_dw_rx_indx_ld      )
+	  	,.dfi_0_ctrlupd_ack            (dfi_0_ctrlupd_ack        )
+	  	,.dfi_0_phyupd_req             (dfi_0_phyupd_req         )
+	  	,.dfi_0_dw_wrdata_dqs_p0       (8'hff)
+	  	,.dfi_0_dw_wrdata_dqs_p1       (8'hff)
+	  	,.dfi_0_dw_rddata_p0           (w_dfi_0_dw_rddata_p0    )
+	  	,.dfi_0_dw_rddata_dm_p0        (dfi_0_dw_rddata_dm_p0 )
+	  	,.dfi_0_dw_rddata_dbi_p0       (dfi_0_dw_rddata_dbi_p0)
+	  	,.dfi_0_dw_rddata_par_p0       (dfi_0_dw_rddata_par_p0)
+	  	,.dfi_0_dw_rddata_p1           (w_dfi_0_dw_rddata_p1    )
+	  	,.dfi_0_dw_rddata_dm_p1        (dfi_0_dw_rddata_dm_p1 )
+	  	,.dfi_0_dw_rddata_dbi_p1       (dfi_0_dw_rddata_dbi_p1)
+	  	,.dfi_0_dw_rddata_par_p1       (dfi_0_dw_rddata_par_p1)
+	  	,.dfi_0_dbi_byte_disable       ( *//* Not Connected *//*  )
+	  	,.dfi_0_dw_rddata_valid        (w_dfi_0_dw_rddata_valid)
+	  	,.dfi_0_dw_derr_n              ( *//* Not Connected *//*  )
+	  	,.dfi_0_aw_aerr_n              ( *//* Not Connected *//*  )
+	  	,.dfi_0_ctrlupd_req            (dfi_0_ctrlupd_req)
+	  	,.dfi_0_phyupd_ack             (dfi_0_phyupd_ack )
+	  	,.dfi_0_clk_init               ( *//* Not Connected *//*  )
+	  	,.dfi_0_init_complete          (w_dfi_0_init_complete)
+	  	,.dfi_0_out_rst_n              (w_dfi_0_out_rst_n    )
+
+
+	  	,.dfi_1_clk                    (dfi_clk)
+	  	,.dfi_1_rst_n                  (dfi_rst_n   )
+	  	,.dfi_1_init_start             (dfi_1_init_start         )
+	  	,.dfi_1_aw_ck_p0               (dfi_1_aw_ck_p0           )
+	  	,.dfi_1_aw_cke_p0              (dfi_1_aw_cke_p0          )
+	  	,.dfi_1_aw_row_p0              (dfi_1_aw_row_p0          )
+	  	,.dfi_1_aw_col_p0              (dfi_1_aw_col_p0          )
+	  	,.dfi_1_dw_wrdata_p0           (dfi_1_dw_wrdata_p0       )
+	  	,.dfi_1_dw_wrdata_mask_p0      (dfi_1_dw_wrdata_mask_p0  )
+	  	,.dfi_1_dw_wrdata_dbi_p0       (dfi_1_dw_wrdata_dbi_p0   )
+	  	,.dfi_1_dw_wrdata_par_p0       (dfi_1_dw_wrdata_par_p0   )
+	  	,.dfi_1_dw_wrdata_dq_en_p0     (dfi_1_dw_wrdata_dq_en_p0 )
+	  	,.dfi_1_dw_wrdata_par_en_p0    (dfi_1_dw_wrdata_par_en_p0)
+	  	,.dfi_1_aw_ck_p1               (dfi_1_aw_ck_p1           )
+	  	,.dfi_1_aw_cke_p1              (dfi_1_aw_cke_p1          )
+	  	,.dfi_1_aw_row_p1              (dfi_1_aw_row_p1          )
+	  	,.dfi_1_aw_col_p1              (dfi_1_aw_col_p1          )
+	  	,.dfi_1_dw_wrdata_p1           (dfi_1_dw_wrdata_p1       )
+	  	,.dfi_1_dw_wrdata_mask_p1      (dfi_1_dw_wrdata_mask_p1  )
+	  	,.dfi_1_dw_wrdata_dbi_p1       (dfi_1_dw_wrdata_dbi_p1   )
+	  	,.dfi_1_dw_wrdata_par_p1       (dfi_1_dw_wrdata_par_p1   )
+	  	,.dfi_1_dw_wrdata_dq_en_p1     (dfi_1_dw_wrdata_dq_en_p1 )
+	  	,.dfi_1_dw_wrdata_par_en_p1    (dfi_1_dw_wrdata_par_en_p1)
+	  	,.dfi_1_aw_ck_dis              (dfi_1_aw_ck_dis          )
+	  	,.dfi_1_lp_pwr_e_req           (dfi_1_lp_pwr_e_req       )
+	  	,.dfi_1_lp_sr_e_req            (dfi_1_lp_sr_e_req        )
+	  	,.dfi_1_lp_pwr_x_req           (dfi_1_lp_pwr_x_e_req     )
+	  	,.dfi_1_aw_tx_indx_ld          (dfi_1_aw_tx_indx_ld      )
+	  	,.dfi_1_dw_tx_indx_ld          (dfi_1_dw_tx_indx_ld      )
+	  	,.dfi_1_dw_rx_indx_ld          (dfi_1_dw_rx_indx_ld      )
+	  	,.dfi_1_ctrlupd_ack            (dfi_1_ctrlupd_ack        )
+	  	,.dfi_1_phyupd_req             (dfi_1_phyupd_req         )
+	  	,.dfi_1_dw_wrdata_dqs_p0       (8'hff)
+	  	,.dfi_1_dw_wrdata_dqs_p1       (8'hff)
+	  	,.dfi_1_dw_rddata_p0           (w_dfi_1_dw_rddata_p0    )
+	  	,.dfi_1_dw_rddata_dm_p0        (dfi_1_dw_rddata_dm_p0 )
+	  	,.dfi_1_dw_rddata_dbi_p0       (dfi_1_dw_rddata_dbi_p0)
+	  	,.dfi_1_dw_rddata_par_p0       (dfi_1_dw_rddata_par_p0)
+	  	,.dfi_1_dw_rddata_p1           (w_dfi_1_dw_rddata_p1    )
+	  	,.dfi_1_dw_rddata_dm_p1        (dfi_1_dw_rddata_dm_p1 )
+	  	,.dfi_1_dw_rddata_dbi_p1       (dfi_1_dw_rddata_dbi_p1)
+	  	,.dfi_1_dw_rddata_par_p1       (dfi_1_dw_rddata_par_p1)
+	  	,.dfi_1_dbi_byte_disable       ( *//* Not Connected *//*  )
+	  	,.dfi_1_dw_rddata_valid        (w_dfi_1_dw_rddata_valid)
+	  	,.dfi_1_dw_derr_n              ( *//* Not Connected *//*  )
+	  	,.dfi_1_aw_aerr_n              ( *//* Not Connected *//*  )
+	  	,.dfi_1_ctrlupd_req            (dfi_1_ctrlupd_req)
+	  	,.dfi_1_phyupd_ack             (dfi_1_phyupd_ack )
+	  	,.dfi_1_clk_init               ( *//* Not Connected *//*  )
+	  	,.dfi_1_init_complete          (w_dfi_1_init_complete)
+	  	,.dfi_1_out_rst_n              (w_dfi_1_out_rst_n    )
+	  	
+
+	  	,.dfi_2_clk                    (dfi_clk)
+	  	,.dfi_2_rst_n                  (dfi_rst_n   )
+	  	,.dfi_2_init_start             (dfi_2_init_start         )
+	  	,.dfi_2_aw_ck_p0               (dfi_2_aw_ck_p0           )
+	  	,.dfi_2_aw_cke_p0              (dfi_2_aw_cke_p0          )
+	  	,.dfi_2_aw_row_p0              (dfi_2_aw_row_p0          )
+	  	,.dfi_2_aw_col_p0              (dfi_2_aw_col_p0          )
+	  	,.dfi_2_dw_wrdata_p0           (dfi_2_dw_wrdata_p0       )
+	  	,.dfi_2_dw_wrdata_mask_p0      (dfi_2_dw_wrdata_mask_p0  )
+	  	,.dfi_2_dw_wrdata_dbi_p0       (dfi_2_dw_wrdata_dbi_p0   )
+	  	,.dfi_2_dw_wrdata_par_p0       (dfi_2_dw_wrdata_par_p0   )
+	  	,.dfi_2_dw_wrdata_dq_en_p0     (dfi_2_dw_wrdata_dq_en_p0 )
+	  	,.dfi_2_dw_wrdata_par_en_p0    (dfi_2_dw_wrdata_par_en_p0)
+	  	,.dfi_2_aw_ck_p1               (dfi_2_aw_ck_p1           )
+	  	,.dfi_2_aw_cke_p1              (dfi_2_aw_cke_p1          )
+	  	,.dfi_2_aw_row_p1              (dfi_2_aw_row_p1          )
+	  	,.dfi_2_aw_col_p1              (dfi_2_aw_col_p1          )
+	  	,.dfi_2_dw_wrdata_p1           (dfi_2_dw_wrdata_p1       )
+	  	,.dfi_2_dw_wrdata_mask_p1      (dfi_2_dw_wrdata_mask_p1  )
+	  	,.dfi_2_dw_wrdata_dbi_p1       (dfi_2_dw_wrdata_dbi_p1   )
+	  	,.dfi_2_dw_wrdata_par_p1       (dfi_2_dw_wrdata_par_p1   )
+	  	,.dfi_2_dw_wrdata_dq_en_p1     (dfi_2_dw_wrdata_dq_en_p1 )
+	  	,.dfi_2_dw_wrdata_par_en_p1    (dfi_2_dw_wrdata_par_en_p1)
+	  	,.dfi_2_aw_ck_dis              (dfi_2_aw_ck_dis          )
+	  	,.dfi_2_lp_pwr_e_req           (dfi_2_lp_pwr_e_req       )
+	  	,.dfi_2_lp_sr_e_req            (dfi_2_lp_sr_e_req        )
+	  	,.dfi_2_lp_pwr_x_req           (dfi_2_lp_pwr_x_e_req     )
+	  	,.dfi_2_aw_tx_indx_ld          (dfi_2_aw_tx_indx_ld      )
+	  	,.dfi_2_dw_tx_indx_ld          (dfi_2_dw_tx_indx_ld      )
+	  	,.dfi_2_dw_rx_indx_ld          (dfi_2_dw_rx_indx_ld      )
+	  	,.dfi_2_ctrlupd_ack            (dfi_2_ctrlupd_ack        )
+	  	,.dfi_2_phyupd_req             (dfi_2_phyupd_req         )
+	  	,.dfi_2_dw_wrdata_dqs_p0       (8'hff)
+	  	,.dfi_2_dw_wrdata_dqs_p1       (8'hff)
+	  	,.dfi_2_dw_rddata_p0           (w_dfi_2_dw_rddata_p0    )
+	  	,.dfi_2_dw_rddata_dm_p0        (dfi_2_dw_rddata_dm_p0 )
+	  	,.dfi_2_dw_rddata_dbi_p0       (dfi_2_dw_rddata_dbi_p0)
+	  	,.dfi_2_dw_rddata_par_p0       (dfi_2_dw_rddata_par_p0)
+	  	,.dfi_2_dw_rddata_p1           (w_dfi_2_dw_rddata_p1    )
+	  	,.dfi_2_dw_rddata_dm_p1        (dfi_2_dw_rddata_dm_p1 )
+	  	,.dfi_2_dw_rddata_dbi_p1       (dfi_2_dw_rddata_dbi_p1)
+	  	,.dfi_2_dw_rddata_par_p1       (dfi_2_dw_rddata_par_p1)
+	  	,.dfi_2_dbi_byte_disable       ( *//* Not Connected *//*  )
+	  	,.dfi_2_dw_rddata_valid        (w_dfi_2_dw_rddata_valid)
+	  	,.dfi_2_dw_derr_n              ( *//* Not Connected *//*  )
+	  	,.dfi_2_aw_aerr_n              ( *//* Not Connected *//*  )
+	  	,.dfi_2_ctrlupd_req            (dfi_2_ctrlupd_req)
+	  	,.dfi_2_phyupd_ack             (dfi_2_phyupd_ack )
+	  	,.dfi_2_clk_init               ( *//* Not Connected *//*  )
+	  	,.dfi_2_init_complete          (w_dfi_2_init_complete)
+	  	,.dfi_2_out_rst_n              (w_dfi_2_out_rst_n    )
+	  	
+
+	  	,.dfi_3_clk                    (dfi_clk)
+	  	,.dfi_3_rst_n                  (dfi_rst_n   )
+	  	,.dfi_3_init_start             (dfi_3_init_start         )
+	  	,.dfi_3_aw_ck_p0               (dfi_3_aw_ck_p0           )
+	  	,.dfi_3_aw_cke_p0              (dfi_3_aw_cke_p0          )
+	  	,.dfi_3_aw_row_p0              (dfi_3_aw_row_p0          )
+	  	,.dfi_3_aw_col_p0              (dfi_3_aw_col_p0          )
+	  	,.dfi_3_dw_wrdata_p0           (dfi_3_dw_wrdata_p0       )
+	  	,.dfi_3_dw_wrdata_mask_p0      (dfi_3_dw_wrdata_mask_p0  )
+	  	,.dfi_3_dw_wrdata_dbi_p0       (dfi_3_dw_wrdata_dbi_p0   )
+	  	,.dfi_3_dw_wrdata_par_p0       (dfi_3_dw_wrdata_par_p0   )
+	  	,.dfi_3_dw_wrdata_dq_en_p0     (dfi_3_dw_wrdata_dq_en_p0 )
+	  	,.dfi_3_dw_wrdata_par_en_p0    (dfi_3_dw_wrdata_par_en_p0)
+	  	,.dfi_3_aw_ck_p1               (dfi_3_aw_ck_p1           )
+	  	,.dfi_3_aw_cke_p1              (dfi_3_aw_cke_p1          )
+	  	,.dfi_3_aw_row_p1              (dfi_3_aw_row_p1          )
+	  	,.dfi_3_aw_col_p1              (dfi_3_aw_col_p1          )
+	  	,.dfi_3_dw_wrdata_p1           (dfi_3_dw_wrdata_p1       )
+	  	,.dfi_3_dw_wrdata_mask_p1      (dfi_3_dw_wrdata_mask_p1  )
+	  	,.dfi_3_dw_wrdata_dbi_p1       (dfi_3_dw_wrdata_dbi_p1   )
+	  	,.dfi_3_dw_wrdata_par_p1       (dfi_3_dw_wrdata_par_p1   )
+	  	,.dfi_3_dw_wrdata_dq_en_p1     (dfi_3_dw_wrdata_dq_en_p1 )
+	  	,.dfi_3_dw_wrdata_par_en_p1    (dfi_3_dw_wrdata_par_en_p1)
+	  	,.dfi_3_aw_ck_dis              (dfi_3_aw_ck_dis          )
+	  	,.dfi_3_lp_pwr_e_req           (dfi_3_lp_pwr_e_req       )
+	  	,.dfi_3_lp_sr_e_req            (dfi_3_lp_sr_e_req        )
+	  	,.dfi_3_lp_pwr_x_req           (dfi_3_lp_pwr_x_e_req     )
+	  	,.dfi_3_aw_tx_indx_ld          (dfi_3_aw_tx_indx_ld      )
+	  	,.dfi_3_dw_tx_indx_ld          (dfi_3_dw_tx_indx_ld      )
+	  	,.dfi_3_dw_rx_indx_ld          (dfi_3_dw_rx_indx_ld      )
+	  	,.dfi_3_ctrlupd_ack            (dfi_3_ctrlupd_ack        )
+	  	,.dfi_3_phyupd_req             (dfi_3_phyupd_req         )
+	  	,.dfi_3_dw_wrdata_dqs_p0       (8'hff)
+	  	,.dfi_3_dw_wrdata_dqs_p1       (8'hff)
+	  	,.dfi_3_dw_rddata_p0           (w_dfi_3_dw_rddata_p0    )
+	  	,.dfi_3_dw_rddata_dm_p0        (dfi_3_dw_rddata_dm_p0 )
+	  	,.dfi_3_dw_rddata_dbi_p0       (dfi_3_dw_rddata_dbi_p0)
+	  	,.dfi_3_dw_rddata_par_p0       (dfi_3_dw_rddata_par_p0)
+	  	,.dfi_3_dw_rddata_p1           (w_dfi_3_dw_rddata_p1    )
+	  	,.dfi_3_dw_rddata_dm_p1        (dfi_3_dw_rddata_dm_p1 )
+	  	,.dfi_3_dw_rddata_dbi_p1       (dfi_3_dw_rddata_dbi_p1)
+	  	,.dfi_3_dw_rddata_par_p1       (dfi_3_dw_rddata_par_p1)
+	  	,.dfi_3_dbi_byte_disable       ( *//* Not Connected *//*  )
+	  	,.dfi_3_dw_rddata_valid        (w_dfi_3_dw_rddata_valid)
+	  	,.dfi_3_dw_derr_n              ( *//* Not Connected *//*  )
+	  	,.dfi_3_aw_aerr_n              ( *//* Not Connected *//*  )
+	  	,.dfi_3_ctrlupd_req            (dfi_3_ctrlupd_req)
+	  	,.dfi_3_phyupd_ack             (dfi_3_phyupd_ack )
+	  	,.dfi_3_clk_init               ( *//* Not Connected *//*  )
+	  	,.dfi_3_init_complete          (w_dfi_3_init_complete)
+	  	,.dfi_3_out_rst_n              (w_dfi_3_out_rst_n    )
+	  	
+
+	  	,.dfi_4_clk                    (dfi_clk)
+	  	,.dfi_4_rst_n                  (dfi_rst_n   )
+	  	,.dfi_4_init_start             (dfi_4_init_start         )
+	  	,.dfi_4_aw_ck_p0               (dfi_4_aw_ck_p0           )
+	  	,.dfi_4_aw_cke_p0              (dfi_4_aw_cke_p0          )
+	  	,.dfi_4_aw_row_p0              (dfi_4_aw_row_p0          )
+	  	,.dfi_4_aw_col_p0              (dfi_4_aw_col_p0          )
+	  	,.dfi_4_dw_wrdata_p0           (dfi_4_dw_wrdata_p0       )
+	  	,.dfi_4_dw_wrdata_mask_p0      (dfi_4_dw_wrdata_mask_p0  )
+	  	,.dfi_4_dw_wrdata_dbi_p0       (dfi_4_dw_wrdata_dbi_p0   )
+	  	,.dfi_4_dw_wrdata_par_p0       (dfi_4_dw_wrdata_par_p0   )
+	  	,.dfi_4_dw_wrdata_dq_en_p0     (dfi_4_dw_wrdata_dq_en_p0 )
+	  	,.dfi_4_dw_wrdata_par_en_p0    (dfi_4_dw_wrdata_par_en_p0)
+	  	,.dfi_4_aw_ck_p1               (dfi_4_aw_ck_p1           )
+	  	,.dfi_4_aw_cke_p1              (dfi_4_aw_cke_p1          )
+	  	,.dfi_4_aw_row_p1              (dfi_4_aw_row_p1          )
+	  	,.dfi_4_aw_col_p1              (dfi_4_aw_col_p1          )
+	  	,.dfi_4_dw_wrdata_p1           (dfi_4_dw_wrdata_p1       )
+	  	,.dfi_4_dw_wrdata_mask_p1      (dfi_4_dw_wrdata_mask_p1  )
+	  	,.dfi_4_dw_wrdata_dbi_p1       (dfi_4_dw_wrdata_dbi_p1   )
+	  	,.dfi_4_dw_wrdata_par_p1       (dfi_4_dw_wrdata_par_p1   )
+	  	,.dfi_4_dw_wrdata_dq_en_p1     (dfi_4_dw_wrdata_dq_en_p1 )
+	  	,.dfi_4_dw_wrdata_par_en_p1    (dfi_4_dw_wrdata_par_en_p1)
+	  	,.dfi_4_aw_ck_dis              (dfi_4_aw_ck_dis          )
+	  	,.dfi_4_lp_pwr_e_req           (dfi_4_lp_pwr_e_req       )
+	  	,.dfi_4_lp_sr_e_req            (dfi_4_lp_sr_e_req        )
+	  	,.dfi_4_lp_pwr_x_req           (dfi_4_lp_pwr_x_e_req     )
+	  	,.dfi_4_aw_tx_indx_ld          (dfi_4_aw_tx_indx_ld      )
+	  	,.dfi_4_dw_tx_indx_ld          (dfi_4_dw_tx_indx_ld      )
+	  	,.dfi_4_dw_rx_indx_ld          (dfi_4_dw_rx_indx_ld      )
+	  	,.dfi_4_ctrlupd_ack            (dfi_4_ctrlupd_ack        )
+	  	,.dfi_4_phyupd_req             (dfi_4_phyupd_req         )
+	  	,.dfi_4_dw_wrdata_dqs_p0       (8'hff)
+	  	,.dfi_4_dw_wrdata_dqs_p1       (8'hff)
+	  	,.dfi_4_dw_rddata_p0           (w_dfi_4_dw_rddata_p0    )
+	  	,.dfi_4_dw_rddata_dm_p0        (dfi_4_dw_rddata_dm_p0 )
+	  	,.dfi_4_dw_rddata_dbi_p0       (dfi_4_dw_rddata_dbi_p0)
+	  	,.dfi_4_dw_rddata_par_p0       (dfi_4_dw_rddata_par_p0)
+	  	,.dfi_4_dw_rddata_p1           (w_dfi_4_dw_rddata_p1    )
+	  	,.dfi_4_dw_rddata_dm_p1        (dfi_4_dw_rddata_dm_p1 )
+	  	,.dfi_4_dw_rddata_dbi_p1       (dfi_4_dw_rddata_dbi_p1)
+	  	,.dfi_4_dw_rddata_par_p1       (dfi_4_dw_rddata_par_p1)
+	  	,.dfi_4_dbi_byte_disable       ( *//* Not Connected *//*  )
+	  	,.dfi_4_dw_rddata_valid        (w_dfi_4_dw_rddata_valid)
+	  	,.dfi_4_dw_derr_n              ( *//* Not Connected *//*  )
+	  	,.dfi_4_aw_aerr_n              ( *//* Not Connected *//*  )
+	  	,.dfi_4_ctrlupd_req            (dfi_4_ctrlupd_req)
+	  	,.dfi_4_phyupd_ack             (dfi_4_phyupd_ack )
+	  	,.dfi_4_clk_init               ( *//* Not Connected *//*  )
+	  	,.dfi_4_init_complete          (w_dfi_4_init_complete)
+	  	,.dfi_4_out_rst_n              (w_dfi_4_out_rst_n    )
+	  	
+
+	  	,.dfi_5_clk                    (dfi_clk)
+	  	,.dfi_5_rst_n                  (dfi_rst_n   )
+	  	,.dfi_5_init_start             (dfi_5_init_start         )
+	  	,.dfi_5_aw_ck_p0               (dfi_5_aw_ck_p0           )
+	  	,.dfi_5_aw_cke_p0              (dfi_5_aw_cke_p0          )
+	  	,.dfi_5_aw_row_p0              (dfi_5_aw_row_p0          )
+	  	,.dfi_5_aw_col_p0              (dfi_5_aw_col_p0          )
+	  	,.dfi_5_dw_wrdata_p0           (dfi_5_dw_wrdata_p0       )
+	  	,.dfi_5_dw_wrdata_mask_p0      (dfi_5_dw_wrdata_mask_p0  )
+	  	,.dfi_5_dw_wrdata_dbi_p0       (dfi_5_dw_wrdata_dbi_p0   )
+	  	,.dfi_5_dw_wrdata_par_p0       (dfi_5_dw_wrdata_par_p0   )
+	  	,.dfi_5_dw_wrdata_dq_en_p0     (dfi_5_dw_wrdata_dq_en_p0 )
+	  	,.dfi_5_dw_wrdata_par_en_p0    (dfi_5_dw_wrdata_par_en_p0)
+	  	,.dfi_5_aw_ck_p1               (dfi_5_aw_ck_p1           )
+	  	,.dfi_5_aw_cke_p1              (dfi_5_aw_cke_p1          )
+	  	,.dfi_5_aw_row_p1              (dfi_5_aw_row_p1          )
+	  	,.dfi_5_aw_col_p1              (dfi_5_aw_col_p1          )
+	  	,.dfi_5_dw_wrdata_p1           (dfi_5_dw_wrdata_p1       )
+	  	,.dfi_5_dw_wrdata_mask_p1      (dfi_5_dw_wrdata_mask_p1  )
+	  	,.dfi_5_dw_wrdata_dbi_p1       (dfi_5_dw_wrdata_dbi_p1   )
+	  	,.dfi_5_dw_wrdata_par_p1       (dfi_5_dw_wrdata_par_p1   )
+	  	,.dfi_5_dw_wrdata_dq_en_p1     (dfi_5_dw_wrdata_dq_en_p1 )
+	  	,.dfi_5_dw_wrdata_par_en_p1    (dfi_5_dw_wrdata_par_en_p1)
+	  	,.dfi_5_aw_ck_dis              (dfi_5_aw_ck_dis          )
+	  	,.dfi_5_lp_pwr_e_req           (dfi_5_lp_pwr_e_req       )
+	  	,.dfi_5_lp_sr_e_req            (dfi_5_lp_sr_e_req        )
+	  	,.dfi_5_lp_pwr_x_req           (dfi_5_lp_pwr_x_e_req     )
+	  	,.dfi_5_aw_tx_indx_ld          (dfi_5_aw_tx_indx_ld      )
+	  	,.dfi_5_dw_tx_indx_ld          (dfi_5_dw_tx_indx_ld      )
+	  	,.dfi_5_dw_rx_indx_ld          (dfi_5_dw_rx_indx_ld      )
+	  	,.dfi_5_ctrlupd_ack            (dfi_5_ctrlupd_ack        )
+	  	,.dfi_5_phyupd_req             (dfi_5_phyupd_req         )
+	  	,.dfi_5_dw_wrdata_dqs_p0       (8'hff)
+	  	,.dfi_5_dw_wrdata_dqs_p1       (8'hff)
+	  	,.dfi_5_dw_rddata_p0           (w_dfi_5_dw_rddata_p0    )
+	  	,.dfi_5_dw_rddata_dm_p0        (dfi_5_dw_rddata_dm_p0 )
+	  	,.dfi_5_dw_rddata_dbi_p0       (dfi_5_dw_rddata_dbi_p0)
+	  	,.dfi_5_dw_rddata_par_p0       (dfi_5_dw_rddata_par_p0)
+	  	,.dfi_5_dw_rddata_p1           (w_dfi_5_dw_rddata_p1    )
+	  	,.dfi_5_dw_rddata_dm_p1        (dfi_5_dw_rddata_dm_p1 )
+	  	,.dfi_5_dw_rddata_dbi_p1       (dfi_5_dw_rddata_dbi_p1)
+	  	,.dfi_5_dw_rddata_par_p1       (dfi_5_dw_rddata_par_p1)
+	  	,.dfi_5_dbi_byte_disable       ( *//* Not Connected *//*  )
+	  	,.dfi_5_dw_rddata_valid        (w_dfi_5_dw_rddata_valid)
+	  	,.dfi_5_dw_derr_n              ( *//* Not Connected *//*  )
+	  	,.dfi_5_aw_aerr_n              ( *//* Not Connected *//*  )
+	  	,.dfi_5_ctrlupd_req            (dfi_5_ctrlupd_req)
+	  	,.dfi_5_phyupd_ack             (dfi_5_phyupd_ack )
+	  	,.dfi_5_clk_init               ( *//* Not Connected *//*  )
+	  	,.dfi_5_init_complete          (w_dfi_5_init_complete)
+	  	,.dfi_5_out_rst_n              (w_dfi_5_out_rst_n    )
+	  	
+
+	  	,.dfi_6_clk                    (dfi_clk)
+	  	,.dfi_6_rst_n                  (dfi_rst_n   )
+	  	,.dfi_6_init_start             (dfi_6_init_start         )
+	  	,.dfi_6_aw_ck_p0               (dfi_6_aw_ck_p0           )
+	  	,.dfi_6_aw_cke_p0              (dfi_6_aw_cke_p0          )
+	  	,.dfi_6_aw_row_p0              (dfi_6_aw_row_p0          )
+	  	,.dfi_6_aw_col_p0              (dfi_6_aw_col_p0          )
+	  	,.dfi_6_dw_wrdata_p0           (dfi_6_dw_wrdata_p0       )
+	  	,.dfi_6_dw_wrdata_mask_p0      (dfi_6_dw_wrdata_mask_p0  )
+	  	,.dfi_6_dw_wrdata_dbi_p0       (dfi_6_dw_wrdata_dbi_p0   )
+	  	,.dfi_6_dw_wrdata_par_p0       (dfi_6_dw_wrdata_par_p0   )
+	  	,.dfi_6_dw_wrdata_dq_en_p0     (dfi_6_dw_wrdata_dq_en_p0 )
+	  	,.dfi_6_dw_wrdata_par_en_p0    (dfi_6_dw_wrdata_par_en_p0)
+	  	,.dfi_6_aw_ck_p1               (dfi_6_aw_ck_p1           )
+	  	,.dfi_6_aw_cke_p1              (dfi_6_aw_cke_p1          )
+	  	,.dfi_6_aw_row_p1              (dfi_6_aw_row_p1          )
+	  	,.dfi_6_aw_col_p1              (dfi_6_aw_col_p1          )
+	  	,.dfi_6_dw_wrdata_p1           (dfi_6_dw_wrdata_p1       )
+	  	,.dfi_6_dw_wrdata_mask_p1      (dfi_6_dw_wrdata_mask_p1  )
+	  	,.dfi_6_dw_wrdata_dbi_p1       (dfi_6_dw_wrdata_dbi_p1   )
+	  	,.dfi_6_dw_wrdata_par_p1       (dfi_6_dw_wrdata_par_p1   )
+	  	,.dfi_6_dw_wrdata_dq_en_p1     (dfi_6_dw_wrdata_dq_en_p1 )
+	  	,.dfi_6_dw_wrdata_par_en_p1    (dfi_6_dw_wrdata_par_en_p1)
+	  	,.dfi_6_aw_ck_dis              (dfi_6_aw_ck_dis          )
+	  	,.dfi_6_lp_pwr_e_req           (dfi_6_lp_pwr_e_req       )
+	  	,.dfi_6_lp_sr_e_req            (dfi_6_lp_sr_e_req        )
+	  	,.dfi_6_lp_pwr_x_req           (dfi_6_lp_pwr_x_e_req     )
+	  	,.dfi_6_aw_tx_indx_ld          (dfi_6_aw_tx_indx_ld      )
+	  	,.dfi_6_dw_tx_indx_ld          (dfi_6_dw_tx_indx_ld      )
+	  	,.dfi_6_dw_rx_indx_ld          (dfi_6_dw_rx_indx_ld      )
+	  	,.dfi_6_ctrlupd_ack            (dfi_6_ctrlupd_ack        )
+	  	,.dfi_6_phyupd_req             (dfi_6_phyupd_req         )
+	  	,.dfi_6_dw_wrdata_dqs_p0       (8'hff)
+	  	,.dfi_6_dw_wrdata_dqs_p1       (8'hff)
+	  	,.dfi_6_dw_rddata_p0           (w_dfi_6_dw_rddata_p0    )
+	  	,.dfi_6_dw_rddata_dm_p0        (dfi_6_dw_rddata_dm_p0 )
+	  	,.dfi_6_dw_rddata_dbi_p0       (dfi_6_dw_rddata_dbi_p0)
+	  	,.dfi_6_dw_rddata_par_p0       (dfi_6_dw_rddata_par_p0)
+	  	,.dfi_6_dw_rddata_p1           (w_dfi_6_dw_rddata_p1    )
+	  	,.dfi_6_dw_rddata_dm_p1        (dfi_6_dw_rddata_dm_p1 )
+	  	,.dfi_6_dw_rddata_dbi_p1       (dfi_6_dw_rddata_dbi_p1)
+	  	,.dfi_6_dw_rddata_par_p1       (dfi_6_dw_rddata_par_p1)
+	  	,.dfi_6_dbi_byte_disable       ( *//* Not Connected *//*  )
+	  	,.dfi_6_dw_rddata_valid        (w_dfi_6_dw_rddata_valid)
+	  	,.dfi_6_dw_derr_n              ( *//* Not Connected *//*  )
+	  	,.dfi_6_aw_aerr_n              ( *//* Not Connected *//*  )
+	  	,.dfi_6_ctrlupd_req            (dfi_6_ctrlupd_req)
+	  	,.dfi_6_phyupd_ack             (dfi_6_phyupd_ack )
+	  	,.dfi_6_clk_init               ( *//* Not Connected *//*  )
+	  	,.dfi_6_init_complete          (w_dfi_6_init_complete)
+	  	,.dfi_6_out_rst_n              (w_dfi_6_out_rst_n    )
+	  	
+
+	  	,.dfi_7_clk                    (dfi_clk)
+	  	,.dfi_7_rst_n                  (dfi_rst_n   )
+	  	,.dfi_7_init_start             (dfi_7_init_start         )
+	  	,.dfi_7_aw_ck_p0               (dfi_7_aw_ck_p0           )
+	  	,.dfi_7_aw_cke_p0              (dfi_7_aw_cke_p0          )
+	  	,.dfi_7_aw_row_p0              (dfi_7_aw_row_p0          )
+	  	,.dfi_7_aw_col_p0              (dfi_7_aw_col_p0          )
+	  	,.dfi_7_dw_wrdata_p0           (dfi_7_dw_wrdata_p0       )
+	  	,.dfi_7_dw_wrdata_mask_p0      (dfi_7_dw_wrdata_mask_p0  )
+	  	,.dfi_7_dw_wrdata_dbi_p0       (dfi_7_dw_wrdata_dbi_p0   )
+	  	,.dfi_7_dw_wrdata_par_p0       (dfi_7_dw_wrdata_par_p0   )
+	  	,.dfi_7_dw_wrdata_dq_en_p0     (dfi_7_dw_wrdata_dq_en_p0 )
+	  	,.dfi_7_dw_wrdata_par_en_p0    (dfi_7_dw_wrdata_par_en_p0)
+	  	,.dfi_7_aw_ck_p1               (dfi_7_aw_ck_p1           )
+	  	,.dfi_7_aw_cke_p1              (dfi_7_aw_cke_p1          )
+	  	,.dfi_7_aw_row_p1              (dfi_7_aw_row_p1          )
+	  	,.dfi_7_aw_col_p1              (dfi_7_aw_col_p1          )
+	  	,.dfi_7_dw_wrdata_p1           (dfi_7_dw_wrdata_p1       )
+	  	,.dfi_7_dw_wrdata_mask_p1      (dfi_7_dw_wrdata_mask_p1  )
+	  	,.dfi_7_dw_wrdata_dbi_p1       (dfi_7_dw_wrdata_dbi_p1   )
+	  	,.dfi_7_dw_wrdata_par_p1       (dfi_7_dw_wrdata_par_p1   )
+	  	,.dfi_7_dw_wrdata_dq_en_p1     (dfi_7_dw_wrdata_dq_en_p1 )
+	  	,.dfi_7_dw_wrdata_par_en_p1    (dfi_7_dw_wrdata_par_en_p1)
+	  	,.dfi_7_aw_ck_dis              (dfi_7_aw_ck_dis          )
+	  	,.dfi_7_lp_pwr_e_req           (dfi_7_lp_pwr_e_req       )
+	  	,.dfi_7_lp_sr_e_req            (dfi_7_lp_sr_e_req        )
+	  	,.dfi_7_lp_pwr_x_req           (dfi_7_lp_pwr_x_e_req     )
+	  	,.dfi_7_aw_tx_indx_ld          (dfi_7_aw_tx_indx_ld      )
+	  	,.dfi_7_dw_tx_indx_ld          (dfi_7_dw_tx_indx_ld      )
+	  	,.dfi_7_dw_rx_indx_ld          (dfi_7_dw_rx_indx_ld      )
+	  	,.dfi_7_ctrlupd_ack            (dfi_7_ctrlupd_ack        )
+	  	,.dfi_7_phyupd_req             (dfi_7_phyupd_req         )
+	  	,.dfi_7_dw_wrdata_dqs_p0       (8'hff)
+	  	,.dfi_7_dw_wrdata_dqs_p1       (8'hff)
+	  	,.dfi_7_dw_rddata_p0           (w_dfi_7_dw_rddata_p0    )
+	  	,.dfi_7_dw_rddata_dm_p0        (dfi_7_dw_rddata_dm_p0 )
+	  	,.dfi_7_dw_rddata_dbi_p0       (dfi_7_dw_rddata_dbi_p0)
+	  	,.dfi_7_dw_rddata_par_p0       (dfi_7_dw_rddata_par_p0)
+	  	,.dfi_7_dw_rddata_p1           (w_dfi_7_dw_rddata_p1    )
+	  	,.dfi_7_dw_rddata_dm_p1        (dfi_7_dw_rddata_dm_p1 )
+	  	,.dfi_7_dw_rddata_dbi_p1       (dfi_7_dw_rddata_dbi_p1)
+	  	,.dfi_7_dw_rddata_par_p1       (dfi_7_dw_rddata_par_p1)
+	  	,.dfi_7_dbi_byte_disable       ( *//* Not Connected *//*  )
+	  	,.dfi_7_dw_rddata_valid        (w_dfi_7_dw_rddata_valid)
+	  	,.dfi_7_dw_derr_n              ( *//* Not Connected *//*  )
+	  	,.dfi_7_aw_aerr_n              ( *//* Not Connected *//*  )
+	  	,.dfi_7_ctrlupd_req            (dfi_7_ctrlupd_req)
+	  	,.dfi_7_phyupd_ack             (dfi_7_phyupd_ack )
+	  	,.dfi_7_clk_init               ( *//* Not Connected *//*  )
+	  	,.dfi_7_init_complete          (w_dfi_7_init_complete)
+	  	,.dfi_7_out_rst_n              (w_dfi_7_out_rst_n    )*/
+	  	
+
+	  	,.dfi_8_clk                    (dfi_clk)
+	  	,.dfi_8_rst_n                  (dfi_rst_n   )
+	  	,.dfi_8_init_start             (dfi_8_init_start         )
+	  	,.dfi_8_aw_ck_p0               (dfi_8_aw_ck_p0           )
+	  	,.dfi_8_aw_cke_p0              (dfi_8_aw_cke_p0          )
+	  	,.dfi_8_aw_row_p0              (dfi_8_aw_row_p0          )
+	  	,.dfi_8_aw_col_p0              (dfi_8_aw_col_p0          )
+	  	,.dfi_8_dw_wrdata_p0           (dfi_8_dw_wrdata_p0       )
+	  	,.dfi_8_dw_wrdata_mask_p0      (dfi_8_dw_wrdata_mask_p0  )
+	  	,.dfi_8_dw_wrdata_dbi_p0       (dfi_8_dw_wrdata_dbi_p0   )
+	  	,.dfi_8_dw_wrdata_par_p0       (dfi_8_dw_wrdata_par_p0   )
+	  	,.dfi_8_dw_wrdata_dq_en_p0     (dfi_8_dw_wrdata_dq_en_p0 )
+	  	,.dfi_8_dw_wrdata_par_en_p0    (dfi_8_dw_wrdata_par_en_p0)
+	  	,.dfi_8_aw_ck_p1               (dfi_8_aw_ck_p1           )
+	  	,.dfi_8_aw_cke_p1              (dfi_8_aw_cke_p1          )
+	  	,.dfi_8_aw_row_p1              (dfi_8_aw_row_p1          )
+	  	,.dfi_8_aw_col_p1              (dfi_8_aw_col_p1          )
+	  	,.dfi_8_dw_wrdata_p1           (dfi_8_dw_wrdata_p1       )
+	  	,.dfi_8_dw_wrdata_mask_p1      (dfi_8_dw_wrdata_mask_p1  )
+	  	,.dfi_8_dw_wrdata_dbi_p1       (dfi_8_dw_wrdata_dbi_p1   )
+	  	,.dfi_8_dw_wrdata_par_p1       (dfi_8_dw_wrdata_par_p1   )
+	  	,.dfi_8_dw_wrdata_dq_en_p1     (dfi_8_dw_wrdata_dq_en_p1 )
+	  	,.dfi_8_dw_wrdata_par_en_p1    (dfi_8_dw_wrdata_par_en_p1)
+	  	,.dfi_8_aw_ck_dis              (dfi_8_aw_ck_dis          )
+	  	,.dfi_8_lp_pwr_e_req           (dfi_8_lp_pwr_e_req       )
+	  	,.dfi_8_lp_sr_e_req            (dfi_8_lp_sr_e_req        )
+	  	,.dfi_8_lp_pwr_x_req           (dfi_8_lp_pwr_x_e_req     )
+	  	,.dfi_8_aw_tx_indx_ld          (dfi_8_aw_tx_indx_ld      )
+	  	,.dfi_8_dw_tx_indx_ld          (dfi_8_dw_tx_indx_ld      )
+	  	,.dfi_8_dw_rx_indx_ld          (dfi_8_dw_rx_indx_ld      )
+	  	,.dfi_8_ctrlupd_ack            (dfi_8_ctrlupd_ack        )
+	  	,.dfi_8_phyupd_req             (dfi_8_phyupd_req         )
+	  	,.dfi_8_dw_wrdata_dqs_p0       (8'hff)
+	  	,.dfi_8_dw_wrdata_dqs_p1       (8'hff)
+	  	,.dfi_8_dw_rddata_p0           (w_dfi_8_dw_rddata_p0    )
+	  	,.dfi_8_dw_rddata_dm_p0        (dfi_8_dw_rddata_dm_p0 )
+	  	,.dfi_8_dw_rddata_dbi_p0       (dfi_8_dw_rddata_dbi_p0)
+	  	,.dfi_8_dw_rddata_par_p0       (dfi_8_dw_rddata_par_p0)
+	  	,.dfi_8_dw_rddata_p1           (w_dfi_8_dw_rddata_p1    )
+	  	,.dfi_8_dw_rddata_dm_p1        (dfi_8_dw_rddata_dm_p1 )
+	  	,.dfi_8_dw_rddata_dbi_p1       (dfi_8_dw_rddata_dbi_p1)
+	  	,.dfi_8_dw_rddata_par_p1       (dfi_8_dw_rddata_par_p1)
+	  	,.dfi_8_dbi_byte_disable       ( /* Not Connected */  )
+	  	,.dfi_8_dw_rddata_valid        (w_dfi_8_dw_rddata_valid)
+	  	,.dfi_8_dw_derr_n              ( /* Not Connected */  )
+	  	,.dfi_8_aw_aerr_n              ( /* Not Connected */  )
+	  	,.dfi_8_ctrlupd_req            (dfi_8_ctrlupd_req)
+	  	,.dfi_8_phyupd_ack             (dfi_8_phyupd_ack )
+	  	,.dfi_8_clk_init               ( /* Not Connected */  )
+	  	,.dfi_8_init_complete          (w_dfi_8_init_complete)
+	  	,.dfi_8_out_rst_n              (w_dfi_8_out_rst_n    )
+	  	
+
+	  	,.dfi_9_clk                    (dfi_clk)
+	  	,.dfi_9_rst_n                  (dfi_rst_n   )
+	  	,.dfi_9_init_start             (dfi_9_init_start         )
+	  	,.dfi_9_aw_ck_p0               (dfi_9_aw_ck_p0           )
+	  	,.dfi_9_aw_cke_p0              (dfi_9_aw_cke_p0          )
+	  	,.dfi_9_aw_row_p0              (dfi_9_aw_row_p0          )
+	  	,.dfi_9_aw_col_p0              (dfi_9_aw_col_p0          )
+	  	,.dfi_9_dw_wrdata_p0           (dfi_9_dw_wrdata_p0       )
+	  	,.dfi_9_dw_wrdata_mask_p0      (dfi_9_dw_wrdata_mask_p0  )
+	  	,.dfi_9_dw_wrdata_dbi_p0       (dfi_9_dw_wrdata_dbi_p0   )
+	  	,.dfi_9_dw_wrdata_par_p0       (dfi_9_dw_wrdata_par_p0   )
+	  	,.dfi_9_dw_wrdata_dq_en_p0     (dfi_9_dw_wrdata_dq_en_p0 )
+	  	,.dfi_9_dw_wrdata_par_en_p0    (dfi_9_dw_wrdata_par_en_p0)
+	  	,.dfi_9_aw_ck_p1               (dfi_9_aw_ck_p1           )
+	  	,.dfi_9_aw_cke_p1              (dfi_9_aw_cke_p1          )
+	  	,.dfi_9_aw_row_p1              (dfi_9_aw_row_p1          )
+	  	,.dfi_9_aw_col_p1              (dfi_9_aw_col_p1          )
+	  	,.dfi_9_dw_wrdata_p1           (dfi_9_dw_wrdata_p1       )
+	  	,.dfi_9_dw_wrdata_mask_p1      (dfi_9_dw_wrdata_mask_p1  )
+	  	,.dfi_9_dw_wrdata_dbi_p1       (dfi_9_dw_wrdata_dbi_p1   )
+	  	,.dfi_9_dw_wrdata_par_p1       (dfi_9_dw_wrdata_par_p1   )
+	  	,.dfi_9_dw_wrdata_dq_en_p1     (dfi_9_dw_wrdata_dq_en_p1 )
+	  	,.dfi_9_dw_wrdata_par_en_p1    (dfi_9_dw_wrdata_par_en_p1)
+	  	,.dfi_9_aw_ck_dis              (dfi_9_aw_ck_dis          )
+	  	,.dfi_9_lp_pwr_e_req           (dfi_9_lp_pwr_e_req       )
+	  	,.dfi_9_lp_sr_e_req            (dfi_9_lp_sr_e_req        )
+	  	,.dfi_9_lp_pwr_x_req           (dfi_9_lp_pwr_x_e_req     )
+	  	,.dfi_9_aw_tx_indx_ld          (dfi_9_aw_tx_indx_ld      )
+	  	,.dfi_9_dw_tx_indx_ld          (dfi_9_dw_tx_indx_ld      )
+	  	,.dfi_9_dw_rx_indx_ld          (dfi_9_dw_rx_indx_ld      )
+	  	,.dfi_9_ctrlupd_ack            (dfi_9_ctrlupd_ack        )
+	  	,.dfi_9_phyupd_req             (dfi_9_phyupd_req         )
+	  	,.dfi_9_dw_wrdata_dqs_p0       (8'hff)
+	  	,.dfi_9_dw_wrdata_dqs_p1       (8'hff)
+	  	,.dfi_9_dw_rddata_p0           (w_dfi_9_dw_rddata_p0    )
+	  	,.dfi_9_dw_rddata_dm_p0        (dfi_9_dw_rddata_dm_p0 )
+	  	,.dfi_9_dw_rddata_dbi_p0       (dfi_9_dw_rddata_dbi_p0)
+	  	,.dfi_9_dw_rddata_par_p0       (dfi_9_dw_rddata_par_p0)
+	  	,.dfi_9_dw_rddata_p1           (w_dfi_9_dw_rddata_p1    )
+	  	,.dfi_9_dw_rddata_dm_p1        (dfi_9_dw_rddata_dm_p1 )
+	  	,.dfi_9_dw_rddata_dbi_p1       (dfi_9_dw_rddata_dbi_p1)
+	  	,.dfi_9_dw_rddata_par_p1       (dfi_9_dw_rddata_par_p1)
+	  	,.dfi_9_dbi_byte_disable       ( /* Not Connected */  )
+	  	,.dfi_9_dw_rddata_valid        (w_dfi_9_dw_rddata_valid)
+	  	,.dfi_9_dw_derr_n              ( /* Not Connected */  )
+	  	,.dfi_9_aw_aerr_n              ( /* Not Connected */  )
+	  	,.dfi_9_ctrlupd_req            (dfi_9_ctrlupd_req)
+	  	,.dfi_9_phyupd_ack             (dfi_9_phyupd_ack )
+	  	,.dfi_9_clk_init               ( /* Not Connected */  )
+	  	,.dfi_9_init_complete          (w_dfi_9_init_complete)
+	  	,.dfi_9_out_rst_n              (w_dfi_9_out_rst_n    )
+	  	
+
+	  	,.dfi_10_clk                    (dfi_clk)
+	  	,.dfi_10_rst_n                  (dfi_rst_n   )
+	  	,.dfi_10_init_start             (dfi_10_init_start         )
+	  	,.dfi_10_aw_ck_p0               (dfi_10_aw_ck_p0           )
+	  	,.dfi_10_aw_cke_p0              (dfi_10_aw_cke_p0          )
+	  	,.dfi_10_aw_row_p0              (dfi_10_aw_row_p0          )
+	  	,.dfi_10_aw_col_p0              (dfi_10_aw_col_p0          )
+	  	,.dfi_10_dw_wrdata_p0           (dfi_10_dw_wrdata_p0       )
+	  	,.dfi_10_dw_wrdata_mask_p0      (dfi_10_dw_wrdata_mask_p0  )
+	  	,.dfi_10_dw_wrdata_dbi_p0       (dfi_10_dw_wrdata_dbi_p0   )
+	  	,.dfi_10_dw_wrdata_par_p0       (dfi_10_dw_wrdata_par_p0   )
+	  	,.dfi_10_dw_wrdata_dq_en_p0     (dfi_10_dw_wrdata_dq_en_p0 )
+	  	,.dfi_10_dw_wrdata_par_en_p0    (dfi_10_dw_wrdata_par_en_p0)
+	  	,.dfi_10_aw_ck_p1               (dfi_10_aw_ck_p1           )
+	  	,.dfi_10_aw_cke_p1              (dfi_10_aw_cke_p1          )
+	  	,.dfi_10_aw_row_p1              (dfi_10_aw_row_p1          )
+	  	,.dfi_10_aw_col_p1              (dfi_10_aw_col_p1          )
+	  	,.dfi_10_dw_wrdata_p1           (dfi_10_dw_wrdata_p1       )
+	  	,.dfi_10_dw_wrdata_mask_p1      (dfi_10_dw_wrdata_mask_p1  )
+	  	,.dfi_10_dw_wrdata_dbi_p1       (dfi_10_dw_wrdata_dbi_p1   )
+	  	,.dfi_10_dw_wrdata_par_p1       (dfi_10_dw_wrdata_par_p1   )
+	  	,.dfi_10_dw_wrdata_dq_en_p1     (dfi_10_dw_wrdata_dq_en_p1 )
+	  	,.dfi_10_dw_wrdata_par_en_p1    (dfi_10_dw_wrdata_par_en_p1)
+	  	,.dfi_10_aw_ck_dis              (dfi_10_aw_ck_dis          )
+	  	,.dfi_10_lp_pwr_e_req           (dfi_10_lp_pwr_e_req       )
+	  	,.dfi_10_lp_sr_e_req            (dfi_10_lp_sr_e_req        )
+	  	,.dfi_10_lp_pwr_x_req           (dfi_10_lp_pwr_x_e_req     )
+	  	,.dfi_10_aw_tx_indx_ld          (dfi_10_aw_tx_indx_ld      )
+	  	,.dfi_10_dw_tx_indx_ld          (dfi_10_dw_tx_indx_ld      )
+	  	,.dfi_10_dw_rx_indx_ld          (dfi_10_dw_rx_indx_ld      )
+	  	,.dfi_10_ctrlupd_ack            (dfi_10_ctrlupd_ack        )
+	  	,.dfi_10_phyupd_req             (dfi_10_phyupd_req         )
+	  	,.dfi_10_dw_wrdata_dqs_p0       (8'hff)
+	  	,.dfi_10_dw_wrdata_dqs_p1       (8'hff)
+	  	,.dfi_10_dw_rddata_p0           (w_dfi_10_dw_rddata_p0    )
+	  	,.dfi_10_dw_rddata_dm_p0        (dfi_10_dw_rddata_dm_p0 )
+	  	,.dfi_10_dw_rddata_dbi_p0       (dfi_10_dw_rddata_dbi_p0)
+	  	,.dfi_10_dw_rddata_par_p0       (dfi_10_dw_rddata_par_p0)
+	  	,.dfi_10_dw_rddata_p1           (w_dfi_10_dw_rddata_p1    )
+	  	,.dfi_10_dw_rddata_dm_p1        (dfi_10_dw_rddata_dm_p1 )
+	  	,.dfi_10_dw_rddata_dbi_p1       (dfi_10_dw_rddata_dbi_p1)
+	  	,.dfi_10_dw_rddata_par_p1       (dfi_10_dw_rddata_par_p1)
+	  	,.dfi_10_dbi_byte_disable       ( /* Not Connected */  )
+	  	,.dfi_10_dw_rddata_valid        (w_dfi_10_dw_rddata_valid)
+	  	,.dfi_10_dw_derr_n              ( /* Not Connected */  )
+	  	,.dfi_10_aw_aerr_n              ( /* Not Connected */  )
+	  	,.dfi_10_ctrlupd_req            (dfi_10_ctrlupd_req)
+	  	,.dfi_10_phyupd_ack             (dfi_10_phyupd_ack )
+	  	,.dfi_10_clk_init               ( /* Not Connected */  )
+	  	,.dfi_10_init_complete          (w_dfi_10_init_complete)
+	  	,.dfi_10_out_rst_n              (w_dfi_10_out_rst_n    )
+	  	
+
+	  	,.dfi_11_clk                    (dfi_clk)
+	  	,.dfi_11_rst_n                  (dfi_rst_n   )
+	  	,.dfi_11_init_start             (dfi_11_init_start         )
+	  	,.dfi_11_aw_ck_p0               (dfi_11_aw_ck_p0           )
+	  	,.dfi_11_aw_cke_p0              (dfi_11_aw_cke_p0          )
+	  	,.dfi_11_aw_row_p0              (dfi_11_aw_row_p0          )
+	  	,.dfi_11_aw_col_p0              (dfi_11_aw_col_p0          )
+	  	,.dfi_11_dw_wrdata_p0           (dfi_11_dw_wrdata_p0       )
+	  	,.dfi_11_dw_wrdata_mask_p0      (dfi_11_dw_wrdata_mask_p0  )
+	  	,.dfi_11_dw_wrdata_dbi_p0       (dfi_11_dw_wrdata_dbi_p0   )
+	  	,.dfi_11_dw_wrdata_par_p0       (dfi_11_dw_wrdata_par_p0   )
+	  	,.dfi_11_dw_wrdata_dq_en_p0     (dfi_11_dw_wrdata_dq_en_p0 )
+	  	,.dfi_11_dw_wrdata_par_en_p0    (dfi_11_dw_wrdata_par_en_p0)
+	  	,.dfi_11_aw_ck_p1               (dfi_11_aw_ck_p1           )
+	  	,.dfi_11_aw_cke_p1              (dfi_11_aw_cke_p1          )
+	  	,.dfi_11_aw_row_p1              (dfi_11_aw_row_p1          )
+	  	,.dfi_11_aw_col_p1              (dfi_11_aw_col_p1          )
+	  	,.dfi_11_dw_wrdata_p1           (dfi_11_dw_wrdata_p1       )
+	  	,.dfi_11_dw_wrdata_mask_p1      (dfi_11_dw_wrdata_mask_p1  )
+	  	,.dfi_11_dw_wrdata_dbi_p1       (dfi_11_dw_wrdata_dbi_p1   )
+	  	,.dfi_11_dw_wrdata_par_p1       (dfi_11_dw_wrdata_par_p1   )
+	  	,.dfi_11_dw_wrdata_dq_en_p1     (dfi_11_dw_wrdata_dq_en_p1 )
+	  	,.dfi_11_dw_wrdata_par_en_p1    (dfi_11_dw_wrdata_par_en_p1)
+	  	,.dfi_11_aw_ck_dis              (dfi_11_aw_ck_dis          )
+	  	,.dfi_11_lp_pwr_e_req           (dfi_11_lp_pwr_e_req       )
+	  	,.dfi_11_lp_sr_e_req            (dfi_11_lp_sr_e_req        )
+	  	,.dfi_11_lp_pwr_x_req           (dfi_11_lp_pwr_x_e_req     )
+	  	,.dfi_11_aw_tx_indx_ld          (dfi_11_aw_tx_indx_ld      )
+	  	,.dfi_11_dw_tx_indx_ld          (dfi_11_dw_tx_indx_ld      )
+	  	,.dfi_11_dw_rx_indx_ld          (dfi_11_dw_rx_indx_ld      )
+	  	,.dfi_11_ctrlupd_ack            (dfi_11_ctrlupd_ack        )
+	  	,.dfi_11_phyupd_req             (dfi_11_phyupd_req         )
+	  	,.dfi_11_dw_wrdata_dqs_p0       (8'hff)
+	  	,.dfi_11_dw_wrdata_dqs_p1       (8'hff)
+	  	,.dfi_11_dw_rddata_p0           (w_dfi_11_dw_rddata_p0    )
+	  	,.dfi_11_dw_rddata_dm_p0        (dfi_11_dw_rddata_dm_p0 )
+	  	,.dfi_11_dw_rddata_dbi_p0       (dfi_11_dw_rddata_dbi_p0)
+	  	,.dfi_11_dw_rddata_par_p0       (dfi_11_dw_rddata_par_p0)
+	  	,.dfi_11_dw_rddata_p1           (w_dfi_11_dw_rddata_p1    )
+	  	,.dfi_11_dw_rddata_dm_p1        (dfi_11_dw_rddata_dm_p1 )
+	  	,.dfi_11_dw_rddata_dbi_p1       (dfi_11_dw_rddata_dbi_p1)
+	  	,.dfi_11_dw_rddata_par_p1       (dfi_11_dw_rddata_par_p1)
+	  	,.dfi_11_dbi_byte_disable       ( /* Not Connected */  )
+	  	,.dfi_11_dw_rddata_valid        (w_dfi_11_dw_rddata_valid)
+	  	,.dfi_11_dw_derr_n              ( /* Not Connected */  )
+	  	,.dfi_11_aw_aerr_n              ( /* Not Connected */  )
+	  	,.dfi_11_ctrlupd_req            (dfi_11_ctrlupd_req)
+	  	,.dfi_11_phyupd_ack             (dfi_11_phyupd_ack )
+	  	,.dfi_11_clk_init               ( /* Not Connected */  )
+	  	,.dfi_11_init_complete          (w_dfi_11_init_complete)
+	  	,.dfi_11_out_rst_n              (w_dfi_11_out_rst_n    )
+	  	
+
+	  	,.dfi_12_clk                    (dfi_clk)
+	  	,.dfi_12_rst_n                  (dfi_rst_n   )
+	  	,.dfi_12_init_start             (dfi_12_init_start         )
+	  	,.dfi_12_aw_ck_p0               (dfi_12_aw_ck_p0           )
+	  	,.dfi_12_aw_cke_p0              (dfi_12_aw_cke_p0          )
+	  	,.dfi_12_aw_row_p0              (dfi_12_aw_row_p0          )
+	  	,.dfi_12_aw_col_p0              (dfi_12_aw_col_p0          )
+	  	,.dfi_12_dw_wrdata_p0           (dfi_12_dw_wrdata_p0       )
+	  	,.dfi_12_dw_wrdata_mask_p0      (dfi_12_dw_wrdata_mask_p0  )
+	  	,.dfi_12_dw_wrdata_dbi_p0       (dfi_12_dw_wrdata_dbi_p0   )
+	  	,.dfi_12_dw_wrdata_par_p0       (dfi_12_dw_wrdata_par_p0   )
+	  	,.dfi_12_dw_wrdata_dq_en_p0     (dfi_12_dw_wrdata_dq_en_p0 )
+	  	,.dfi_12_dw_wrdata_par_en_p0    (dfi_12_dw_wrdata_par_en_p0)
+	  	,.dfi_12_aw_ck_p1               (dfi_12_aw_ck_p1           )
+	  	,.dfi_12_aw_cke_p1              (dfi_12_aw_cke_p1          )
+	  	,.dfi_12_aw_row_p1              (dfi_12_aw_row_p1          )
+	  	,.dfi_12_aw_col_p1              (dfi_12_aw_col_p1          )
+	  	,.dfi_12_dw_wrdata_p1           (dfi_12_dw_wrdata_p1       )
+	  	,.dfi_12_dw_wrdata_mask_p1      (dfi_12_dw_wrdata_mask_p1  )
+	  	,.dfi_12_dw_wrdata_dbi_p1       (dfi_12_dw_wrdata_dbi_p1   )
+	  	,.dfi_12_dw_wrdata_par_p1       (dfi_12_dw_wrdata_par_p1   )
+	  	,.dfi_12_dw_wrdata_dq_en_p1     (dfi_12_dw_wrdata_dq_en_p1 )
+	  	,.dfi_12_dw_wrdata_par_en_p1    (dfi_12_dw_wrdata_par_en_p1)
+	  	,.dfi_12_aw_ck_dis              (dfi_12_aw_ck_dis          )
+	  	,.dfi_12_lp_pwr_e_req           (dfi_12_lp_pwr_e_req       )
+	  	,.dfi_12_lp_sr_e_req            (dfi_12_lp_sr_e_req        )
+	  	,.dfi_12_lp_pwr_x_req           (dfi_12_lp_pwr_x_e_req     )
+	  	,.dfi_12_aw_tx_indx_ld          (dfi_12_aw_tx_indx_ld      )
+	  	,.dfi_12_dw_tx_indx_ld          (dfi_12_dw_tx_indx_ld      )
+	  	,.dfi_12_dw_rx_indx_ld          (dfi_12_dw_rx_indx_ld      )
+	  	,.dfi_12_ctrlupd_ack            (dfi_12_ctrlupd_ack        )
+	  	,.dfi_12_phyupd_req             (dfi_12_phyupd_req         )
+	  	,.dfi_12_dw_wrdata_dqs_p0       (8'hff)
+	  	,.dfi_12_dw_wrdata_dqs_p1       (8'hff)
+	  	,.dfi_12_dw_rddata_p0           (w_dfi_12_dw_rddata_p0    )
+	  	,.dfi_12_dw_rddata_dm_p0        (dfi_12_dw_rddata_dm_p0 )
+	  	,.dfi_12_dw_rddata_dbi_p0       (dfi_12_dw_rddata_dbi_p0)
+	  	,.dfi_12_dw_rddata_par_p0       (dfi_12_dw_rddata_par_p0)
+	  	,.dfi_12_dw_rddata_p1           (w_dfi_12_dw_rddata_p1    )
+	  	,.dfi_12_dw_rddata_dm_p1        (dfi_12_dw_rddata_dm_p1 )
+	  	,.dfi_12_dw_rddata_dbi_p1       (dfi_12_dw_rddata_dbi_p1)
+	  	,.dfi_12_dw_rddata_par_p1       (dfi_12_dw_rddata_par_p1)
+	  	,.dfi_12_dbi_byte_disable       ( /* Not Connected */  )
+	  	,.dfi_12_dw_rddata_valid        (w_dfi_12_dw_rddata_valid)
+	  	,.dfi_12_dw_derr_n              ( /* Not Connected */  )
+	  	,.dfi_12_aw_aerr_n              ( /* Not Connected */  )
+	  	,.dfi_12_ctrlupd_req            (dfi_12_ctrlupd_req)
+	  	,.dfi_12_phyupd_ack             (dfi_12_phyupd_ack )
+	  	,.dfi_12_clk_init               ( /* Not Connected */  )
+	  	,.dfi_12_init_complete          (w_dfi_12_init_complete)
+	  	,.dfi_12_out_rst_n              (w_dfi_12_out_rst_n    )
+	  	
+
+	  	,.dfi_13_clk                    (dfi_clk)
+	  	,.dfi_13_rst_n                  (dfi_rst_n   )
+	  	,.dfi_13_init_start             (dfi_13_init_start         )
+	  	,.dfi_13_aw_ck_p0               (dfi_13_aw_ck_p0           )
+	  	,.dfi_13_aw_cke_p0              (dfi_13_aw_cke_p0          )
+	  	,.dfi_13_aw_row_p0              (dfi_13_aw_row_p0          )
+	  	,.dfi_13_aw_col_p0              (dfi_13_aw_col_p0          )
+	  	,.dfi_13_dw_wrdata_p0           (dfi_13_dw_wrdata_p0       )
+	  	,.dfi_13_dw_wrdata_mask_p0      (dfi_13_dw_wrdata_mask_p0  )
+	  	,.dfi_13_dw_wrdata_dbi_p0       (dfi_13_dw_wrdata_dbi_p0   )
+	  	,.dfi_13_dw_wrdata_par_p0       (dfi_13_dw_wrdata_par_p0   )
+	  	,.dfi_13_dw_wrdata_dq_en_p0     (dfi_13_dw_wrdata_dq_en_p0 )
+	  	,.dfi_13_dw_wrdata_par_en_p0    (dfi_13_dw_wrdata_par_en_p0)
+	  	,.dfi_13_aw_ck_p1               (dfi_13_aw_ck_p1           )
+	  	,.dfi_13_aw_cke_p1              (dfi_13_aw_cke_p1          )
+	  	,.dfi_13_aw_row_p1              (dfi_13_aw_row_p1          )
+	  	,.dfi_13_aw_col_p1              (dfi_13_aw_col_p1          )
+	  	,.dfi_13_dw_wrdata_p1           (dfi_13_dw_wrdata_p1       )
+	  	,.dfi_13_dw_wrdata_mask_p1      (dfi_13_dw_wrdata_mask_p1  )
+	  	,.dfi_13_dw_wrdata_dbi_p1       (dfi_13_dw_wrdata_dbi_p1   )
+	  	,.dfi_13_dw_wrdata_par_p1       (dfi_13_dw_wrdata_par_p1   )
+	  	,.dfi_13_dw_wrdata_dq_en_p1     (dfi_13_dw_wrdata_dq_en_p1 )
+	  	,.dfi_13_dw_wrdata_par_en_p1    (dfi_13_dw_wrdata_par_en_p1)
+	  	,.dfi_13_aw_ck_dis              (dfi_13_aw_ck_dis          )
+	  	,.dfi_13_lp_pwr_e_req           (dfi_13_lp_pwr_e_req       )
+	  	,.dfi_13_lp_sr_e_req            (dfi_13_lp_sr_e_req        )
+	  	,.dfi_13_lp_pwr_x_req           (dfi_13_lp_pwr_x_e_req     )
+	  	,.dfi_13_aw_tx_indx_ld          (dfi_13_aw_tx_indx_ld      )
+	  	,.dfi_13_dw_tx_indx_ld          (dfi_13_dw_tx_indx_ld      )
+	  	,.dfi_13_dw_rx_indx_ld          (dfi_13_dw_rx_indx_ld      )
+	  	,.dfi_13_ctrlupd_ack            (dfi_13_ctrlupd_ack        )
+	  	,.dfi_13_phyupd_req             (dfi_13_phyupd_req         )
+	  	,.dfi_13_dw_wrdata_dqs_p0       (8'hff)
+	  	,.dfi_13_dw_wrdata_dqs_p1       (8'hff)
+	  	,.dfi_13_dw_rddata_p0           (w_dfi_13_dw_rddata_p0    )
+	  	,.dfi_13_dw_rddata_dm_p0        (dfi_13_dw_rddata_dm_p0 )
+	  	,.dfi_13_dw_rddata_dbi_p0       (dfi_13_dw_rddata_dbi_p0)
+	  	,.dfi_13_dw_rddata_par_p0       (dfi_13_dw_rddata_par_p0)
+	  	,.dfi_13_dw_rddata_p1           (w_dfi_13_dw_rddata_p1    )
+	  	,.dfi_13_dw_rddata_dm_p1        (dfi_13_dw_rddata_dm_p1 )
+	  	,.dfi_13_dw_rddata_dbi_p1       (dfi_13_dw_rddata_dbi_p1)
+	  	,.dfi_13_dw_rddata_par_p1       (dfi_13_dw_rddata_par_p1)
+	  	,.dfi_13_dbi_byte_disable       ( /* Not Connected */  )
+	  	,.dfi_13_dw_rddata_valid        (w_dfi_13_dw_rddata_valid)
+	  	,.dfi_13_dw_derr_n              ( /* Not Connected */  )
+	  	,.dfi_13_aw_aerr_n              ( /* Not Connected */  )
+	  	,.dfi_13_ctrlupd_req            (dfi_13_ctrlupd_req)
+	  	,.dfi_13_phyupd_ack             (dfi_13_phyupd_ack )
+	  	,.dfi_13_clk_init               ( /* Not Connected */  )
+	  	,.dfi_13_init_complete          (w_dfi_13_init_complete)
+	  	,.dfi_13_out_rst_n              (w_dfi_13_out_rst_n    )
+	  	
+
+	  	,.dfi_14_clk                    (dfi_clk)
+	  	,.dfi_14_rst_n                  (dfi_rst_n   )
+	  	,.dfi_14_init_start             (dfi_14_init_start         )
+	  	,.dfi_14_aw_ck_p0               (dfi_14_aw_ck_p0           )
+	  	,.dfi_14_aw_cke_p0              (dfi_14_aw_cke_p0          )
+	  	,.dfi_14_aw_row_p0              (dfi_14_aw_row_p0          )
+	  	,.dfi_14_aw_col_p0              (dfi_14_aw_col_p0          )
+	  	,.dfi_14_dw_wrdata_p0           (dfi_14_dw_wrdata_p0       )
+	  	,.dfi_14_dw_wrdata_mask_p0      (dfi_14_dw_wrdata_mask_p0  )
+	  	,.dfi_14_dw_wrdata_dbi_p0       (dfi_14_dw_wrdata_dbi_p0   )
+	  	,.dfi_14_dw_wrdata_par_p0       (dfi_14_dw_wrdata_par_p0   )
+	  	,.dfi_14_dw_wrdata_dq_en_p0     (dfi_14_dw_wrdata_dq_en_p0 )
+	  	,.dfi_14_dw_wrdata_par_en_p0    (dfi_14_dw_wrdata_par_en_p0)
+	  	,.dfi_14_aw_ck_p1               (dfi_14_aw_ck_p1           )
+	  	,.dfi_14_aw_cke_p1              (dfi_14_aw_cke_p1          )
+	  	,.dfi_14_aw_row_p1              (dfi_14_aw_row_p1          )
+	  	,.dfi_14_aw_col_p1              (dfi_14_aw_col_p1          )
+	  	,.dfi_14_dw_wrdata_p1           (dfi_14_dw_wrdata_p1       )
+	  	,.dfi_14_dw_wrdata_mask_p1      (dfi_14_dw_wrdata_mask_p1  )
+	  	,.dfi_14_dw_wrdata_dbi_p1       (dfi_14_dw_wrdata_dbi_p1   )
+	  	,.dfi_14_dw_wrdata_par_p1       (dfi_14_dw_wrdata_par_p1   )
+	  	,.dfi_14_dw_wrdata_dq_en_p1     (dfi_14_dw_wrdata_dq_en_p1 )
+	  	,.dfi_14_dw_wrdata_par_en_p1    (dfi_14_dw_wrdata_par_en_p1)
+	  	,.dfi_14_aw_ck_dis              (dfi_14_aw_ck_dis          )
+	  	,.dfi_14_lp_pwr_e_req           (dfi_14_lp_pwr_e_req       )
+	  	,.dfi_14_lp_sr_e_req            (dfi_14_lp_sr_e_req        )
+	  	,.dfi_14_lp_pwr_x_req           (dfi_14_lp_pwr_x_e_req     )
+	  	,.dfi_14_aw_tx_indx_ld          (dfi_14_aw_tx_indx_ld      )
+	  	,.dfi_14_dw_tx_indx_ld          (dfi_14_dw_tx_indx_ld      )
+	  	,.dfi_14_dw_rx_indx_ld          (dfi_14_dw_rx_indx_ld      )
+	  	,.dfi_14_ctrlupd_ack            (dfi_14_ctrlupd_ack        )
+	  	,.dfi_14_phyupd_req             (dfi_14_phyupd_req         )
+	  	,.dfi_14_dw_wrdata_dqs_p0       (8'hff)
+	  	,.dfi_14_dw_wrdata_dqs_p1       (8'hff)
+	  	,.dfi_14_dw_rddata_p0           (w_dfi_14_dw_rddata_p0    )
+	  	,.dfi_14_dw_rddata_dm_p0        (dfi_14_dw_rddata_dm_p0 )
+	  	,.dfi_14_dw_rddata_dbi_p0       (dfi_14_dw_rddata_dbi_p0)
+	  	,.dfi_14_dw_rddata_par_p0       (dfi_14_dw_rddata_par_p0)
+	  	,.dfi_14_dw_rddata_p1           (w_dfi_14_dw_rddata_p1    )
+	  	,.dfi_14_dw_rddata_dm_p1        (dfi_14_dw_rddata_dm_p1 )
+	  	,.dfi_14_dw_rddata_dbi_p1       (dfi_14_dw_rddata_dbi_p1)
+	  	,.dfi_14_dw_rddata_par_p1       (dfi_14_dw_rddata_par_p1)
+	  	,.dfi_14_dbi_byte_disable       ( /* Not Connected */  )
+	  	,.dfi_14_dw_rddata_valid        (w_dfi_14_dw_rddata_valid)
+	  	,.dfi_14_dw_derr_n              ( /* Not Connected */  )
+	  	,.dfi_14_aw_aerr_n              ( /* Not Connected */  )
+	  	,.dfi_14_ctrlupd_req            (dfi_14_ctrlupd_req)
+	  	,.dfi_14_phyupd_ack             (dfi_14_phyupd_ack )
+	  	,.dfi_14_clk_init               ( /* Not Connected */  )
+	  	,.dfi_14_init_complete          (w_dfi_14_init_complete)
+	  	,.dfi_14_out_rst_n              (w_dfi_14_out_rst_n    )
+	  	
+
+	  	,.dfi_15_clk                    (dfi_clk)
+	  	,.dfi_15_rst_n                  (dfi_rst_n   )
+	  	,.dfi_15_init_start             (dfi_15_init_start         )
+	  	,.dfi_15_aw_ck_p0               (dfi_15_aw_ck_p0           )
+	  	,.dfi_15_aw_cke_p0              (dfi_15_aw_cke_p0          )
+	  	,.dfi_15_aw_row_p0              (dfi_15_aw_row_p0          )
+	  	,.dfi_15_aw_col_p0              (dfi_15_aw_col_p0          )
+	  	,.dfi_15_dw_wrdata_p0           (dfi_15_dw_wrdata_p0       )
+	  	,.dfi_15_dw_wrdata_mask_p0      (dfi_15_dw_wrdata_mask_p0  )
+	  	,.dfi_15_dw_wrdata_dbi_p0       (dfi_15_dw_wrdata_dbi_p0   )
+	  	,.dfi_15_dw_wrdata_par_p0       (dfi_15_dw_wrdata_par_p0   )
+	  	,.dfi_15_dw_wrdata_dq_en_p0     (dfi_15_dw_wrdata_dq_en_p0 )
+	  	,.dfi_15_dw_wrdata_par_en_p0    (dfi_15_dw_wrdata_par_en_p0)
+	  	,.dfi_15_aw_ck_p1               (dfi_15_aw_ck_p1           )
+	  	,.dfi_15_aw_cke_p1              (dfi_15_aw_cke_p1          )
+	  	,.dfi_15_aw_row_p1              (dfi_15_aw_row_p1          )
+	  	,.dfi_15_aw_col_p1              (dfi_15_aw_col_p1          )
+	  	,.dfi_15_dw_wrdata_p1           (dfi_15_dw_wrdata_p1       )
+	  	,.dfi_15_dw_wrdata_mask_p1      (dfi_15_dw_wrdata_mask_p1  )
+	  	,.dfi_15_dw_wrdata_dbi_p1       (dfi_15_dw_wrdata_dbi_p1   )
+	  	,.dfi_15_dw_wrdata_par_p1       (dfi_15_dw_wrdata_par_p1   )
+	  	,.dfi_15_dw_wrdata_dq_en_p1     (dfi_15_dw_wrdata_dq_en_p1 )
+	  	,.dfi_15_dw_wrdata_par_en_p1    (dfi_15_dw_wrdata_par_en_p1)
+	  	,.dfi_15_aw_ck_dis              (dfi_15_aw_ck_dis          )
+	  	,.dfi_15_lp_pwr_e_req           (dfi_15_lp_pwr_e_req       )
+	  	,.dfi_15_lp_sr_e_req            (dfi_15_lp_sr_e_req        )
+	  	,.dfi_15_lp_pwr_x_req           (dfi_15_lp_pwr_x_e_req     )
+	  	,.dfi_15_aw_tx_indx_ld          (dfi_15_aw_tx_indx_ld      )
+	  	,.dfi_15_dw_tx_indx_ld          (dfi_15_dw_tx_indx_ld      )
+	  	,.dfi_15_dw_rx_indx_ld          (dfi_15_dw_rx_indx_ld      )
+	  	,.dfi_15_ctrlupd_ack            (dfi_15_ctrlupd_ack        )
+	  	,.dfi_15_phyupd_req             (dfi_15_phyupd_req         )
+	  	,.dfi_15_dw_wrdata_dqs_p0       (8'hff)
+	  	,.dfi_15_dw_wrdata_dqs_p1       (8'hff)
+	  	,.dfi_15_dw_rddata_p0           (w_dfi_15_dw_rddata_p0    )
+	  	,.dfi_15_dw_rddata_dm_p0        (dfi_15_dw_rddata_dm_p0 )
+	  	,.dfi_15_dw_rddata_dbi_p0       (dfi_15_dw_rddata_dbi_p0)
+	  	,.dfi_15_dw_rddata_par_p0       (dfi_15_dw_rddata_par_p0)
+	  	,.dfi_15_dw_rddata_p1           (w_dfi_15_dw_rddata_p1    )
+	  	,.dfi_15_dw_rddata_dm_p1        (dfi_15_dw_rddata_dm_p1 )
+	  	,.dfi_15_dw_rddata_dbi_p1       (dfi_15_dw_rddata_dbi_p1)
+	  	,.dfi_15_dw_rddata_par_p1       (dfi_15_dw_rddata_par_p1)
+	  	,.dfi_15_dbi_byte_disable       ( /* Not Connected */  )
+	  	,.dfi_15_dw_rddata_valid        (w_dfi_15_dw_rddata_valid)
+	  	,.dfi_15_dw_derr_n              ( /* Not Connected */  )
+	  	,.dfi_15_aw_aerr_n              ( /* Not Connected */  )
+	  	,.dfi_15_ctrlupd_req            (dfi_15_ctrlupd_req)
+	  	,.dfi_15_phyupd_ack             (dfi_15_phyupd_ack )
+	  	,.dfi_15_clk_init               ( /* Not Connected */  )
+	  	,.dfi_15_init_complete          (w_dfi_15_init_complete)
+	  	,.dfi_15_out_rst_n              (w_dfi_15_out_rst_n    )
+	  	
+	  	// Not sure what should these represent
+	  	,.APB_0_PCLK                   (APB_0_PCLK)
+	  	,.APB_0_PRESET_N               (APB_0_PRESET_N)
+	  	,.APB_1_PCLK                   (APB_1_PCLK)
+	  	,.APB_1_PRESET_N               (APB_1_PRESET_N)
+	  	
+	  	,.apb_complete_0               (apb_complete_0)
+	  	,.apb_complete_1               (apb_complete_1)
+	  	,.DRAM_0_STAT_CATTRIP          (DRAM_0_STAT_CATTRIP)
+	  	,.DRAM_0_STAT_TEMP             (DRAM_0_STAT_TEMP   )
+	  	,.DRAM_1_STAT_CATTRIP          (DRAM_1_STAT_CATTRIP)
+	  	,.DRAM_1_STAT_TEMP             (DRAM_1_STAT_TEMP   )
+	);
+    
+    
+endmodule
\ No newline at end of file
diff --git a/projects/U50-HBM/verilog/project.vh b/projects/U50-HBM/verilog/project.vh
new file mode 100644
index 0000000..607ddb5
--- /dev/null
+++ b/projects/U50-HBM/verilog/project.vh
@@ -0,0 +1,27 @@
+`define XUPVVH_HBM
+`define HBM_BENDER
+
+// Row Commands
+`define RNOP	0
+`define ACTT	1
+`define PREE	2  
+`define PREA	3
+`define REFSB	4
+`define REFF	5
+`define PDE		6 
+`define SREE	7 
+`define PDX_SRX	8 
+// Column Commands
+`define CNOP	9 
+`define RD		10
+`define RDA		11
+`define WR		12
+`define WRA		13
+//`define MRS		14
+
+`define ROW_ADDR_WIDTH		14
+`define COL_ADDR_WIDTH		5
+`define BA_ADDR_WIDTH		4
+`define CMD_TYPE_WIDTH		4
+`define PC_WIDTH		    1
+`define WR_DATA_WIDTH       256
\ No newline at end of file
diff --git a/projects/U50-HBM/verilog/softmc_top.v b/projects/U50-HBM/verilog/softmc_top.v
new file mode 100644
index 0000000..f826a5f
--- /dev/null
+++ b/projects/U50-HBM/verilog/softmc_top.v
@@ -0,0 +1,398 @@
+`include "parameters.vh"
+`include "project.vh"
+
+module softmc_top #(parameter tCK = 1500, SIM = "false")
+(
+  // common signals
+  input c0_sys_clk_p,
+  input c0_sys_clk_n,
+  input sys_rst_l,
+  
+  // xdma signals
+  input clk_ref_p,
+  input clk_ref_n,
+  input pcie_rst,
+  output  [7:0]    pci_exp_txp,
+  output  [7:0]    pci_exp_txn,
+  input   [7:0]    pci_exp_rxp,
+  input   [7:0]    pci_exp_rxn,
+  
+  output icc
+);
+  
+  // clock signals
+  wire fab_clk;
+  wire dfi_clk;
+  wire main_clk;
+  
+  // Frontend control signals
+  wire softmc_fin;
+  wire user_rst;  
+  
+  // Frontend <-> Fetch signals
+  wire [`IMEM_ADDR_WIDTH-1:0] fr_addr_in;
+  wire                        fr_valid_in;
+  wire [`INSTR_WIDTH-1:0]     fr_data_out;
+  wire                        fr_valid_out;
+  wire [`IMEM_ADDR_WIDTH-1:0] fr_addr_out;
+  wire                        fr_ready_out;
+
+  // Frontend <-> misc. control signals
+  wire                        per_rd_init;
+  wire                        per_zq_init;
+  wire                        per_ref_init;
+  wire                        rbe_switch_mode;
+  wire                        toggle_dll;  
+
+  // AXI streaming ports
+  wire [`XDMA_AXI_DATA_WIDTH-1:0]   m_axis_h2c_tdata_0,xdma_h2c_tdata_0;
+  wire                              m_axis_h2c_tlast_0, xdma_h2c_tlast_0;
+  wire                              m_axis_h2c_tvalid_0, xdma_h2c_tvalid_0;
+  wire                              m_axis_h2c_tready_0, xdma_h2c_tready_0;
+  wire [`XDMA_AXI_DATA_WIDTH/8-1:0] m_axis_h2c_tkeep_0, xdma_h2c_tkeep_0;
+  wire [`XDMA_AXI_DATA_WIDTH-1:0]   s_axis_c2h_tdata_0, xdma_c2h_tdata_0; 
+  wire                              s_axis_c2h_tlast_0, xdma_c2h_tlast_0;
+  wire                              s_axis_c2h_tvalid_0, xdma_c2h_tvalid_0;
+  wire                              s_axis_c2h_tready_0, xdma_c2h_tready_0;
+  wire [`XDMA_AXI_DATA_WIDTH/8-1:0] s_axis_c2h_tkeep_0, xdma_c2h_tkeep_0;
+ 
+  // ddr_pipeline <-> outer module if
+  wire [3:0]                  ddr_write;
+  wire [3:0]                  ddr_read;
+  wire [3:0]                  ddr_pre;
+  wire [3:0]                  ddr_act;
+  wire [3:0]                  ddr_ref;
+  wire [3:0]                  hbm_sel_ch;
+  wire [3:0]                  ddr_nop;
+  wire [3:0]                  ddr_ap;
+  wire [3:0]                  ddr_pall;
+  wire [3:0]                  ddr_rank;
+  wire [3:0]                  ddr_half_bl;
+  wire [4*`HBM_CH_WIDTH-1:0]  hbm_ch;
+  wire [4*`BG_WIDTH-1:0]      ddr_bg;
+  wire [4*`BANK_WIDTH-1:0]    ddr_bank;
+  wire [4*`COL_WIDTH-1:0]     ddr_col;
+  wire [4*`ROW_WIDTH-1:0]     ddr_row;
+  wire [511:0]                ddr_wdata;
+ 
+  // periodic maintenance signals
+  wire                      ddr_maint_read;
+  
+  wire         read_seq_incoming; // next few instructions will read from DRAM
+  wire [11:0]  incoming_reads;    // how many reads next few instructions will issue
+  wire [11:0]  buffer_space;      // remaining buffer size
+ 
+  wire sys_rst = ~sys_rst_l; // low active signal
+  
+  // HBM PHY signals
+  wire dfi_0_init_complete;
+  wire HBM_ready;
+  wire dfi_0_dw_rddata_valid;
+  wire [255:0] dfi_0_dw_rddata_p0;
+  wire [255:0] dfi_0_dw_rddata_p1;
+  wire hbm_ref_clk_buf;
+  
+  // There is a possibility that these signals are on
+  // the critical path as observed in 
+  // the previous iteration of SoftMC
+  reg dfi_0_init_complete_r, sys_rst_r;
+  wire iq_full, processing_iseq, rdback_fifo_empty;  
+  
+  wire [6:0] hbm0_temp;
+  wire [6:0] hbm1_temp;
+
+  IBUFDS hbm_ref_clk_ibuf (.O(hbm_ref_clk_buf), .I(c0_sys_clk_p), .IB((c0_sys_clk_n)));
+  
+  // clock generation
+  clk_wiz_0 clk_gen (
+    .clk_150MHz(fab_clk),
+    .clk_300MHz(dfi_clk),
+    .clk_in1(hbm_ref_clk_buf)
+  );
+
+  
+  always @(posedge fab_clk) begin
+    dfi_0_init_complete_r <= dfi_0_init_complete;
+    sys_rst_r <= sys_rst;  
+  end
+  
+  reg dllt_active = 1'b0;
+  
+  `ifdef ENABLE_DLL_TOGGLER
+  always @(posedge fab_clk) begin
+    if(toggle_dll) begin
+      dllt_active <= ~dllt_active;
+    end
+    if(dllt_done) begin
+      dllt_active <= ~dllt_active;
+    end
+  end
+  `endif
+    
+  
+  softmc_pipeline pipeline(
+    .clk(fab_clk),
+    .rst(~HBM_ready || user_rst),
+   
+    .softmc_end(softmc_fin),
+    .read_size(incoming_reads),
+    .read_seq_incoming(read_seq_incoming),
+    .buffer_space(buffer_space),
+    
+    .addr_out(fr_addr_in),
+    .valid_out(fr_valid_in),
+    .data_in(fr_data_out),
+    .valid_in(fr_valid_out),
+    .addr_in(fr_addr_out),
+    .ready_out(fr_ready_out),
+   
+    .ddr_write(ddr_write),  
+    .ddr_read(ddr_read),  
+    .ddr_pre(ddr_pre),    
+    .ddr_act(ddr_act),    
+    .ddr_rank(ddr_rank),  
+    .ddr_ref(ddr_ref),    
+    .ddr_zq(hbm_sel_ch),
+    .ddr_nop(ddr_nop),    
+    .ddr_ap(ddr_ap),
+    .ddr_pall(ddr_pall),    
+    //.ddr_half_bl(ddr_half_bl),
+    .hbm_ch(hbm_ch),   
+    .ddr_bg(ddr_bg),    
+    .ddr_bank(ddr_bank),  
+    .ddr_col(ddr_col),    
+    .ddr_row(ddr_row),    
+    .ddr_wdata(ddr_wdata)
+  );
+
+ 
+  assign icc = dfi_0_init_complete_r;
+ 
+  wire frontend_ready;
+  
+  wire hbm_temp_rd;
+  
+  frontend #(.SIM_MEM(SIM)) frontend(
+    .clk(fab_clk),
+    .rst(~HBM_ready),
+    
+    .init_calib_complete(dfi_0_init_complete_r),
+    .softmc_fin(softmc_fin),
+    .user_rst(user_rst),
+   
+    .dllt_begin(toggle_dll),
+   
+    // indicates read_back unit is ready for the next iseq
+    .frontend_ready(frontend_ready),
+   
+    // frontend <-> fetch stage if
+    .addr_in(fr_addr_in),
+    .valid_in(fr_valid_in),
+    .data_out(fr_data_out),
+    .valid_out(fr_valid_out),
+    .addr_out(fr_addr_out),
+    .ready_in(fr_ready_out),
+    
+    .hbm_temp_rd(hbm_temp_rd),
+    
+    // frontend <-> xdma interface
+    .h2c_tdata_0(m_axis_h2c_tdata_0),
+    .h2c_tlast_0(m_axis_h2c_tlast_0),
+    .h2c_tvalid_0(m_axis_h2c_tvalid_0),
+    .h2c_tready_0(m_axis_h2c_tready_0),
+    .h2c_tkeep_0(m_axis_h2c_tkeep_0),
+    
+    .per_rd_init(per_rd_init),
+    .per_zq_init(per_zq_init),
+    .per_ref_init(per_ref_init),
+    .rbe_switch_mode(rbe_switch_mode)
+  );
+
+  wire sys_clk, sys_clk_gt;
+  wire [2:0]    msi_vector_width;
+  wire          msi_enable;
+  wire          user_lnk_up, usr_irq_req, usr_irq_ack;
+  `ifdef XUPVVH_HBM
+  IBUFDS_GTE4 refclk_ibuf (.O(sys_clk_gt), .ODIV2(sys_clk), .I(clk_ref_p), .CEB(1'b0), .IB(clk_ref_n));
+  `else
+  IBUFDS_GTE3 # (.REFCLK_HROW_CK_SEL(2'b01)) refclk_ibuf (.O(sys_clk_gt), .ODIV2(sys_clk), .I(clk_ref_p), .CEB(1'b0), .IB(clk_ref_n));
+  `endif
+  wire axi_clk, axi_rst;
+  
+  
+  xdma xdma_i 
+  (
+    //---------------------------------------------------------------------------------------//
+    //  PCI Express (pci_exp) Interface                                                      //
+    //---------------------------------------------------------------------------------------//
+    .sys_rst_n       ( pcie_rst ),
+    .sys_clk         ( sys_clk ),
+    .sys_clk_gt      ( sys_clk_gt),
+    
+    // Tx
+    .pci_exp_txn     ( pci_exp_txn ),
+    .pci_exp_txp     ( pci_exp_txp ),
+    
+    // Rx
+    .pci_exp_rxn     ( pci_exp_rxn ),
+    .pci_exp_rxp     ( pci_exp_rxp ),
+    
+    // AXI streaming ports
+    .s_axis_c2h_tdata_0(xdma_c2h_tdata_0),  
+    .s_axis_c2h_tlast_0(xdma_c2h_tlast_0),
+    .s_axis_c2h_tvalid_0(xdma_c2h_tvalid_0), 
+    .s_axis_c2h_tready_0(xdma_c2h_tready_0),
+    .s_axis_c2h_tkeep_0(xdma_c2h_tkeep_0),
+    .m_axis_h2c_tdata_0(xdma_h2c_tdata_0),
+    .m_axis_h2c_tlast_0(xdma_h2c_tlast_0),
+    .m_axis_h2c_tvalid_0(xdma_h2c_tvalid_0),
+    .m_axis_h2c_tready_0(xdma_h2c_tready_0),
+    .m_axis_h2c_tkeep_0(xdma_h2c_tkeep_0),
+    
+    .usr_irq_req       (1'b0),
+    .usr_irq_ack       (usr_irq_ack),
+    .msi_enable        (msi_enable),
+    .msi_vector_width  (msi_vector_width),
+    
+    
+    // Config managemnet interface
+    .cfg_mgmt_addr  ( 19'b0 ),
+    .cfg_mgmt_write ( 1'b0 ),
+    .cfg_mgmt_write_data ( 32'b0 ),
+    .cfg_mgmt_byte_enable ( 4'b0 ),
+    .cfg_mgmt_read  ( 1'b0 ),
+    .cfg_mgmt_read_data (),
+    .cfg_mgmt_read_write_done (),
+    `ifndef XUPVVH_HBM
+    .cfg_mgmt_type1_cfg_reg_access ( 1'b0 ),
+    //---------- Shared Logic Internal -------------------------
+    .int_qpll1lock_out          (  ),   
+    .int_qpll1outrefclk_out     (  ),
+    .int_qpll1outclk_out        (  ),
+    `endif
+    
+    //-- AXI Global
+    .axi_aclk        (axi_clk), // AXI i-face clock driven from pcie clk
+    .axi_aresetn     (axi_rst), // reset synchronous to axi_clk
+    
+    .user_lnk_up     ( user_lnk_up )
+  );
+  
+    // Clock converter for the c2h interface
+  axis_clock_converter axis_clk_conv_i0
+  (
+    .s_axis_tvalid(s_axis_c2h_tvalid_0),
+    .s_axis_tlast(s_axis_c2h_tlast_0),
+    .s_axis_tdata(s_axis_c2h_tdata_0),
+    .s_axis_tkeep(s_axis_c2h_tkeep_0),
+    .s_axis_tready(s_axis_c2h_tready_0),
+    .m_axis_tvalid(xdma_c2h_tvalid_0),
+    .m_axis_tlast(xdma_c2h_tlast_0),
+    .m_axis_tdata(xdma_c2h_tdata_0),
+    .m_axis_tkeep(xdma_c2h_tkeep_0),
+    .m_axis_tready(xdma_c2h_tready_0),
+    .s_axis_aresetn(HBM_ready),
+    .s_axis_aclk(fab_clk),
+    .m_axis_aresetn(axi_rst),
+    .m_axis_aclk(axi_clk)
+  );
+  
+  // Clock converter for the h2c interface
+  axis_clock_converter axis_clk_conv_i1
+  (
+    .m_axis_tvalid(m_axis_h2c_tvalid_0),
+    .m_axis_tlast(m_axis_h2c_tlast_0),
+    .m_axis_tdata(m_axis_h2c_tdata_0),
+    .m_axis_tkeep(m_axis_h2c_tkeep_0),
+    .m_axis_tready(m_axis_h2c_tready_0),
+    .s_axis_tvalid(xdma_h2c_tvalid_0),
+    .s_axis_tlast(xdma_h2c_tlast_0),
+    .s_axis_tdata(xdma_h2c_tdata_0),
+    .s_axis_tkeep(xdma_h2c_tkeep_0),
+    .s_axis_tready(xdma_h2c_tready_0),
+    .m_axis_aresetn(HBM_ready),
+    .m_axis_aclk(fab_clk),
+    .s_axis_aresetn(axi_rst),
+    .s_axis_aclk(axi_clk)
+  );
+  
+  
+  readback_engine rbe(     
+    // common signals
+    .clk(fab_clk),
+    .rst(~HBM_ready || user_rst),
+    
+    // other ctrl signals
+    .flush(frontend_ready),
+    .switch_mode(rbe_switch_mode),
+    .read_seq_incoming(read_seq_incoming), // next few instructions will read from DRAM
+    .incoming_reads(incoming_reads),    // how many reads next few instructions will issue
+    .buffer_space(buffer_space),      // remaining buffer size
+    // DRAM <-> engine if
+    
+    // We make sure to retrieve the data following our convention
+    // wr/rddata[255:0] corresponds to PC0, and wr/rddata[511:256] corresponds to PC1
+    .rd_data({dfi_0_dw_rddata_p1, dfi_0_dw_rddata_p0}),
+              
+     // Data is valid when dfi_0_dw_rddata_valid = 0011 (else 1100 or 0000), for now we can just use dfi_0_dw_rddata_valid[0]
+    .rd_valid(dfi_0_dw_rddata_valid),
+     
+    // rbe <-> rf interface  
+    .ddr_wdata(ddr_wdata),
+    
+    .per_rd_init(per_rd_init),
+    .per_zq_init(per_zq_init),
+    .per_ref_init(per_ref_init),
+    
+    `ifdef HBM_BENDER
+    .hbm_temp_rd(hbm_temp_rd),
+    .hbm0_temp(hbm0_temp),
+    .hbm1_temp(hbm1_temp),
+    `endif
+    
+    // rbe <-> xdma if
+    .c2h_tdata_0(s_axis_c2h_tdata_0),  
+    .c2h_tlast_0(s_axis_c2h_tlast_0),
+    .c2h_tvalid_0(s_axis_c2h_tvalid_0),
+    .c2h_tready_0(s_axis_c2h_tready_0), // use this when not simulating: s_axis_c2h_tready_0
+    .c2h_tkeep_0(s_axis_c2h_tkeep_0)  
+  );
+  
+  HBM_adapter HBM_adapter (
+    .c0_sys_clk_p(hbm_ref_clk_buf),
+    .sys_rst(~sys_rst),
+    .fab_clk(fab_clk),
+    .dfi_clk(dfi_clk),
+    .dfi_rst_n(~sys_rst),
+    
+    .ddr_write(ddr_write),  
+    .ddr_read(ddr_read),  
+    .ddr_pre(ddr_pre),    
+    .ddr_act(ddr_act),    
+    .ddr_ref(ddr_ref),    
+    .ddr_rank(ddr_rank),  
+    .hbm_sel_ch(hbm_sel_ch),  
+    .hbm_ch(hbm_ch),
+    .ddr_nop(ddr_nop),    
+    .ddr_ap(ddr_ap),    
+    .ddr_pall(ddr_pall), 
+    .ddr_bg(ddr_bg),    
+    .ddr_bank(ddr_bank),  
+    .ddr_col(ddr_col),    
+    .ddr_row(ddr_row),    
+    .ddr_wdata(ddr_wdata),
+    
+    .o_dfi_0_init_complete(dfi_0_init_complete),
+    .o_HBM_ready(HBM_ready),
+    
+    // Received by readback engine
+    .o_dfi_0_dw_rddata_p0(dfi_0_dw_rddata_p0),
+    .o_dfi_0_dw_rddata_p1(dfi_0_dw_rddata_p1),
+    .o_dfi_0_dw_rddata_valid(dfi_0_dw_rddata_valid),
+    
+    .hbm0_temp(hbm0_temp),
+    .hbm1_temp(hbm1_temp)
+  );
+  
+   
+endmodule