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diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ip/phy_ddr4/phy_ddr4.veo b/projects/XUPVVH/XUPVVH.ip_user_files/ip/phy_ddr4/phy_ddr4.veo
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+// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:ddr4:2.2
+// IP Revision: 8
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+phy_ddr4 your_instance_name (
+  .c0_init_calib_complete(c0_init_calib_complete),    // output wire c0_init_calib_complete
+  .dbg_clk(dbg_clk),                                  // output wire dbg_clk
+  .c0_sys_clk_p(c0_sys_clk_p),                        // input wire c0_sys_clk_p
+  .c0_sys_clk_n(c0_sys_clk_n),                        // input wire c0_sys_clk_n
+  .dbg_bus(dbg_bus),                                  // output wire [511 : 0] dbg_bus
+  .c0_ddr4_parity(c0_ddr4_parity),                    // output wire c0_ddr4_parity
+  .c0_ddr4_ui_clk(c0_ddr4_ui_clk),                    // output wire c0_ddr4_ui_clk
+  .c0_ddr4_ui_clk_sync_rst(c0_ddr4_ui_clk_sync_rst),  // output wire c0_ddr4_ui_clk_sync_rst
+  .sys_rst(sys_rst),                                  // input wire sys_rst
+  .rdDataEn(rdDataEn),                                // output wire [0 : 0] rdDataEn
+  .rdDataEnd(rdDataEnd),                              // output wire [0 : 0] rdDataEnd
+  .per_rd_done(per_rd_done),                          // output wire [0 : 0] per_rd_done
+  .rmw_rd_done(rmw_rd_done),                          // output wire [0 : 0] rmw_rd_done
+  .wrDataEn(wrDataEn),                                // output wire [0 : 0] wrDataEn
+  .mc_ACT_n(mc_ACT_n),                                // input wire [7 : 0] mc_ACT_n
+  .mcCasSlot(mcCasSlot),                              // input wire [1 : 0] mcCasSlot
+  .mcCasSlot2(mcCasSlot2),                            // input wire [0 : 0] mcCasSlot2
+  .mcRdCAS(mcRdCAS),                                  // input wire [0 : 0] mcRdCAS
+  .mcWrCAS(mcWrCAS),                                  // input wire [0 : 0] mcWrCAS
+  .winInjTxn(winInjTxn),                              // input wire [0 : 0] winInjTxn
+  .winRmw(winRmw),                                    // input wire [0 : 0] winRmw
+  .gt_data_ready(gt_data_ready),                      // input wire gt_data_ready
+  .winRank(winRank),                                  // input wire [1 : 0] winRank
+  .tCWL(tCWL),                                        // output wire [5 : 0] tCWL
+  .wrData(wrData),                                    // input wire [575 : 0] wrData
+  .rdData(rdData),                                    // output wire [575 : 0] rdData
+  .mc_ADR(mc_ADR),                                    // input wire [135 : 0] mc_ADR
+  .mc_BA(mc_BA),                                      // input wire [15 : 0] mc_BA
+  .mc_CKE(mc_CKE),                                    // input wire [15 : 0] mc_CKE
+  .mc_CS_n(mc_CS_n),                                  // input wire [15 : 0] mc_CS_n
+  .mc_ODT(mc_ODT),                                    // input wire [15 : 0] mc_ODT
+  .dBufAdr(dBufAdr),                                  // input wire [4 : 0] dBufAdr
+  .rdDataAddr(rdDataAddr),                            // output wire [4 : 0] rdDataAddr
+  .wrDataAddr(wrDataAddr),                            // output wire [4 : 0] wrDataAddr
+  .winBuf(winBuf),                                    // input wire [4 : 0] winBuf
+  .ddr4_act_n(ddr4_act_n),                            // output wire ddr4_act_n
+  .ddr4_adr(ddr4_adr),                                // output wire [16 : 0] ddr4_adr
+  .ddr4_ba(ddr4_ba),                                  // output wire [1 : 0] ddr4_ba
+  .ddr4_bg(ddr4_bg),                                  // output wire [1 : 0] ddr4_bg
+  .ddr4_par(ddr4_par),                                // output wire ddr4_par
+  .ddr4_cke(ddr4_cke),                                // output wire [1 : 0] ddr4_cke
+  .ddr4_odt(ddr4_odt),                                // output wire [1 : 0] ddr4_odt
+  .ddr4_cs_n(ddr4_cs_n),                              // output wire [1 : 0] ddr4_cs_n
+  .ddr4_ck_t(ddr4_ck_t),                              // output wire ddr4_ck_t
+  .ddr4_ck_c(ddr4_ck_c),                              // output wire ddr4_ck_c
+  .ddr4_reset_n(ddr4_reset_n),                        // output wire ddr4_reset_n
+  .ddr4_parity(ddr4_parity),                          // output wire ddr4_parity
+  .ddr4_dq(ddr4_dq),                                  // inout wire [71 : 0] ddr4_dq
+  .ddr4_dqs_c(ddr4_dqs_c),                            // inout wire [17 : 0] ddr4_dqs_c
+  .ddr4_dqs_t(ddr4_dqs_t),                            // inout wire [17 : 0] ddr4_dqs_t
+  .mc_BG(mc_BG)                                      // input wire [15 : 0] mc_BG
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file phy_ddr4.v when simulating
+// the core, phy_ddr4. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ip/phy_ddr4/phy_ddr4.vho b/projects/XUPVVH/XUPVVH.ip_user_files/ip/phy_ddr4/phy_ddr4.vho
new file mode 100755
index 0000000..a2de9eb
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/ip/phy_ddr4/phy_ddr4.vho
@@ -0,0 +1,175 @@
+-- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:ddr4:2.2
+-- IP Revision: 8
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT phy_ddr4
+  PORT (
+    c0_init_calib_complete : OUT STD_LOGIC;
+    dbg_clk : OUT STD_LOGIC;
+    c0_sys_clk_p : IN STD_LOGIC;
+    c0_sys_clk_n : IN STD_LOGIC;
+    dbg_bus : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
+    c0_ddr4_parity : OUT STD_LOGIC;
+    c0_ddr4_ui_clk : OUT STD_LOGIC;
+    c0_ddr4_ui_clk_sync_rst : OUT STD_LOGIC;
+    sys_rst : IN STD_LOGIC;
+    rdDataEn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    rdDataEnd : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    per_rd_done : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    rmw_rd_done : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    wrDataEn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    mc_ACT_n : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    mcCasSlot : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    mcCasSlot2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    mcRdCAS : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    mcWrCAS : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    winInjTxn : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    winRmw : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    gt_data_ready : IN STD_LOGIC;
+    winRank : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    tCWL : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+    wrData : IN STD_LOGIC_VECTOR(575 DOWNTO 0);
+    rdData : OUT STD_LOGIC_VECTOR(575 DOWNTO 0);
+    mc_ADR : IN STD_LOGIC_VECTOR(135 DOWNTO 0);
+    mc_BA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    mc_CKE : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    mc_CS_n : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    mc_ODT : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    dBufAdr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+    rdDataAddr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+    wrDataAddr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+    winBuf : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+    ddr4_act_n : OUT STD_LOGIC;
+    ddr4_adr : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
+    ddr4_ba : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    ddr4_bg : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    ddr4_par : OUT STD_LOGIC;
+    ddr4_cke : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    ddr4_odt : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    ddr4_cs_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    ddr4_ck_t : OUT STD_LOGIC;
+    ddr4_ck_c : OUT STD_LOGIC;
+    ddr4_reset_n : OUT STD_LOGIC;
+    ddr4_parity : OUT STD_LOGIC;
+    ddr4_dq : INOUT STD_LOGIC_VECTOR(71 DOWNTO 0);
+    ddr4_dqs_c : INOUT STD_LOGIC_VECTOR(17 DOWNTO 0);
+    ddr4_dqs_t : INOUT STD_LOGIC_VECTOR(17 DOWNTO 0);
+    mc_BG : IN STD_LOGIC_VECTOR(15 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : phy_ddr4
+  PORT MAP (
+    c0_init_calib_complete => c0_init_calib_complete,
+    dbg_clk => dbg_clk,
+    c0_sys_clk_p => c0_sys_clk_p,
+    c0_sys_clk_n => c0_sys_clk_n,
+    dbg_bus => dbg_bus,
+    c0_ddr4_parity => c0_ddr4_parity,
+    c0_ddr4_ui_clk => c0_ddr4_ui_clk,
+    c0_ddr4_ui_clk_sync_rst => c0_ddr4_ui_clk_sync_rst,
+    sys_rst => sys_rst,
+    rdDataEn => rdDataEn,
+    rdDataEnd => rdDataEnd,
+    per_rd_done => per_rd_done,
+    rmw_rd_done => rmw_rd_done,
+    wrDataEn => wrDataEn,
+    mc_ACT_n => mc_ACT_n,
+    mcCasSlot => mcCasSlot,
+    mcCasSlot2 => mcCasSlot2,
+    mcRdCAS => mcRdCAS,
+    mcWrCAS => mcWrCAS,
+    winInjTxn => winInjTxn,
+    winRmw => winRmw,
+    gt_data_ready => gt_data_ready,
+    winRank => winRank,
+    tCWL => tCWL,
+    wrData => wrData,
+    rdData => rdData,
+    mc_ADR => mc_ADR,
+    mc_BA => mc_BA,
+    mc_CKE => mc_CKE,
+    mc_CS_n => mc_CS_n,
+    mc_ODT => mc_ODT,
+    dBufAdr => dBufAdr,
+    rdDataAddr => rdDataAddr,
+    wrDataAddr => wrDataAddr,
+    winBuf => winBuf,
+    ddr4_act_n => ddr4_act_n,
+    ddr4_adr => ddr4_adr,
+    ddr4_ba => ddr4_ba,
+    ddr4_bg => ddr4_bg,
+    ddr4_par => ddr4_par,
+    ddr4_cke => ddr4_cke,
+    ddr4_odt => ddr4_odt,
+    ddr4_cs_n => ddr4_cs_n,
+    ddr4_ck_t => ddr4_ck_t,
+    ddr4_ck_c => ddr4_ck_c,
+    ddr4_reset_n => ddr4_reset_n,
+    ddr4_parity => ddr4_parity,
+    ddr4_dq => ddr4_dq,
+    ddr4_dqs_c => ddr4_dqs_c,
+    ddr4_dqs_t => ddr4_dqs_t,
+    mc_BG => mc_BG
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file phy_ddr4.vhd when simulating
+-- the core, phy_ddr4. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.v b/projects/XUPVVH/XUPVVH.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.v
new file mode 100644
index 0000000..856787d
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.v
@@ -0,0 +1,75 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+// Date        : Sun Oct 18 14:45:25 2020
+// Host        : jalapeno running 64-bit Ubuntu 18.04.5 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.srcs/sources_1/ip/phy_ddr4/phy_ddr4_stub.v
+// Design      : phy_ddr4
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xcvu37p-fsvh2892-2-e
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "ddr4_v2_2_8,Vivado 2019.2" *)
+module phy_ddr4(sys_rst, c0_sys_clk_p, c0_sys_clk_n, 
+  c0_ddr4_ui_clk, c0_ddr4_ui_clk_sync_rst, dbg_clk, c0_ddr4_act_n, c0_ddr4_adr, c0_ddr4_ba, 
+  c0_ddr4_bg, c0_ddr4_cke, c0_ddr4_odt, c0_ddr4_cs_n, c0_ddr4_ck_t, c0_ddr4_ck_c, 
+  c0_ddr4_reset_n, c0_ddr4_parity, c0_ddr4_dq, c0_ddr4_dqs_c, c0_ddr4_dqs_t, 
+  c0_init_calib_complete, dBufAdr, wrData, rdData, rdDataAddr, rdDataEn, rdDataEnd, per_rd_done, 
+  rmw_rd_done, wrDataAddr, wrDataEn, mc_ACT_n, mc_ADR, mc_BA, mc_BG, mc_CKE, mc_CS_n, mc_ODT, 
+  mcCasSlot, mcCasSlot2, mcRdCAS, mcWrCAS, winInjTxn, winRmw, gt_data_ready, winBuf, winRank, tCWL, 
+  dbg_bus)
+/* synthesis syn_black_box black_box_pad_pin="sys_rst,c0_sys_clk_p,c0_sys_clk_n,c0_ddr4_ui_clk,c0_ddr4_ui_clk_sync_rst,dbg_clk,c0_ddr4_act_n,c0_ddr4_adr[16:0],c0_ddr4_ba[1:0],c0_ddr4_bg[1:0],c0_ddr4_cke[1:0],c0_ddr4_odt[1:0],c0_ddr4_cs_n[1:0],c0_ddr4_ck_t[0:0],c0_ddr4_ck_c[0:0],c0_ddr4_reset_n,c0_ddr4_parity,c0_ddr4_dq[71:0],c0_ddr4_dqs_c[17:0],c0_ddr4_dqs_t[17:0],c0_init_calib_complete,dBufAdr[4:0],wrData[575:0],rdData[575:0],rdDataAddr[4:0],rdDataEn[0:0],rdDataEnd[0:0],per_rd_done[0:0],rmw_rd_done[0:0],wrDataAddr[4:0],wrDataEn[0:0],mc_ACT_n[7:0],mc_ADR[135:0],mc_BA[15:0],mc_BG[15:0],mc_CKE[15:0],mc_CS_n[15:0],mc_ODT[15:0],mcCasSlot[1:0],mcCasSlot2[0:0],mcRdCAS[0:0],mcWrCAS[0:0],winInjTxn[0:0],winRmw[0:0],gt_data_ready,winBuf[4:0],winRank[1:0],tCWL[5:0],dbg_bus[511:0]" */;
+  input sys_rst;
+  input c0_sys_clk_p;
+  input c0_sys_clk_n;
+  output c0_ddr4_ui_clk;
+  output c0_ddr4_ui_clk_sync_rst;
+  output dbg_clk;
+  output c0_ddr4_act_n;
+  output [16:0]c0_ddr4_adr;
+  output [1:0]c0_ddr4_ba;
+  output [1:0]c0_ddr4_bg;
+  output [1:0]c0_ddr4_cke;
+  output [1:0]c0_ddr4_odt;
+  output [1:0]c0_ddr4_cs_n;
+  output [0:0]c0_ddr4_ck_t;
+  output [0:0]c0_ddr4_ck_c;
+  output c0_ddr4_reset_n;
+  output c0_ddr4_parity;
+  inout [71:0]c0_ddr4_dq;
+  inout [17:0]c0_ddr4_dqs_c;
+  inout [17:0]c0_ddr4_dqs_t;
+  output c0_init_calib_complete;
+  input [4:0]dBufAdr;
+  input [575:0]wrData;
+  output [575:0]rdData;
+  output [4:0]rdDataAddr;
+  output [0:0]rdDataEn;
+  output [0:0]rdDataEnd;
+  output [0:0]per_rd_done;
+  output [0:0]rmw_rd_done;
+  output [4:0]wrDataAddr;
+  output [0:0]wrDataEn;
+  input [7:0]mc_ACT_n;
+  input [135:0]mc_ADR;
+  input [15:0]mc_BA;
+  input [15:0]mc_BG;
+  input [15:0]mc_CKE;
+  input [15:0]mc_CS_n;
+  input [15:0]mc_ODT;
+  input [1:0]mcCasSlot;
+  input [0:0]mcCasSlot2;
+  input [0:0]mcRdCAS;
+  input [0:0]mcWrCAS;
+  input [0:0]winInjTxn;
+  input [0:0]winRmw;
+  input gt_data_ready;
+  input [4:0]winBuf;
+  input [1:0]winRank;
+  output [5:0]tCWL;
+  output [511:0]dbg_bus;
+endmodule
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.vhdl b/projects/XUPVVH/XUPVVH.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.vhdl
new file mode 100644
index 0000000..e5a1389
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/ip/phy_ddr4/phy_ddr4_stub.vhdl
@@ -0,0 +1,78 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+-- Date        : Sun Oct 18 14:45:25 2020
+-- Host        : jalapeno running 64-bit Ubuntu 18.04.5 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.srcs/sources_1/ip/phy_ddr4/phy_ddr4_stub.vhdl
+-- Design      : phy_ddr4
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xcvu37p-fsvh2892-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity phy_ddr4 is
+  Port ( 
+    sys_rst : in STD_LOGIC;
+    c0_sys_clk_p : in STD_LOGIC;
+    c0_sys_clk_n : in STD_LOGIC;
+    c0_ddr4_ui_clk : out STD_LOGIC;
+    c0_ddr4_ui_clk_sync_rst : out STD_LOGIC;
+    dbg_clk : out STD_LOGIC;
+    c0_ddr4_act_n : out STD_LOGIC;
+    c0_ddr4_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
+    c0_ddr4_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    c0_ddr4_bg : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    c0_ddr4_cke : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    c0_ddr4_odt : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    c0_ddr4_cs_n : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    c0_ddr4_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
+    c0_ddr4_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
+    c0_ddr4_reset_n : out STD_LOGIC;
+    c0_ddr4_parity : out STD_LOGIC;
+    c0_ddr4_dq : inout STD_LOGIC_VECTOR ( 71 downto 0 );
+    c0_ddr4_dqs_c : inout STD_LOGIC_VECTOR ( 17 downto 0 );
+    c0_ddr4_dqs_t : inout STD_LOGIC_VECTOR ( 17 downto 0 );
+    c0_init_calib_complete : out STD_LOGIC;
+    dBufAdr : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    wrData : in STD_LOGIC_VECTOR ( 575 downto 0 );
+    rdData : out STD_LOGIC_VECTOR ( 575 downto 0 );
+    rdDataAddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
+    rdDataEn : out STD_LOGIC_VECTOR ( 0 to 0 );
+    rdDataEnd : out STD_LOGIC_VECTOR ( 0 to 0 );
+    per_rd_done : out STD_LOGIC_VECTOR ( 0 to 0 );
+    rmw_rd_done : out STD_LOGIC_VECTOR ( 0 to 0 );
+    wrDataAddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
+    wrDataEn : out STD_LOGIC_VECTOR ( 0 to 0 );
+    mc_ACT_n : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    mc_ADR : in STD_LOGIC_VECTOR ( 135 downto 0 );
+    mc_BA : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    mc_BG : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    mc_CKE : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    mc_CS_n : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    mc_ODT : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    mcCasSlot : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    mcCasSlot2 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    mcRdCAS : in STD_LOGIC_VECTOR ( 0 to 0 );
+    mcWrCAS : in STD_LOGIC_VECTOR ( 0 to 0 );
+    winInjTxn : in STD_LOGIC_VECTOR ( 0 to 0 );
+    winRmw : in STD_LOGIC_VECTOR ( 0 to 0 );
+    gt_data_ready : in STD_LOGIC;
+    winBuf : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    winRank : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    tCWL : out STD_LOGIC_VECTOR ( 5 downto 0 );
+    dbg_bus : out STD_LOGIC_VECTOR ( 511 downto 0 )
+  );
+
+end phy_ddr4;
+
+architecture stub of phy_ddr4 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "sys_rst,c0_sys_clk_p,c0_sys_clk_n,c0_ddr4_ui_clk,c0_ddr4_ui_clk_sync_rst,dbg_clk,c0_ddr4_act_n,c0_ddr4_adr[16:0],c0_ddr4_ba[1:0],c0_ddr4_bg[1:0],c0_ddr4_cke[1:0],c0_ddr4_odt[1:0],c0_ddr4_cs_n[1:0],c0_ddr4_ck_t[0:0],c0_ddr4_ck_c[0:0],c0_ddr4_reset_n,c0_ddr4_parity,c0_ddr4_dq[71:0],c0_ddr4_dqs_c[17:0],c0_ddr4_dqs_t[17:0],c0_init_calib_complete,dBufAdr[4:0],wrData[575:0],rdData[575:0],rdDataAddr[4:0],rdDataEn[0:0],rdDataEnd[0:0],per_rd_done[0:0],rmw_rd_done[0:0],wrDataAddr[4:0],wrDataEn[0:0],mc_ACT_n[7:0],mc_ADR[135:0],mc_BA[15:0],mc_BG[15:0],mc_CKE[15:0],mc_CS_n[15:0],mc_ODT[15:0],mcCasSlot[1:0],mcCasSlot2[0:0],mcRdCAS[0:0],mcWrCAS[0:0],winInjTxn[0:0],winRmw[0:0],gt_data_ready,winBuf[4:0],winRank[1:0],tCWL[5:0],dbg_bus[511:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "ddr4_v2_2_8,Vivado 2019.2";
+begin
+end;