Initial commit

4 files changed, 251 insertions, 0 deletions

diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ip/rdback_fifo/rdback_fifo.veo b/projects/XUPVVH/XUPVVH.ip_user_files/ip/rdback_fifo/rdback_fifo.veo
new file mode 100755
index 0000000..48604e9
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/ip/rdback_fifo/rdback_fifo.veo
@@ -0,0 +1,77 @@
+// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:fifo_generator:13.2
+// IP Revision: 5
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+rdback_fifo your_instance_name (
+  .clk(clk),                  // input wire clk
+  .srst(srst),                // input wire srst
+  .din(din),                  // input wire [511 : 0] din
+  .wr_en(wr_en),              // input wire wr_en
+  .rd_en(rd_en),              // input wire rd_en
+  .dout(dout),                // output wire [255 : 0] dout
+  .full(full),                // output wire full
+  .empty(empty),              // output wire empty
+  .valid(valid),              // output wire valid
+  .prog_full(prog_full),      // output wire prog_full
+  .prog_empty(prog_empty),    // output wire prog_empty
+  .wr_rst_busy(wr_rst_busy),  // output wire wr_rst_busy
+  .rd_rst_busy(rd_rst_busy)  // output wire rd_rst_busy
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file rdback_fifo.v when simulating
+// the core, rdback_fifo. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ip/rdback_fifo/rdback_fifo.vho b/projects/XUPVVH/XUPVVH.ip_user_files/ip/rdback_fifo/rdback_fifo.vho
new file mode 100755
index 0000000..c48cbe0
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/ip/rdback_fifo/rdback_fifo.vho
@@ -0,0 +1,99 @@
+-- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
+-- IP Revision: 5
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT rdback_fifo
+  PORT (
+    clk : IN STD_LOGIC;
+    srst : IN STD_LOGIC;
+    din : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
+    wr_en : IN STD_LOGIC;
+    rd_en : IN STD_LOGIC;
+    dout : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
+    full : OUT STD_LOGIC;
+    empty : OUT STD_LOGIC;
+    valid : OUT STD_LOGIC;
+    prog_full : OUT STD_LOGIC;
+    prog_empty : OUT STD_LOGIC;
+    wr_rst_busy : OUT STD_LOGIC;
+    rd_rst_busy : OUT STD_LOGIC
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : rdback_fifo
+  PORT MAP (
+    clk => clk,
+    srst => srst,
+    din => din,
+    wr_en => wr_en,
+    rd_en => rd_en,
+    dout => dout,
+    full => full,
+    empty => empty,
+    valid => valid,
+    prog_full => prog_full,
+    prog_empty => prog_empty,
+    wr_rst_busy => wr_rst_busy,
+    rd_rst_busy => rd_rst_busy
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file rdback_fifo.vhd when simulating
+-- the core, rdback_fifo. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.v b/projects/XUPVVH/XUPVVH.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.v
new file mode 100644
index 0000000..cad3ff7
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.v
@@ -0,0 +1,33 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+// Date        : Sun Oct 18 14:26:16 2020
+// Host        : jalapeno running 64-bit Ubuntu 18.04.5 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.srcs/sources_1/ip/rdback_fifo/rdback_fifo_stub.v
+// Design      : rdback_fifo
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xcvu37p-fsvh2892-2-e
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "fifo_generator_v13_2_5,Vivado 2019.2" *)
+module rdback_fifo(clk, srst, din, wr_en, rd_en, dout, full, empty, valid, 
+  prog_full, prog_empty, wr_rst_busy, rd_rst_busy)
+/* synthesis syn_black_box black_box_pad_pin="clk,srst,din[511:0],wr_en,rd_en,dout[255:0],full,empty,valid,prog_full,prog_empty,wr_rst_busy,rd_rst_busy" */;
+  input clk;
+  input srst;
+  input [511:0]din;
+  input wr_en;
+  input rd_en;
+  output [255:0]dout;
+  output full;
+  output empty;
+  output valid;
+  output prog_full;
+  output prog_empty;
+  output wr_rst_busy;
+  output rd_rst_busy;
+endmodule
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.vhdl b/projects/XUPVVH/XUPVVH.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.vhdl
new file mode 100644
index 0000000..fcc0412
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/ip/rdback_fifo/rdback_fifo_stub.vhdl
@@ -0,0 +1,42 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+-- Date        : Sun Oct 18 14:26:16 2020
+-- Host        : jalapeno running 64-bit Ubuntu 18.04.5 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.srcs/sources_1/ip/rdback_fifo/rdback_fifo_stub.vhdl
+-- Design      : rdback_fifo
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xcvu37p-fsvh2892-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity rdback_fifo is
+  Port ( 
+    clk : in STD_LOGIC;
+    srst : in STD_LOGIC;
+    din : in STD_LOGIC_VECTOR ( 511 downto 0 );
+    wr_en : in STD_LOGIC;
+    rd_en : in STD_LOGIC;
+    dout : out STD_LOGIC_VECTOR ( 255 downto 0 );
+    full : out STD_LOGIC;
+    empty : out STD_LOGIC;
+    valid : out STD_LOGIC;
+    prog_full : out STD_LOGIC;
+    prog_empty : out STD_LOGIC;
+    wr_rst_busy : out STD_LOGIC;
+    rd_rst_busy : out STD_LOGIC
+  );
+
+end rdback_fifo;
+
+architecture stub of rdback_fifo is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk,srst,din[511:0],wr_en,rd_en,dout[255:0],full,empty,valid,prog_full,prog_empty,wr_rst_busy,rd_rst_busy";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2019.2";
+begin
+end;