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diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ip/xdma/xdma.veo b/projects/XUPVVH/XUPVVH.ip_user_files/ip/xdma/xdma.veo
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+// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:xdma:4.1
+// IP Revision: 4
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+xdma your_instance_name (
+  .sys_clk(sys_clk),                                    // input wire sys_clk
+  .sys_clk_gt(sys_clk_gt),                              // input wire sys_clk_gt
+  .sys_rst_n(sys_rst_n),                                // input wire sys_rst_n
+  .user_lnk_up(user_lnk_up),                            // output wire user_lnk_up
+  .pci_exp_txp(pci_exp_txp),                            // output wire [7 : 0] pci_exp_txp
+  .pci_exp_txn(pci_exp_txn),                            // output wire [7 : 0] pci_exp_txn
+  .pci_exp_rxp(pci_exp_rxp),                            // input wire [7 : 0] pci_exp_rxp
+  .pci_exp_rxn(pci_exp_rxn),                            // input wire [7 : 0] pci_exp_rxn
+  .axi_aclk(axi_aclk),                                  // output wire axi_aclk
+  .axi_aresetn(axi_aresetn),                            // output wire axi_aresetn
+  .usr_irq_req(usr_irq_req),                            // input wire [0 : 0] usr_irq_req
+  .usr_irq_ack(usr_irq_ack),                            // output wire [0 : 0] usr_irq_ack
+  .msi_enable(msi_enable),                              // output wire msi_enable
+  .msi_vector_width(msi_vector_width),                  // output wire [2 : 0] msi_vector_width
+  .cfg_mgmt_addr(cfg_mgmt_addr),                        // input wire [18 : 0] cfg_mgmt_addr
+  .cfg_mgmt_write(cfg_mgmt_write),                      // input wire cfg_mgmt_write
+  .cfg_mgmt_write_data(cfg_mgmt_write_data),            // input wire [31 : 0] cfg_mgmt_write_data
+  .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),          // input wire [3 : 0] cfg_mgmt_byte_enable
+  .cfg_mgmt_read(cfg_mgmt_read),                        // input wire cfg_mgmt_read
+  .cfg_mgmt_read_data(cfg_mgmt_read_data),              // output wire [31 : 0] cfg_mgmt_read_data
+  .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),  // output wire cfg_mgmt_read_write_done
+  .s_axis_c2h_tdata_0(s_axis_c2h_tdata_0),              // input wire [255 : 0] s_axis_c2h_tdata_0
+  .s_axis_c2h_tlast_0(s_axis_c2h_tlast_0),              // input wire s_axis_c2h_tlast_0
+  .s_axis_c2h_tvalid_0(s_axis_c2h_tvalid_0),            // input wire s_axis_c2h_tvalid_0
+  .s_axis_c2h_tready_0(s_axis_c2h_tready_0),            // output wire s_axis_c2h_tready_0
+  .s_axis_c2h_tkeep_0(s_axis_c2h_tkeep_0),              // input wire [31 : 0] s_axis_c2h_tkeep_0
+  .m_axis_h2c_tdata_0(m_axis_h2c_tdata_0),              // output wire [255 : 0] m_axis_h2c_tdata_0
+  .m_axis_h2c_tlast_0(m_axis_h2c_tlast_0),              // output wire m_axis_h2c_tlast_0
+  .m_axis_h2c_tvalid_0(m_axis_h2c_tvalid_0),            // output wire m_axis_h2c_tvalid_0
+  .m_axis_h2c_tready_0(m_axis_h2c_tready_0),            // input wire m_axis_h2c_tready_0
+  .m_axis_h2c_tkeep_0(m_axis_h2c_tkeep_0)              // output wire [31 : 0] m_axis_h2c_tkeep_0
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file xdma.v when simulating
+// the core, xdma. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ip/xdma/xdma.vho b/projects/XUPVVH/XUPVVH.ip_user_files/ip/xdma/xdma.vho
new file mode 100755
index 0000000..8d6a368
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/ip/xdma/xdma.vho
@@ -0,0 +1,135 @@
+-- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:xdma:4.1
+-- IP Revision: 4
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT xdma
+  PORT (
+    sys_clk : IN STD_LOGIC;
+    sys_clk_gt : IN STD_LOGIC;
+    sys_rst_n : IN STD_LOGIC;
+    user_lnk_up : OUT STD_LOGIC;
+    pci_exp_txp : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    pci_exp_txn : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    pci_exp_rxp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    pci_exp_rxn : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    axi_aclk : OUT STD_LOGIC;
+    axi_aresetn : OUT STD_LOGIC;
+    usr_irq_req : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    usr_irq_ack : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    msi_enable : OUT STD_LOGIC;
+    msi_vector_width : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+    cfg_mgmt_addr : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
+    cfg_mgmt_write : IN STD_LOGIC;
+    cfg_mgmt_write_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    cfg_mgmt_byte_enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    cfg_mgmt_read : IN STD_LOGIC;
+    cfg_mgmt_read_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    cfg_mgmt_read_write_done : OUT STD_LOGIC;
+    s_axis_c2h_tdata_0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
+    s_axis_c2h_tlast_0 : IN STD_LOGIC;
+    s_axis_c2h_tvalid_0 : IN STD_LOGIC;
+    s_axis_c2h_tready_0 : OUT STD_LOGIC;
+    s_axis_c2h_tkeep_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    m_axis_h2c_tdata_0 : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
+    m_axis_h2c_tlast_0 : OUT STD_LOGIC;
+    m_axis_h2c_tvalid_0 : OUT STD_LOGIC;
+    m_axis_h2c_tready_0 : IN STD_LOGIC;
+    m_axis_h2c_tkeep_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : xdma
+  PORT MAP (
+    sys_clk => sys_clk,
+    sys_clk_gt => sys_clk_gt,
+    sys_rst_n => sys_rst_n,
+    user_lnk_up => user_lnk_up,
+    pci_exp_txp => pci_exp_txp,
+    pci_exp_txn => pci_exp_txn,
+    pci_exp_rxp => pci_exp_rxp,
+    pci_exp_rxn => pci_exp_rxn,
+    axi_aclk => axi_aclk,
+    axi_aresetn => axi_aresetn,
+    usr_irq_req => usr_irq_req,
+    usr_irq_ack => usr_irq_ack,
+    msi_enable => msi_enable,
+    msi_vector_width => msi_vector_width,
+    cfg_mgmt_addr => cfg_mgmt_addr,
+    cfg_mgmt_write => cfg_mgmt_write,
+    cfg_mgmt_write_data => cfg_mgmt_write_data,
+    cfg_mgmt_byte_enable => cfg_mgmt_byte_enable,
+    cfg_mgmt_read => cfg_mgmt_read,
+    cfg_mgmt_read_data => cfg_mgmt_read_data,
+    cfg_mgmt_read_write_done => cfg_mgmt_read_write_done,
+    s_axis_c2h_tdata_0 => s_axis_c2h_tdata_0,
+    s_axis_c2h_tlast_0 => s_axis_c2h_tlast_0,
+    s_axis_c2h_tvalid_0 => s_axis_c2h_tvalid_0,
+    s_axis_c2h_tready_0 => s_axis_c2h_tready_0,
+    s_axis_c2h_tkeep_0 => s_axis_c2h_tkeep_0,
+    m_axis_h2c_tdata_0 => m_axis_h2c_tdata_0,
+    m_axis_h2c_tlast_0 => m_axis_h2c_tlast_0,
+    m_axis_h2c_tvalid_0 => m_axis_h2c_tvalid_0,
+    m_axis_h2c_tready_0 => m_axis_h2c_tready_0,
+    m_axis_h2c_tkeep_0 => m_axis_h2c_tkeep_0
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file xdma.vhd when simulating
+-- the core, xdma. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ip/xdma/xdma_stub.v b/projects/XUPVVH/XUPVVH.ip_user_files/ip/xdma/xdma_stub.v
new file mode 100644
index 0000000..4ed4c76
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/ip/xdma/xdma_stub.v
@@ -0,0 +1,56 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+// Date        : Sun Oct 18 14:34:24 2020
+// Host        : jalapeno running 64-bit Ubuntu 18.04.5 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.srcs/sources_1/ip/xdma/xdma_stub.v
+// Design      : xdma
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xcvu37p-fsvh2892-2-e
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "xdma_core_top,Vivado 2019.2" *)
+module xdma(sys_clk, sys_clk_gt, sys_rst_n, user_lnk_up, 
+  pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, axi_aclk, axi_aresetn, usr_irq_req, 
+  usr_irq_ack, msi_enable, msi_vector_width, cfg_mgmt_addr, cfg_mgmt_write, 
+  cfg_mgmt_write_data, cfg_mgmt_byte_enable, cfg_mgmt_read, cfg_mgmt_read_data, 
+  cfg_mgmt_read_write_done, s_axis_c2h_tdata_0, s_axis_c2h_tlast_0, s_axis_c2h_tvalid_0, 
+  s_axis_c2h_tready_0, s_axis_c2h_tkeep_0, m_axis_h2c_tdata_0, m_axis_h2c_tlast_0, 
+  m_axis_h2c_tvalid_0, m_axis_h2c_tready_0, m_axis_h2c_tkeep_0)
+/* synthesis syn_black_box black_box_pad_pin="sys_clk,sys_clk_gt,sys_rst_n,user_lnk_up,pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],axi_aclk,axi_aresetn,usr_irq_req[0:0],usr_irq_ack[0:0],msi_enable,msi_vector_width[2:0],cfg_mgmt_addr[18:0],cfg_mgmt_write,cfg_mgmt_write_data[31:0],cfg_mgmt_byte_enable[3:0],cfg_mgmt_read,cfg_mgmt_read_data[31:0],cfg_mgmt_read_write_done,s_axis_c2h_tdata_0[255:0],s_axis_c2h_tlast_0,s_axis_c2h_tvalid_0,s_axis_c2h_tready_0,s_axis_c2h_tkeep_0[31:0],m_axis_h2c_tdata_0[255:0],m_axis_h2c_tlast_0,m_axis_h2c_tvalid_0,m_axis_h2c_tready_0,m_axis_h2c_tkeep_0[31:0]" */;
+  input sys_clk;
+  input sys_clk_gt;
+  input sys_rst_n;
+  output user_lnk_up;
+  output [7:0]pci_exp_txp;
+  output [7:0]pci_exp_txn;
+  input [7:0]pci_exp_rxp;
+  input [7:0]pci_exp_rxn;
+  output axi_aclk;
+  output axi_aresetn;
+  input [0:0]usr_irq_req;
+  output [0:0]usr_irq_ack;
+  output msi_enable;
+  output [2:0]msi_vector_width;
+  input [18:0]cfg_mgmt_addr;
+  input cfg_mgmt_write;
+  input [31:0]cfg_mgmt_write_data;
+  input [3:0]cfg_mgmt_byte_enable;
+  input cfg_mgmt_read;
+  output [31:0]cfg_mgmt_read_data;
+  output cfg_mgmt_read_write_done;
+  input [255:0]s_axis_c2h_tdata_0;
+  input s_axis_c2h_tlast_0;
+  input s_axis_c2h_tvalid_0;
+  output s_axis_c2h_tready_0;
+  input [31:0]s_axis_c2h_tkeep_0;
+  output [255:0]m_axis_h2c_tdata_0;
+  output m_axis_h2c_tlast_0;
+  output m_axis_h2c_tvalid_0;
+  input m_axis_h2c_tready_0;
+  output [31:0]m_axis_h2c_tkeep_0;
+endmodule
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ip/xdma/xdma_stub.vhdl b/projects/XUPVVH/XUPVVH.ip_user_files/ip/xdma/xdma_stub.vhdl
new file mode 100644
index 0000000..6c1b234
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/ip/xdma/xdma_stub.vhdl
@@ -0,0 +1,60 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+-- Date        : Sun Oct 18 14:34:24 2020
+-- Host        : jalapeno running 64-bit Ubuntu 18.04.5 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.srcs/sources_1/ip/xdma/xdma_stub.vhdl
+-- Design      : xdma
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xcvu37p-fsvh2892-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity xdma is
+  Port ( 
+    sys_clk : in STD_LOGIC;
+    sys_clk_gt : in STD_LOGIC;
+    sys_rst_n : in STD_LOGIC;
+    user_lnk_up : out STD_LOGIC;
+    pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    axi_aclk : out STD_LOGIC;
+    axi_aresetn : out STD_LOGIC;
+    usr_irq_req : in STD_LOGIC_VECTOR ( 0 to 0 );
+    usr_irq_ack : out STD_LOGIC_VECTOR ( 0 to 0 );
+    msi_enable : out STD_LOGIC;
+    msi_vector_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    cfg_mgmt_addr : in STD_LOGIC_VECTOR ( 18 downto 0 );
+    cfg_mgmt_write : in STD_LOGIC;
+    cfg_mgmt_write_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    cfg_mgmt_byte_enable : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    cfg_mgmt_read : in STD_LOGIC;
+    cfg_mgmt_read_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    cfg_mgmt_read_write_done : out STD_LOGIC;
+    s_axis_c2h_tdata_0 : in STD_LOGIC_VECTOR ( 255 downto 0 );
+    s_axis_c2h_tlast_0 : in STD_LOGIC;
+    s_axis_c2h_tvalid_0 : in STD_LOGIC;
+    s_axis_c2h_tready_0 : out STD_LOGIC;
+    s_axis_c2h_tkeep_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    m_axis_h2c_tdata_0 : out STD_LOGIC_VECTOR ( 255 downto 0 );
+    m_axis_h2c_tlast_0 : out STD_LOGIC;
+    m_axis_h2c_tvalid_0 : out STD_LOGIC;
+    m_axis_h2c_tready_0 : in STD_LOGIC;
+    m_axis_h2c_tkeep_0 : out STD_LOGIC_VECTOR ( 31 downto 0 )
+  );
+
+end xdma;
+
+architecture stub of xdma is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "sys_clk,sys_clk_gt,sys_rst_n,user_lnk_up,pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],axi_aclk,axi_aresetn,usr_irq_req[0:0],usr_irq_ack[0:0],msi_enable,msi_vector_width[2:0],cfg_mgmt_addr[18:0],cfg_mgmt_write,cfg_mgmt_write_data[31:0],cfg_mgmt_byte_enable[3:0],cfg_mgmt_read,cfg_mgmt_read_data[31:0],cfg_mgmt_read_write_done,s_axis_c2h_tdata_0[255:0],s_axis_c2h_tlast_0,s_axis_c2h_tvalid_0,s_axis_c2h_tready_0,s_axis_c2h_tkeep_0[31:0],m_axis_h2c_tdata_0[255:0],m_axis_h2c_tlast_0,m_axis_h2c_tvalid_0,m_axis_h2c_tready_0,m_axis_h2c_tkeep_0[31:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "xdma_core_top,Vivado 2019.2";
+begin
+end;