Initial commit

5 files changed, 463 insertions, 0 deletions

diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/README.txt
new file mode 100644
index 0000000..13253af
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2019.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sun Oct 18 14:23:04 +03 2020
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./phy_ddr4.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './phy_ddr4.sh' script.
+
+./phy_ddr4.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./phy_ddr4.sh -noclean_files
+
+For more information on the script, please type './phy_ddr4.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/file_info.txt
new file mode 100644
index 0000000..0d9fc1a
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/file_info.txt
@@ -0,0 +1,61 @@
+xpm_cdc.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_fifo.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_memory.sv,systemverilog,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+microblaze_v11_0_vh_rfs.vhd,vhdl,microblaze_v11_0_2,../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_microblaze_I_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_rst_0_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lmb_v10_v3_0_vh_rfs.vhd,vhdl,lmb_v10_v3_0_10,../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_ilmb_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_dlmb_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,vhdl,lmb_bram_if_cntlr_v4_0_17,../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_dlmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_ilmb_cntlr_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_second_lmb_bram_I_0.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+iomodule_v3_1_vh_rfs.vhd,vhdl,iomodule_v3_1_5,../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c_iomodule_0_0.vhd,vhdl,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+bd_9f2c.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_microblaze_mcs.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_phy_v2_2_xiphy_behav.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
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+ddr4_v2_2_cal_top.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal_xsdb_arbiter.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_cal.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_chipscope_xsdb_slave.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+ddr4_v2_2_dp_AB9.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4_ddr4_cal_riu.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+phy_ddr4.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+microblaze_mcs_0.sv,systemverilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv,incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top"incdir="../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/glbl.v
new file mode 100644
index 0000000..be64233
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.sh
new file mode 100755
index 0000000..b4560e5
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/phy_ddr4.sh
@@ -0,0 +1,181 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.2 (64-bit)
+#
+# Filename    : phy_ddr4.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sun Oct 18 14:23:04 +03 2020
+# SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: phy_ddr4.sh [-help]
+# usage: phy_ddr4.sh [-lib_map_path]
+# usage: phy_ddr4.sh [-noclean_files]
+# usage: phy_ddr4.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'phy_ddr4.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xpm microblaze_v11_0_2 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lmb_v10_v3_0_10 lmb_bram_if_cntlr_v4_0_17 blk_mem_gen_v8_4_4 iomodule_v3_1_5)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "phy_ddr4.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.phy_ddr4 \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" \
+       +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" \
+       +incdir+"$ref_dir/../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal" \
+       +incdir+"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/map" \
+       +incdir+"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top" \
+       +incdir+"../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./phy_ddr4.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./phy_ddr4.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: phy_ddr4.sh [-help]\n\
+Usage: phy_ddr4.sh [-lib_map_path]\n\
+Usage: phy_ddr4.sh [-reset_run]\n\
+Usage: phy_ddr4.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/run.f b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/run.f
new file mode 100644
index 0000000..3f8a560
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/phy_ddr4/ies/run.f
@@ -0,0 +1,102 @@
+-makelib ies_lib/xpm -sv \
+  "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+  "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/microblaze_v11_0_2 \
+  "../../../ipstatic/hdl/microblaze_v11_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_0/sim/bd_9f2c_microblaze_I_0.vhd" \
+-endlib
+-makelib ies_lib/lib_cdc_v1_0_2 \
+  "../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
+-endlib
+-makelib ies_lib/proc_sys_reset_v5_0_13 \
+  "../../../ipstatic/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_1/sim/bd_9f2c_rst_0_0.vhd" \
+-endlib
+-makelib ies_lib/lmb_v10_v3_0_10 \
+  "../../../ipstatic/hdl/lmb_v10_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_2/sim/bd_9f2c_ilmb_0.vhd" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_3/sim/bd_9f2c_dlmb_0.vhd" \
+-endlib
+-makelib ies_lib/lmb_bram_if_cntlr_v4_0_17 \
+  "../../../ipstatic/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_4/sim/bd_9f2c_dlmb_cntlr_0.vhd" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_5/sim/bd_9f2c_ilmb_cntlr_0.vhd" \
+-endlib
+-makelib ies_lib/blk_mem_gen_v8_4_4 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_6/sim/bd_9f2c_lmb_bram_I_0.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_7/sim/bd_9f2c_second_dlmb_cntlr_0.vhd" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_8/sim/bd_9f2c_second_ilmb_cntlr_0.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_9/sim/bd_9f2c_second_lmb_bram_I_0.v" \
+-endlib
+-makelib ies_lib/iomodule_v3_1_5 \
+  "../../../ipstatic/hdl/iomodule_v3_1_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/ip/ip_10/sim/bd_9f2c_iomodule_0_0.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/bd_0/sim/bd_9f2c.v" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_0/sim/phy_ddr4_microblaze_mcs.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib -sv \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/phy_ddr4_phy_ddr4.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/ip_1/rtl/ip_top/phy_ddr4_phy.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/clocking/ddr4_v2_2_infrastructure.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_sync.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_read.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_pi.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_cplx.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_config_rom.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_top.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_dp_AB9.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4_ddr4.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/cal/phy_ddr4_ddr4_cal_riu.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/rtl/ip_top/phy_ddr4.sv" \
+  "../../../../XUPVVH.srcs/sources_1/ip/phy_ddr4/tb/microblaze_mcs_0.sv" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+