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diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/README.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/README.txt
new file mode 100644
index 0000000..5df63e8
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sun Oct 18 14:23:28 +03 2020
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./rdback_fifo.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './rdback_fifo.sh' script.
+
+./rdback_fifo.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./rdback_fifo.sh -noclean_files
+
+For more information on the script, please type './rdback_fifo.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/compile.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/compile.do
new file mode 100644
index 0000000..c05b1c0
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/compile.do
@@ -0,0 +1,34 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/fifo_generator_v13_2_5
+vlib questa_lib/msim/xil_defaultlib
+
+vmap xpm questa_lib/msim/xpm
+vmap fifo_generator_v13_2_5 questa_lib/msim/fifo_generator_v13_2_5
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+
+vlog -work xpm -64 -sv \
+"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
+"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work fifo_generator_v13_2_5 -64 \
+"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+
+vcom -work fifo_generator_v13_2_5 -64 -93 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+
+vlog -work fifo_generator_v13_2_5 -64 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+
+vlog -work xil_defaultlib -64 \
+"../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/elaborate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/elaborate.do
new file mode 100644
index 0000000..f2543ff
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 +acc -l elaborate.log -L xpm -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.rdback_fifo xil_defaultlib.glbl -o rdback_fifo_opt
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/file_info.txt b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/file_info.txt
new file mode 100644
index 0000000..211c17c
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/file_info.txt
@@ -0,0 +1,9 @@
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+rdback_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/glbl.v b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/glbl.v
new file mode 100644
index 0000000..be64233
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.sh b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.sh
new file mode 100755
index 0000000..fce92ef
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.sh
@@ -0,0 +1,174 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.2 (64-bit)
+#
+# Filename    : rdback_fifo.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Sun Oct 18 14:23:28 +03 2020
+# SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: rdback_fifo.sh [-help]
+# usage: rdback_fifo.sh [-lib_map_path]
+# usage: rdback_fifo.sh [-noclean_files]
+# usage: rdback_fifo.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'rdback_fifo.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.cache/compile_simlib/questa"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: rdback_fifo.sh [-help]\n\
+Usage: rdback_fifo.sh [-lib_map_path]\n\
+Usage: rdback_fifo.sh [-reset_run]\n\
+Usage: rdback_fifo.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.udo b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.udo
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/rdback_fifo.udo
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/simulate.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/simulate.do
new file mode 100644
index 0000000..1f469d6
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -t 1ps -lib xil_defaultlib rdback_fifo_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {rdback_fifo.udo}
+
+run -all
+
+quit -force
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/wave.do b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/questa/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR