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Diffstat (limited to 'projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim')
11 files changed, 426 insertions, 0 deletions
diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/README.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/README.txt new file mode 100644 index 0000000..6aedcac --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Mar 08 14:24:42 CET 2022 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rdback_fifo.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rdback_fifo.sh' script. + +./rdback_fifo.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rdback_fifo.sh -noclean_files + +For more information on the script, please type './rdback_fifo.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/U200.smi b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/U200.smi new file mode 100644 index 0000000..f20b0a8 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/U200.smi @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2020.2 (64-bit) --> +<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 --> +<!-- --> +<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --> +<!-- Nov 18 2020 --> +<!-- --> +<!-- This file is generated by the software with the Tcl write_mem_info command. --> +<!-- Do not edit this file. --> + +<MemInfoSimulation Version="1" Minor="1"> + <Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I"> + <AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303"> + <BusBlock> + <BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303"> + <DataWidth MSB="31" LSB="0"/> + <AddressRange Begin="0" End="16383"/> + <Parity ON="false" NumBits="0"/> + <MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/> + </BitLane> + </BusBlock> + </AddressSpace> + </Processor> + <Config> + <Option Name="Part" Val="xcu200-fsgd2104-2-e"/> + </Config> + <DRC> + <Rule Name="RDADDRCHANGE" Val="false"/> + </DRC> +</MemInfoSimulation> diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/cmd.tcl b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/file_info.txt b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/file_info.txt new file mode 100644 index 0000000..4ebc368 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/file_info.txt @@ -0,0 +1,2 @@ +rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/glbl.v b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_9f2c.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_9f2c.protoinst new file mode 100644 index 0000000..cf73fce --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_9f2c.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_9f2c": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_afa8.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_afa8.protoinst new file mode 100644 index 0000000..a0656b6 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_afa8.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_afa8": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_ba6a.protoinst b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_ba6a.protoinst new file mode 100644 index 0000000..c42e1c4 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/protoinst_files/bd_ba6a.protoinst @@ -0,0 +1,9 @@ +{ + "version": "1.0", + "modules": { + "bd_ba6a": { + "proto_instances": { + } + } + } +} diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/rdback_fifo.sh b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/rdback_fifo.sh new file mode 100755 index 0000000..199b134 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/rdback_fifo.sh @@ -0,0 +1,214 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : rdback_fifo.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Mar 08 14:24:42 CET 2022 +# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: rdback_fifo.sh [-help] +# usage: rdback_fifo.sh [-lib_map_path] +# usage: rdback_fifo.sh [-noclean_files] +# usage: rdback_fifo.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2020.2/tps/boost_1_64_0 +xvlog_opts="--relax -L xdma_v4_1_8" +xvhdl_opts="--relax" + + +# Script info +echo -e "rdback_fifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: <compile> +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: <elaborate> +elaborate() +{ + xelab --relax --debug typical --mt auto -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot rdback_fifo xil_defaultlib.rdback_fifo xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: <simulate> +simulate() +{ + xsim rdback_fifo -key {Behavioral:sim_1:Functional:rdback_fifo} -tclbatch cmd.tcl -protoinst "protoinst_files/bd_9f2c.protoinst" -protoinst "protoinst_files/bd_ba6a.protoinst" -protoinst "protoinst_files/bd_afa8.protoinst" -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # <user specific commands> + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2020.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb rdback_fifo.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rdback_fifo.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rdback_fifo.sh [-help]\n\ +Usage: rdback_fifo.sh [-lib_map_path]\n\ +Usage: rdback_fifo.sh [-reset_run]\n\ +Usage: rdback_fifo.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vhdl.prj b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vhdl.prj new file mode 100644 index 0000000..359cbd5 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vhdl.prj @@ -0,0 +1,2 @@ + +nosort diff --git a/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vlog.prj b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vlog.prj new file mode 100644 index 0000000..094bca5 --- /dev/null +++ b/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort |