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Diffstat (limited to 'projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter')
4 files changed, 257 insertions, 0 deletions
diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.veo b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.veo new file mode 100755 index 0000000..84a68ee --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.veo @@ -0,0 +1,78 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axis_clock_converter:1.1 +// IP Revision: 23 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axis_clock_converter your_instance_name ( + .s_axis_aresetn(s_axis_aresetn), // input wire s_axis_aresetn + .m_axis_aresetn(m_axis_aresetn), // input wire m_axis_aresetn + .s_axis_aclk(s_axis_aclk), // input wire s_axis_aclk + .s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid + .s_axis_tready(s_axis_tready), // output wire s_axis_tready + .s_axis_tdata(s_axis_tdata), // input wire [255 : 0] s_axis_tdata + .s_axis_tkeep(s_axis_tkeep), // input wire [31 : 0] s_axis_tkeep + .s_axis_tlast(s_axis_tlast), // input wire s_axis_tlast + .m_axis_aclk(m_axis_aclk), // input wire m_axis_aclk + .m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid + .m_axis_tready(m_axis_tready), // input wire m_axis_tready + .m_axis_tdata(m_axis_tdata), // output wire [255 : 0] m_axis_tdata + .m_axis_tkeep(m_axis_tkeep), // output wire [31 : 0] m_axis_tkeep + .m_axis_tlast(m_axis_tlast) // output wire m_axis_tlast +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axis_clock_converter.v when simulating +// the core, axis_clock_converter. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.vho b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.vho new file mode 100755 index 0000000..62fdd7b --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter.vho @@ -0,0 +1,101 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axis_clock_converter:1.1 +-- IP Revision: 23 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axis_clock_converter + PORT ( + s_axis_aresetn : IN STD_LOGIC; + m_axis_aresetn : IN STD_LOGIC; + s_axis_aclk : IN STD_LOGIC; + s_axis_tvalid : IN STD_LOGIC; + s_axis_tready : OUT STD_LOGIC; + s_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + s_axis_tkeep : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axis_tlast : IN STD_LOGIC; + m_axis_aclk : IN STD_LOGIC; + m_axis_tvalid : OUT STD_LOGIC; + m_axis_tready : IN STD_LOGIC; + m_axis_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + m_axis_tkeep : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_tlast : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axis_clock_converter + PORT MAP ( + s_axis_aresetn => s_axis_aresetn, + m_axis_aresetn => m_axis_aresetn, + s_axis_aclk => s_axis_aclk, + s_axis_tvalid => s_axis_tvalid, + s_axis_tready => s_axis_tready, + s_axis_tdata => s_axis_tdata, + s_axis_tkeep => s_axis_tkeep, + s_axis_tlast => s_axis_tlast, + m_axis_aclk => m_axis_aclk, + m_axis_tvalid => m_axis_tvalid, + m_axis_tready => m_axis_tready, + m_axis_tdata => m_axis_tdata, + m_axis_tkeep => m_axis_tkeep, + m_axis_tlast => m_axis_tlast + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axis_clock_converter.vhd when simulating +-- the core, axis_clock_converter. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.v b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.v new file mode 100644 index 0000000..b09eff7 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.v @@ -0,0 +1,35 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Fri Mar 31 17:35:06 2023 +// Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter_stub.v +// Design : axis_clock_converter +// Purpose : Stub declaration of top-level module interface +// Device : xcu50-fsvh2104-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "axis_clock_converter_v1_1_23_axis_clock_converter,Vivado 2020.2" *) +module axis_clock_converter(s_axis_aresetn, m_axis_aresetn, s_axis_aclk, + s_axis_tvalid, s_axis_tready, s_axis_tdata, s_axis_tkeep, s_axis_tlast, m_axis_aclk, + m_axis_tvalid, m_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tlast) +/* synthesis syn_black_box black_box_pad_pin="s_axis_aresetn,m_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[255:0],s_axis_tkeep[31:0],s_axis_tlast,m_axis_aclk,m_axis_tvalid,m_axis_tready,m_axis_tdata[255:0],m_axis_tkeep[31:0],m_axis_tlast" */; + input s_axis_aresetn; + input m_axis_aresetn; + input s_axis_aclk; + input s_axis_tvalid; + output s_axis_tready; + input [255:0]s_axis_tdata; + input [31:0]s_axis_tkeep; + input s_axis_tlast; + input m_axis_aclk; + output m_axis_tvalid; + input m_axis_tready; + output [255:0]m_axis_tdata; + output [31:0]m_axis_tkeep; + output m_axis_tlast; +endmodule diff --git a/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.vhdl b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.vhdl new file mode 100644 index 0000000..7b85852 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.ip_user_files/ip/axis_clock_converter/axis_clock_converter_stub.vhdl @@ -0,0 +1,43 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +-- Date : Fri Mar 31 17:35:06 2023 +-- Host : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/axis_clock_converter/axis_clock_converter_stub.vhdl +-- Design : axis_clock_converter +-- Purpose : Stub declaration of top-level module interface +-- Device : xcu50-fsvh2104-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity axis_clock_converter is + Port ( + s_axis_aresetn : in STD_LOGIC; + m_axis_aresetn : in STD_LOGIC; + s_axis_aclk : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); + s_axis_tkeep : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axis_tlast : in STD_LOGIC; + m_axis_aclk : in STD_LOGIC; + m_axis_tvalid : out STD_LOGIC; + m_axis_tready : in STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 ); + m_axis_tkeep : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axis_tlast : out STD_LOGIC + ); + +end axis_clock_converter; + +architecture stub of axis_clock_converter is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "s_axis_aresetn,m_axis_aresetn,s_axis_aclk,s_axis_tvalid,s_axis_tready,s_axis_tdata[255:0],s_axis_tkeep[31:0],s_axis_tlast,m_axis_aclk,m_axis_tvalid,m_axis_tready,m_axis_tdata[255:0],m_axis_tkeep[31:0],m_axis_tlast"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "axis_clock_converter_v1_1_23_axis_clock_converter,Vivado 2020.2"; +begin +end; |