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+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+// Date        : Fri Mar 31 17:33:10 2023
+// Host        : safari-aolgun0 running 64-bit Ubuntu 22.04.2 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.srcs/sources_1/ip/scratchpad/scratchpad_stub.v
+// Design      : scratchpad
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xcu50-fsvh2104-2-e
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *)
+module scratchpad(clka, ena, wea, addra, dina, douta)
+/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[31:0],douta[31:0]" */;
+  input clka;
+  input ena;
+  input [0:0]wea;
+  input [9:0]addra;
+  input [31:0]dina;
+  output [31:0]douta;
+endmodule