diff options
Diffstat (limited to 'projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/simulate.log')
| -rw-r--r-- | projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/simulate.log | 534 |
1 files changed, 534 insertions, 0 deletions
diff --git a/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/simulate.log b/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/simulate.log new file mode 100644 index 0000000..de1b833 --- /dev/null +++ b/projects/U50-HBM/U50-HBM.sim/sim_1/behav/questa/simulate.log @@ -0,0 +1,534 @@ +# // Questa Sim-64 +# // Version 2020.1 linux_x86_64 Jan 28 2020 +# // +# // Copyright 1991-2020 Mentor Graphics Corporation +# // All Rights Reserved. +# // +# // QuestaSim and its associated documentation contain trade +# // secrets and commercial or financial information that are the property of +# // Mentor Graphics Corporation and are privileged, confidential, +# // and exempt from disclosure under the Freedom of Information Act, +# // 5 U.S.C. Section 552. Furthermore, this information +# // is prohibited from disclosure under the Trade Secrets Act, +# // 18 U.S.C. Section 1905. +# // +# do {sim_tb_top_simulate.do} +# vsim "+notimingchecks" -onfinish final -lib xil_defaultlib sim_tb_top_opt +# Start time: 17:31:40 on Aug 31,2022 +# Loading work.sim_tb_top(fast) +# Loading work.softmc_top(fast) +# Loading work.HBM_adapter(fast) +# Loading work.cmd_gen(fast) +# Loading work.cmd_buf(fast) +# Loading work.controller_top(fast) +# Loading work.HBM_interface(fast) +# Loading sv_std.std +# Loading work.hbm_0(fast) +# Loading work.hbm_v1_0_9(fast) +# Loading unisims_ver.IBUF(fast) +# Loading unisims_ver.BUFG(fast) +# Loading hbm_v1_0_9.hbm_top(fast) +# Loading xpm.xpm_memory_spram(fast) +# Loading xpm.xpm_memory_base(fast) +# Loading hbm_v1_0_9.hbm_data_fetch(fast) +# Loading hbm_v1_0_9.hbm_apb_mst(fast) +# Loading hbm_v1_0_9.hbm_temp_rd(fast) +# Loading hbm_v1_0_9.hbm_apb_arbiter(fast) +# Loading xpm.xpm_memory_spram(fast__1) +# Loading xpm.xpm_memory_base(fast__1) +# Loading unisims_ver.HBM_TWO_STACK_INTF(fast) +# Loading secureip.SIP_HBM_TWO_STACK_INTF(fast) +# Loading secureip.xil_hbm_two_stack_intf_mod786(fast) +# Loading secureip.xil_hbm_two_stack_intf_mod1(fast) +# Loading secureip.xil_hbm_two_stack_intf_mod6(fast) +# Loading secureip.xil_hbm_two_stack_intf_mod2(fast) +# Loading secureip.xil_hbm_two_stack_intf_mod4(fast) +# Loading work.HBM(fast) +# Loading work.cdc_HBM_to_rbe(fast) +# Loading work.cdc_fifo(fast) +# Loading work.softmc_pipeline(fast) +# Loading work.fetch_stage(fast) +# Loading work.pre_decode(fast) +# Loading work.decode_stage(fast) +# Loading work.execute_stage(fast) +# Loading work.ddr_pipeline(fast) +# Loading work.exe_pipeline(fast) +# Loading work.scratchpad(fast) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4(fast) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_mem_module(fast) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_output_stage(fast) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_output_stage(fast__1) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_softecc_output_reg_stage(fast) +# Loading work.register_file(fast) +# Loading work.frontend(fast) +# Loading work.instr_blk_mem_sim(fast) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4(fast__1) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_mem_module(fast__1) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_output_stage(fast__2) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_output_stage(fast__3) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_softecc_output_reg_stage(fast__1) +# Loading work.maintenance_controller(fast) +# Loading work.pr_read_mem(fast) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4(fast__2) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_mem_module(fast__2) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_output_stage(fast__4) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_output_stage(fast__5) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_softecc_output_reg_stage(fast__2) +# Loading work.zq_calib_mem(fast) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4(fast__3) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_mem_module(fast__3) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_output_stage(fast__6) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_output_stage(fast__7) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_softecc_output_reg_stage(fast__3) +# Loading work.pr_ref_mem(fast) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4(fast__4) +# Loading blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4_mem_module(fast__4) +# Loading unisims_ver.IBUFDS_GTE4(fast) +# Loading work.readback_engine(fast) +# Loading work.pop_count4(fast) +# Loading work.diff_shift_reg(fast) +# Loading work.rdback_fifo(fast) +# Loading work.glbl(fast) +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.std_logic_arith(body) +# Loading ieee.std_logic_unsigned(body) +# Loading synopsys.attributes +# Loading ieee.std_logic_misc(body) +# Loading xpm.vcomponents +# Loading ieee.numeric_std(body) +# Loading ieee.vital_timing(body) +# Loading ieee.vital_primitives(body) +# Loading unisim.vpkg(body) +# Loading unisim.fifo36e2(fifo36e2_v)#2 +# Loading unisim.fifo36e2(fifo36e2_v)#3 +# Loading unisim.fifo36e2(fifo36e2_v)#4 +# Loading unisim.fifo36e2(fifo36e2_v)#1 +# ** Warning: (vsim-3015) [PCDPC] - Port size (10) does not match connection size (11) for port 'addra'. The port definition is at: ../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem_sim/sim/instr_blk_mem_sim.v(60). +# Time: 0 ps Iteration: 0 Instance: /sim_tb_top/UUT/frontend/genblk1/imem File: ../../../../../../sources/hdl/verilog/frontend.v Line: 60 +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>(10) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>(9) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>(8) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>(7) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>(6) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>(5) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>(4) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>(3) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>(2) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>(1) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>(0) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(35 downto 34). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(35 downto 34). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(53 downto 52). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(53 downto 52). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(71 downto 70). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(71 downto 70). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(89 downto 88). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(89 downto 88). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(107 downto 106). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(107 downto 106). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(125 downto 124). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(125 downto 124). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(143 downto 142). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(143 downto 142). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(161 downto 160). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(161 downto 160). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(179 downto 178). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(179 downto 178). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(197 downto 196). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(197 downto 196). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(215 downto 214). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(215 downto 214). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(233 downto 232). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(233 downto 232). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(251 downto 250). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(251 downto 250). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(269 downto 268). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(269 downto 268). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(287 downto 286). +# ** Warning: (vsim-8684) No drivers exist on out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(17 downto 16), and its initial value is not used. +# Therefore, simulation behavior may occur that is not in compliance with +# the VHDL standard as the initial values come from the base signal /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>(287 downto 286). +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>(9) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>(8) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>(7) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>(6) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>(5) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>(4) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>(3) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>(2) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>(1) has no driver. +# This port will contribute value (U) to the signal network. +# ** Warning: (vsim-8683) Uninitialized out port /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>(0) has no driver. +# This port will contribute value (U) to the signal network. +# 1 +# 1 +# .main_pane.wave.interior.cs.body.pw.wf +# .main_pane.structure.interior.cs.body.struct +# .main_pane.objects.interior.cs.body.tree +# ** Note: Actual FIFO Depth = 1025 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 1025 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 1025 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 1025 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 1025 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 1025 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 1025 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 1025 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 1025 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 1025 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 1025 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 1025 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 1025 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 1025 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 1025 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 1025 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: DEPTH = 1024 WIDTH = 36 C_RD_PRIM_WIDTH = 18 C_RD_PRIM_DEPTH = 2304 DEEP = 1 WIDE = 16 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/rbe/rbf/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 2055 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 2055 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 2055 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 2055 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 2055 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 2055 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 2055 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: Actual FIFO Depth = 2055 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# ** Note: DEPTH = 512 WIDTH = 72 C_RD_PRIM_WIDTH = 72 C_RD_PRIM_DEPTH = 512 DEEP = 4 WIDE = 8 +# Time: 0 ps Iteration: 0 Protected: /sim_tb_top/UUT/HBM_adapter/cdc_HBM/cdc_fifo0/inst/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> +# Block Memory Generator module sim_tb_top.UUT.pipeline.es.data_mem.inst.native_mem_module.blk_mem_gen_v8_4_4_inst is using a behavioral model for simulation which will not precisely model memory collision behavior. +# Block Memory Generator module loading initial data... +# Block Memory Generator data initialization complete. +# Block Memory Generator module sim_tb_top.UUT.frontend.genblk1.imem.inst.native_mem_module.blk_mem_gen_v8_4_4_inst is using a behavioral model for simulation which will not precisely model memory collision behavior. +# Block Memory Generator module loading initial data... +# Block Memory Generator data initialization complete. +# Block Memory Generator module sim_tb_top.UUT.frontend.maint_ctrl.prm.inst.native_mem_module.blk_mem_gen_v8_4_4_inst is using a behavioral model for simulation which will not precisely model memory collision behavior. +# Block Memory Generator module loading initial data... +# Block Memory Generator data initialization complete. +# Block Memory Generator module sim_tb_top.UUT.frontend.maint_ctrl.pzm.inst.native_mem_module.blk_mem_gen_v8_4_4_inst is using a behavioral model for simulation which will not precisely model memory collision behavior. +# Block Memory Generator module loading initial data... +# Block Memory Generator data initialization complete. +# Block Memory Generator module sim_tb_top.UUT.frontend.maint_ctrl.prefm.inst.native_mem_module.blk_mem_gen_v8_4_4_inst is using a behavioral model for simulation which will not precisely model memory collision behavior. +# HBM[CH_A] : Resetb is de-asserted at 0.0000 ns +# HBM[CH_B] : Resetb is de-asserted at 0.0000 ns +# HBM[CH_C] : Resetb is de-asserted at 0.0000 ns +# HBM[CH_D] : Resetb is de-asserted at 0.0000 ns +# HBM[CH_E] : Resetb is de-asserted at 0.0000 ns +# HBM[CH_F] : Resetb is de-asserted at 0.0000 ns +# HBM[CH_G] : Resetb is de-asserted at 0.0000 ns +# HBM[CH_H] : Resetb is de-asserted at 0.0000 ns +# HBM[CH_A] : Resetb is de-asserted at 0.0000 ns +# HBM[CH_B] : Resetb is de-asserted at 0.0000 ns +# HBM[CH_C] : Resetb is de-asserted at 0.0000 ns +# HBM[CH_D] : Resetb is de-asserted at 0.0000 ns +# HBM[CH_E] : Resetb is de-asserted at 0.0000 ns +# HBM[CH_F] : Resetb is de-asserted at 0.0000 ns +# HBM[CH_G] : Resetb is de-asserted at 0.0000 ns +# HBM[CH_H] : Resetb is de-asserted at 0.0000 ns +# ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.xpm_memory_spram_inst_0.xpm_memory_base_inst.config_drc +# Time: 1 ps Scope: sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.xpm_memory_spram_inst_0.xpm_memory_base_inst.config_drc File: /usr/pack/vitis-2020.2-kgf/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 488 +# ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.xpm_memory_spram_inst_1.xpm_memory_base_inst.config_drc +# Time: 1 ps Scope: sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.xpm_memory_spram_inst_1.xpm_memory_base_inst.config_drc File: /usr/pack/vitis-2020.2-kgf/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 488 +# ** Warning: (vsim-PLI-3408) Too few data words read on line 85 of file "xpm_internal_config_file_sim_0.mem". Expected 2048, found 84. : /usr/pack/vitis-2020.2-kgf/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv(1104) +# Time: 10 ps Iteration: 0 Instance: /sim_tb_top/UUT/HBM_adapter/ctrl_top/hbm_inst/inst/TWO_STACK/u_hbm_top/TWO_STACK_HBM/xpm_memory_spram_inst_0/xpm_memory_base_inst +# ** Warning: (vsim-PLI-3408) Too few data words read on line 63 of file "xpm_internal_config_file_sim_1.mem". Expected 2048, found 62. : /usr/pack/vitis-2020.2-kgf/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv(1104) +# Time: 10 ps Iteration: 0 Instance: /sim_tb_top/UUT/HBM_adapter/ctrl_top/hbm_inst/inst/TWO_STACK/u_hbm_top/TWO_STACK_HBM/xpm_memory_spram_inst_1/xpm_memory_base_inst +# HBM[CH_A] : Resetb is asserted at 0.0350 ns +# HBM[CH_B] : Resetb is asserted at 0.0350 ns +# HBM[CH_C] : Resetb is asserted at 0.0350 ns +# HBM[CH_D] : Resetb is asserted at 0.0350 ns +# HBM[CH_E] : Resetb is asserted at 0.0350 ns +# HBM[CH_F] : Resetb is asserted at 0.0350 ns +# HBM[CH_G] : Resetb is asserted at 0.0350 ns +# HBM[CH_H] : Resetb is asserted at 0.0350 ns +# HBM[CH_A] : Resetb is asserted at 0.0350 ns +# HBM[CH_B] : Resetb is asserted at 0.0350 ns +# HBM[CH_C] : Resetb is asserted at 0.0350 ns +# HBM[CH_D] : Resetb is asserted at 0.0350 ns +# HBM[CH_E] : Resetb is asserted at 0.0350 ns +# HBM[CH_F] : Resetb is asserted at 0.0350 ns +# HBM[CH_G] : Resetb is asserted at 0.0350 ns +# HBM[CH_H] : Resetb is asserted at 0.0350 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHa.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHa.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHa.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHa.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHa.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHa.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHa.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHa.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHb.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHb.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHb.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHb.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHb.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHb.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHb.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHb.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHc.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHc.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHc.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHc.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHc.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHc.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHc.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHc.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHd.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHd.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHd.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHd.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHd.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHd.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHd.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHd.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHe.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHe.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHe.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHe.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHe.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHe.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHe.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHe.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHf.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHf.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHf.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHf.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHf.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHf.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHf.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHf.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHg.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHg.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHg.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHg.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHg.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHg.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHg.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHg.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHh.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHh.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHh.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHh.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHh.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHh.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHh.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHh.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHa.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHa.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHa.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHa.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHa.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHa.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHa.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHa.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHb.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHb.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHb.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHb.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHb.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHb.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHb.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHb.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHc.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHc.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHc.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHc.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHc.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHc.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHc.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHc.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHd.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHd.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHd.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHd.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHd.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHd.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHd.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHd.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHe.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHe.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHe.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHe.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHe.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHe.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHe.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHe.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHf.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHf.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHf.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHf.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHf.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHf.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHf.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHf.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHg.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHg.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHg.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHg.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHg.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHg.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHg.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHg.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHh.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHh.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHh.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHh.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHh.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHh.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHh.<protected>.<protected>.<protected> at 0.0000 ns +# Warning: Set Value for EMASA doesn't match Default value 1 in sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHh.<protected>.<protected>.<protected> at 0.0000 ns +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHa.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHa.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHb.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHb.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHc.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHc.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHd.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHd.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHe.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHe.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHf.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHf.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHg.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHg.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHh.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_RT.MC_CHh.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHa.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHa.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHb.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHb.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHc.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHc.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHd.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHd.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHe.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHe.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHf.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHf.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHg.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHg.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHh.<protected>.<protected>.<protected> RMW Assertion checking active +# sim_tb_top.UUT.HBM_adapter.ctrl_top.hbm_inst.inst.TWO_STACK.u_hbm_top.TWO_STACK_HBM.hbm_two_stack_intf.SIP_HBM_TWO_STACK_INTF_INST.HBM_DMAH_CORE.HBM_SC_LT.MC_CHh.<protected>.<protected>.<protected> RMW Assertion checking active +# HBM[CH_A] : Resetb is de-asserted at 25245.0280 ns +# HBM[CH_B] : Resetb is de-asserted at 25245.0280 ns +# HBM[CH_C] : Resetb is de-asserted at 25245.0280 ns +# HBM[CH_D] : Resetb is de-asserted at 25245.0280 ns +# HBM[CH_E] : Resetb is de-asserted at 25245.0280 ns +# HBM[CH_F] : Resetb is de-asserted at 25245.0280 ns +# HBM[CH_G] : Resetb is de-asserted at 25245.0280 ns +# HBM[CH_H] : Resetb is de-asserted at 25245.0280 ns +# HBM[CH_A] : Resetb is de-asserted at 25245.0280 ns +# HBM[CH_B] : Resetb is de-asserted at 25245.0280 ns +# HBM[CH_C] : Resetb is de-asserted at 25245.0280 ns +# HBM[CH_D] : Resetb is de-asserted at 25245.0280 ns +# HBM[CH_E] : Resetb is de-asserted at 25245.0280 ns +# HBM[CH_F] : Resetb is de-asserted at 25245.0280 ns +# HBM[CH_G] : Resetb is de-asserted at 25245.0280 ns +# HBM[CH_H] : Resetb is de-asserted at 25245.0280 ns +add wave -position insertpoint sim:/sim_tb_top/UUT/rbe/* |