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-rw-r--r--projects/U50-HBM/U50-HBM.xpr1185
1 files changed, 1185 insertions, 0 deletions
diff --git a/projects/U50-HBM/U50-HBM.xpr b/projects/U50-HBM/U50-HBM.xpr
new file mode 100644
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--- /dev/null
+++ b/projects/U50-HBM/U50-HBM.xpr
@@ -0,0 +1,1185 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
+
+<Project Version="7" Minor="54" Path="/home/ataberk/DRAM-Bender/gitlab/projects/U50-HBM/U50-HBM.xpr">
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <Configuration>
+ <Option Name="Id" Val="7a04b544d02540f198bf2850743bcf39"/>
+ <Option Name="Part" Val="xcu50-fsvh2104-2-e"/>
+ <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+ <Option Name="CompiledLibDirXSim" Val=""/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+ <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+ <Option Name="SimulatorInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorInstallDirIES" Val=""/>
+ <Option Name="SimulatorInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorInstallDirVCS" Val=""/>
+ <Option Name="SimulatorInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorGccInstallDirIES" Val=""/>
+ <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+ <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+ <Option Name="TargetSimulator" Val="Questa"/>
+ <Option Name="BoardPart" Val="xilinx.com:au50:part0:1.3"/>
+ <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="DefaultLib" Val="xil_defaultlib"/>
+ <Option Name="ProjectType" Val="Default"/>
+ <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+ <Option Name="IPCachePermission" Val="read"/>
+ <Option Name="IPCachePermission" Val="write"/>
+ <Option Name="EnableCoreContainer" Val="FALSE"/>
+ <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+ <Option Name="EnableBDX" Val="FALSE"/>
+ <Option Name="DSABoardId" Val="au50lv"/>
+ <Option Name="WTXSimLaunchSim" Val="0"/>
+ <Option Name="WTModelSimLaunchSim" Val="0"/>
+ <Option Name="WTQuestaLaunchSim" Val="14"/>
+ <Option Name="WTIesLaunchSim" Val="0"/>
+ <Option Name="WTVcsLaunchSim" Val="0"/>
+ <Option Name="WTRivieraLaunchSim" Val="0"/>
+ <Option Name="WTActivehdlLaunchSim" Val="0"/>
+ <Option Name="WTXSimExportSim" Val="114"/>
+ <Option Name="WTModelSimExportSim" Val="114"/>
+ <Option Name="WTQuestaExportSim" Val="114"/>
+ <Option Name="WTIesExportSim" Val="114"/>
+ <Option Name="WTVcsExportSim" Val="113"/>
+ <Option Name="WTRivieraExportSim" Val="113"/>
+ <Option Name="WTActivehdlExportSim" Val="113"/>
+ <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+ <Option Name="XSimRadix" Val="hex"/>
+ <Option Name="XSimTimeUnit" Val="ns"/>
+ <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+ <Option Name="XSimTraceLimit" Val="65536"/>
+ <Option Name="SimTypes" Val="rtl"/>
+ <Option Name="SimTypes" Val="bfm"/>
+ <Option Name="SimTypes" Val="tlm"/>
+ <Option Name="SimTypes" Val="tlm_dpi"/>
+ <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+ <Option Name="DcpsUptoDate" Val="TRUE"/>
+ </Configuration>
+ <FileSets Version="1" Minor="31">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/verilog/project.vh">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/header_verilog/parameters.vh">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/verilog/HBM_adapter.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/verilog/HBM_interface.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/verilog/cdc_HBM_to_rbe.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/verilog/channel_selector.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/verilog/cmd_gen.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/verilog/controller_top.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/header_verilog/encoding.vh">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/verilog/ddr_pipeline.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/verilog/decode_stage.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/verilog/diff_shift_reg.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/verilog/exe_pipeline.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/verilog/execute_stage.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/verilog/fetch_stage.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/verilog/frontend.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/verilog/maintenance_controller.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/verilog/pop_count4.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/verilog/pre_decode.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/verilog/readback_engine.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/verilog/register_file.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/verilog/softmc_pipeline.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/verilog/softmc_top.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/ip/c_counter_binary_0/c_counter_binary_0.xci">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="ImportPath" Val="$PPRDIR/../../../../Downloads/DRAM-Bender/projects/XUPVVH/XUPVVH.srcs/sources_1/ip/c_counter_binary_0/c_counter_binary_0.xci"/>
+ <Attr Name="ImportTime" Val="1662709773"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
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+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/coe/program.coe">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/coe/read.coe">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/coe/zq.coe">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/coe/ref.coe">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
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+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="softmc_top"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/constraints/HBM.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TargetConstrsFile" Val="$PPRDIR/constraints/HBM.xdc"/>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PSRCDIR/sim_1/new/sim_tb_top.v">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../../../../Downloads/DRAM-Bender/projects/XUPVVH/XUPVVH.srcs/sim_1/new/sim_tb_top.v"/>
+ <Attr Name="ImportTime" Val="1663186096"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/sim_verilog/tb_decode_stage.v">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
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+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/sim_verilog/tb_softmc_top.v">
+ <FileInfo>
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+ <Attr Name="UsedIn" Val="synthesis"/>
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+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../sources/hdl/sim_verilog/tb_frontend.v">
+ <FileInfo>
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+ <Attr Name="UsedIn" Val="synthesis"/>
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+ </FileInfo>
+ </File>
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+ <FileInfo>
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+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="sim_tb_top"/>
+ <Option Name="TopLib" Val="xil_defaultlib"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ <Option Name="TransportPathDelay" Val="0"/>
+ <Option Name="TransportIntDelay" Val="0"/>
+ <Option Name="SelectedSimModel" Val="rtl"/>
+ <Option Name="PamDesignTestbench" Val=""/>
+ <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+ <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+ <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ <Option Name="questa.compile.vlog.more_options" Val="+notimingchecks"/>
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+ <Option Name="questa.simulate.log_all_signals" Val="true"/>
+ <Option Name="questa.simulate.vsim.more_options" Val="+notimingchecks -onfinish final"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="scratchpad" Type="BlockSrcs" RelSrcDir="$PSRCDIR/scratchpad">
+ <File Path="$PSRCDIR/sources_1/ip/scratchpad/scratchpad.xci">
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+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopModule" Val="scratchpad"/>
+ <Option Name="UseBlackboxStub" Val="1"/>
+ </Config>
+ </FileSet>
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+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../../../../Downloads/DRAM-Bender/projects/XUPVVH/XUPVVH.srcs/sources_1/ip/pr_read_mem/pr_read_mem.xci"/>
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+ </File>
+ <Config>
+ <Option Name="TopModule" Val="pr_read_mem"/>
+ <Option Name="UseBlackboxStub" Val="1"/>
+ </Config>
+ </FileSet>
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+ <Attr Name="ImportPath" Val="$PPRDIR/../../../../Downloads/DRAM-Bender/projects/XUPVVH/XUPVVH.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem.xci"/>
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+ </File>
+ <Config>
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+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="axis_clock_converter_impl_1" Type="Ft2:EntireDesign" Part="xcu50-fsvh2104-2-e" ConstrsSet="axis_clock_converter" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axis_clock_converter_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_clock_converter_impl_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="cmd_fifo_impl_1" Type="Ft2:EntireDesign" Part="xcu50-fsvh2104-2-e" ConstrsSet="cmd_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cmd_fifo_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmd_fifo_impl_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="wrdata_fifo_impl_1" Type="Ft2:EntireDesign" Part="xcu50-fsvh2104-2-e" ConstrsSet="wrdata_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="wrdata_fifo_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/wrdata_fifo_impl_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="instr_blk_mem_sim_impl_1" Type="Ft2:EntireDesign" Part="xcu50-fsvh2104-2-e" ConstrsSet="instr_blk_mem_sim" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="instr_blk_mem_sim_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/instr_blk_mem_sim_impl_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="hbm_0_impl_1" Type="Ft2:EntireDesign" Part="xcu50-fsvh2104-2-e" ConstrsSet="hbm_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hbm_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hbm_0_impl_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="clk_wiz_0_impl_1" Type="Ft2:EntireDesign" Part="xcu50-fsvh2104-2-e" ConstrsSet="clk_wiz_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_wiz_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/clk_wiz_0_impl_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ </Runs>
+ <MsgRule>
+ <MsgAttr Name="RuleType" Val="0"/>
+ <MsgAttr Name="Limit" Val="-1"/>
+ <MsgAttr Name="NewSeverity" Val="ANY"/>
+ <MsgAttr Name="Id" Val="[BD 41-1306]"/>
+ <MsgAttr Name="Severity" Val="ANY"/>
+ <MsgAttr Name="ShowRule" Val="1"/>
+ <MsgAttr Name="RuleSource" Val="2"/>
+ <MsgAttr Name="StringIsRegExp" Val="0"/>
+ <MsgAttr Name="RuleId" Val="1"/>
+ <MsgAttr Name="Note" Val=""/>
+ <MsgAttr Name="Author" Val=""/>
+ <MsgAttr Name="CreatedTimestamp" Val=""/>
+ </MsgRule>
+ <MsgRule>
+ <MsgAttr Name="RuleType" Val="0"/>
+ <MsgAttr Name="Limit" Val="-1"/>
+ <MsgAttr Name="NewSeverity" Val="ANY"/>
+ <MsgAttr Name="Id" Val="[BD 41-1271]"/>
+ <MsgAttr Name="Severity" Val="ANY"/>
+ <MsgAttr Name="ShowRule" Val="1"/>
+ <MsgAttr Name="RuleSource" Val="2"/>
+ <MsgAttr Name="StringIsRegExp" Val="0"/>
+ <MsgAttr Name="RuleId" Val="10"/>
+ <MsgAttr Name="Note" Val=""/>
+ <MsgAttr Name="Author" Val=""/>
+ <MsgAttr Name="CreatedTimestamp" Val=""/>
+ </MsgRule>
+ <MsgRule>
+ <MsgAttr Name="RuleType" Val="0"/>
+ <MsgAttr Name="Limit" Val="-1"/>
+ <MsgAttr Name="NewSeverity" Val="ANY"/>
+ <MsgAttr Name="Id" Val="[BD 41-1306]"/>
+ <MsgAttr Name="Severity" Val="ANY"/>
+ <MsgAttr Name="ShowRule" Val="1"/>
+ <MsgAttr Name="RuleSource" Val="2"/>
+ <MsgAttr Name="StringIsRegExp" Val="0"/>
+ <MsgAttr Name="RuleId" Val="13"/>
+ <MsgAttr Name="Note" Val=""/>
+ <MsgAttr Name="Author" Val=""/>
+ <MsgAttr Name="CreatedTimestamp" Val=""/>
+ </MsgRule>
+ <MsgRule>
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+ <MsgAttr Name="Limit" Val="-1"/>
+ <MsgAttr Name="NewSeverity" Val="ANY"/>
+ <MsgAttr Name="Id" Val="[BD 41-1271]"/>
+ <MsgAttr Name="Severity" Val="ANY"/>
+ <MsgAttr Name="ShowRule" Val="1"/>
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+ <MsgAttr Name="StringIsRegExp" Val="0"/>
+ <MsgAttr Name="RuleId" Val="14"/>
+ <MsgAttr Name="Note" Val=""/>
+ <MsgAttr Name="Author" Val=""/>
+ <MsgAttr Name="CreatedTimestamp" Val=""/>
+ </MsgRule>
+ <MsgRule>
+ <MsgAttr Name="RuleType" Val="0"/>
+ <MsgAttr Name="Limit" Val="-1"/>
+ <MsgAttr Name="NewSeverity" Val="ANY"/>
+ <MsgAttr Name="Id" Val="[BD 41-1271]"/>
+ <MsgAttr Name="Severity" Val="ANY"/>
+ <MsgAttr Name="ShowRule" Val="1"/>
+ <MsgAttr Name="RuleSource" Val="2"/>
+ <MsgAttr Name="StringIsRegExp" Val="0"/>
+ <MsgAttr Name="RuleId" Val="2"/>
+ <MsgAttr Name="Note" Val=""/>
+ <MsgAttr Name="Author" Val=""/>
+ <MsgAttr Name="CreatedTimestamp" Val=""/>
+ </MsgRule>
+ <MsgRule>
+ <MsgAttr Name="RuleType" Val="0"/>
+ <MsgAttr Name="Limit" Val="-1"/>
+ <MsgAttr Name="NewSeverity" Val="ANY"/>
+ <MsgAttr Name="Id" Val="[BD 41-1306]"/>
+ <MsgAttr Name="Severity" Val="ANY"/>
+ <MsgAttr Name="ShowRule" Val="1"/>
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+ <MsgAttr Name="StringIsRegExp" Val="0"/>
+ <MsgAttr Name="RuleId" Val="3"/>
+ <MsgAttr Name="Note" Val=""/>
+ <MsgAttr Name="Author" Val=""/>
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+ <MsgRule>
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+ <MsgRule>
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+ <MsgAttr Name="Severity" Val="ANY"/>
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+ <MsgAttr Name="RuleId" Val="5"/>
+ <MsgAttr Name="Note" Val=""/>
+ <MsgAttr Name="Author" Val=""/>
+ <MsgAttr Name="CreatedTimestamp" Val=""/>
+ </MsgRule>
+ <MsgRule>
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+ <MsgAttr Name="Limit" Val="-1"/>
+ <MsgAttr Name="NewSeverity" Val="ANY"/>
+ <MsgAttr Name="Id" Val="[BD 41-1271]"/>
+ <MsgAttr Name="Severity" Val="ANY"/>
+ <MsgAttr Name="ShowRule" Val="1"/>
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+ <MsgAttr Name="StringIsRegExp" Val="0"/>
+ <MsgAttr Name="RuleId" Val="6"/>
+ <MsgAttr Name="Note" Val=""/>
+ <MsgAttr Name="Author" Val=""/>
+ <MsgAttr Name="CreatedTimestamp" Val=""/>
+ </MsgRule>
+ <MsgRule>
+ <MsgAttr Name="RuleType" Val="0"/>
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+ <MsgAttr Name="NewSeverity" Val="ANY"/>
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+ <MsgAttr Name="Severity" Val="ANY"/>
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+ <MsgAttr Name="StringIsRegExp" Val="0"/>
+ <MsgAttr Name="RuleId" Val="7"/>
+ <MsgAttr Name="Note" Val=""/>
+ <MsgAttr Name="Author" Val=""/>
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+ </MsgRule>
+ <MsgRule>
+ <MsgAttr Name="RuleType" Val="0"/>
+ <MsgAttr Name="Limit" Val="-1"/>
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+ <MsgAttr Name="Id" Val="[BD 41-1271]"/>
+ <MsgAttr Name="Severity" Val="ANY"/>
+ <MsgAttr Name="ShowRule" Val="1"/>
+ <MsgAttr Name="RuleSource" Val="2"/>
+ <MsgAttr Name="StringIsRegExp" Val="0"/>
+ <MsgAttr Name="RuleId" Val="8"/>
+ <MsgAttr Name="Note" Val=""/>
+ <MsgAttr Name="Author" Val=""/>
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+ </MsgRule>
+ <MsgRule>
+ <MsgAttr Name="RuleType" Val="0"/>
+ <MsgAttr Name="Limit" Val="-1"/>
+ <MsgAttr Name="NewSeverity" Val="ANY"/>
+ <MsgAttr Name="Id" Val="[BD 41-1306]"/>
+ <MsgAttr Name="Severity" Val="ANY"/>
+ <MsgAttr Name="ShowRule" Val="1"/>
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+ <MsgAttr Name="StringIsRegExp" Val="0"/>
+ <MsgAttr Name="RuleId" Val="9"/>
+ <MsgAttr Name="Note" Val=""/>
+ <MsgAttr Name="Author" Val=""/>
+ <MsgAttr Name="CreatedTimestamp" Val=""/>
+ </MsgRule>
+ <Board>
+ <Jumpers/>
+ </Board>
+ <DashboardSummary Version="1" Minor="0">
+ <Dashboards>
+ <Dashboard Name="default_dashboard">
+ <Gadgets>
+ <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+ </Gadget>
+ <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+ </Gadget>
+ <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+ </Gadget>
+ <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+ </Gadget>
+ <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+ <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+ <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+ </Gadget>
+ <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+ </Gadget>
+ </Gadgets>
+ </Dashboard>
+ <CurrentDashboard>default_dashboard</CurrentDashboard>
+ </Dashboards>
+ </DashboardSummary>
+</Project>