diff options
Diffstat (limited to 'projects/VU095/VU095.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml')
| -rw-r--r-- | projects/VU095/VU095.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml | 8556 |
1 files changed, 8556 insertions, 0 deletions
diff --git a/projects/VU095/VU095.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml b/projects/VU095/VU095.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml new file mode 100644 index 0000000..953948e --- /dev/null +++ b/projects/VU095/VU095.srcs/sources_1/ip/phy_ddr4/phy_ddr4.xml @@ -0,0 +1,8556 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>customized_ip</spirit:library> + <spirit:name>phy_ddr4</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>C0_SYS_CLK</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/> + <spirit:slave/> + <spirit:connectionRequired>true</spirit:connectionRequired> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>CLK_N</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>c0_sys_clk_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>CLK_P</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>c0_sys_clk_p</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name> + <spirit:value spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK.BOARD.ASSOCIATED_PARAM">C0_CLOCK_BOARD_INTERFACE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CAN_DEBUG</spirit:name> + <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.C0_SYS_CLK.CAN_DEBUG">false</spirit:value> + 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<spirit:name>C0_DDR4</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddr4" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ddr4_rtl" spirit:version="1.0"/> + <spirit:master/> + <spirit:connectionRequired>true</spirit:connectionRequired> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>ACT_N</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>c0_ddr4_act_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>ADR</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>c0_ddr4_adr</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>BA</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>c0_ddr4_ba</spirit:name> + </spirit:physicalPort> + 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<xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_app_wdf_wren" xilinx:dependency="( ( spirit:decode(id('MODELPARAM_VALUE.C0.ControllerType')) = "DDR4_SDRAM" ) and ( spirit:decode(id('PARAM_VALUE.C0.DDR4_AxiSelection')) = false ) and ( spirit:decode(id('PARAM_VALUE.Phy_Only')) = "Complete_Memory_Controller" ) )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>c0_ddr4_app_correct_en_i</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_app_correct_en_i" xilinx:dependency="( ( spirit:decode(id('MODELPARAM_VALUE.C0.ControllerType')) = "DDR4_SDRAM" ) and ( spirit:decode(id('PARAM_VALUE.C0.DDR4_AxiSelection')) = false ) and ( spirit:decode(id('PARAM_VALUE.C0.DDR4_ECC')) = true()() ))">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>c0_ddr4_app_rd_data_end</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_app_rd_data_end" xilinx:dependency="( ( spirit:decode(id('MODELPARAM_VALUE.C0.ControllerType')) = "DDR4_SDRAM" ) and ( spirit:decode(id('PARAM_VALUE.C0.DDR4_AxiSelection')) = false ) and ( spirit:decode(id('PARAM_VALUE.Phy_Only')) = "Complete_Memory_Controller" ) )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>c0_ddr4_app_rd_data_valid</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_app_rd_data_valid" xilinx:dependency="( ( spirit:decode(id('MODELPARAM_VALUE.C0.ControllerType')) = "DDR4_SDRAM" ) and ( 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"Complete_Memory_Controller" ) )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>c0_ddr4_app_wdf_rdy</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_app_wdf_rdy" xilinx:dependency="( ( spirit:decode(id('MODELPARAM_VALUE.C0.ControllerType')) = "DDR4_SDRAM" ) and ( spirit:decode(id('PARAM_VALUE.C0.DDR4_AxiSelection')) = false ) and ( spirit:decode(id('PARAM_VALUE.Phy_Only')) = "Complete_Memory_Controller" ) )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + 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spirit:decode(id('PARAM_VALUE.C0.DDR4_UserRefresh_ZQCS')) = true )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>c0_ddr4_app_autoprecharge</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_app_autoprecharge" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.C0.DDR4_AutoPrecharge')) = true )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + 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<spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_s_axi_arprot" xilinx:dependency="( spirit:decode(id('MODELPARAM_VALUE.C0.ControllerType')) = "DDR4_SDRAM" ) and ( spirit:decode(id('PARAM_VALUE.C0.DDR4_AxiSelection')) = true() )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>c0_ddr4_s_axi_arqos</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">3</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_s_axi_arqos" xilinx:dependency="( spirit:decode(id('MODELPARAM_VALUE.C0.ControllerType')) = "DDR4_SDRAM" ) and ( spirit:decode(id('PARAM_VALUE.C0.DDR4_AxiSelection')) = true() )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>c0_ddr4_s_axi_arvalid</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_s_axi_arvalid" xilinx:dependency="( spirit:decode(id('MODELPARAM_VALUE.C0.ControllerType')) = "DDR4_SDRAM" ) and ( spirit:decode(id('PARAM_VALUE.C0.DDR4_AxiSelection')) = true() )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>c0_ddr4_s_axi_arready</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_s_axi_arready" xilinx:dependency="( spirit:decode(id('MODELPARAM_VALUE.C0.ControllerType')) = "DDR4_SDRAM" ) and ( spirit:decode(id('PARAM_VALUE.C0.DDR4_AxiSelection')) = true() )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>c0_ddr4_s_axi_rready</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_s_axi_rready" xilinx:dependency="( spirit:decode(id('MODELPARAM_VALUE.C0.ControllerType')) = "DDR4_SDRAM" ) and ( spirit:decode(id('PARAM_VALUE.C0.DDR4_AxiSelection')) = true() )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>c0_ddr4_s_axi_rlast</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_s_axi_rlast" xilinx:dependency="( spirit:decode(id('MODELPARAM_VALUE.C0.ControllerType')) = "DDR4_SDRAM" ) and ( spirit:decode(id('PARAM_VALUE.C0.DDR4_AxiSelection')) = true() )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>c0_ddr4_s_axi_rvalid</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_s_axi_rvalid" xilinx:dependency="( spirit:decode(id('MODELPARAM_VALUE.C0.ControllerType')) = "DDR4_SDRAM" ) and ( spirit:decode(id('PARAM_VALUE.C0.DDR4_AxiSelection')) = true() )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>c0_ddr4_s_axi_rresp</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">1</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_s_axi_rresp" xilinx:dependency="( spirit:decode(id('MODELPARAM_VALUE.C0.ControllerType')) = "DDR4_SDRAM" ) and ( spirit:decode(id('PARAM_VALUE.C0.DDR4_AxiSelection')) = true() )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>c0_ddr4_s_axi_rid</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C0.DDR4_AXI_ID_WIDTH')))-1">3</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_s_axi_rid" xilinx:dependency="( spirit:decode(id('MODELPARAM_VALUE.C0.ControllerType')) = "DDR4_SDRAM" ) and ( spirit:decode(id('PARAM_VALUE.C0.DDR4_AxiSelection')) = true() )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>c0_ddr4_s_axi_rdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C0.DDR4_AXI_DATA_WIDTH')))-1">63</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_s_axi_rdata" xilinx:dependency="( spirit:decode(id('MODELPARAM_VALUE.C0.ControllerType')) = "DDR4_SDRAM" ) and ( spirit:decode(id('PARAM_VALUE.C0.DDR4_AxiSelection')) = true() )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>traffic_error</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="2*spirit:decode(id('MODELPARAM_VALUE.C0.DDR4_nCK_PER_CLK'))*spirit:decode(id('MODELPARAM_VALUE.C0.DDR4_DQ_WIDTH'))-1">511</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.traffic_error" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>traffic_wr_done</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.traffic_wr_done" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>traffic_status_err_bit_valid</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.traffic_status_err_bit_valid" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>traffic_status_err_type_valid</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.traffic_status_err_type_valid" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>traffic_status_err_type</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.traffic_status_err_type" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>traffic_status_done</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.traffic_status_done" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>traffic_status_watch_dog_hang</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.traffic_status_watch_dog_hang" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>win_start</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">3</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.win_start" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>traffic_clr_error</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.traffic_clr_error" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>traffic_start</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.traffic_start" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>traffic_rst</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.traffic_rst" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>traffic_err_chk_en</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.traffic_err_chk_en" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>traffic_instr_addr_mode</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">3</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.traffic_instr_addr_mode" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>traffic_instr_data_mode</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">3</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.traffic_instr_data_mode" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>traffic_instr_rw_mode</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">3</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.traffic_instr_rw_mode" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>traffic_instr_rw_submode</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">1</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.traffic_instr_rw_submode" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>traffic_instr_num_of_iter</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">31</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.traffic_instr_num_of_iter" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>traffic_instr_nxt_instr</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">5</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.traffic_instr_nxt_instr" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>win_status</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">31</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.win_status" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.Example_TG')) = "ADVANCED_TG" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>addn_ui_clkout1</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.addn_ui_clkout1" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.No_Controller')) > 0 ) && ( spirit:decode(id('PARAM_VALUE.ADDN_UI_CLKOUT1_FREQ_HZ')) != "NONE" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>addn_ui_clkout2</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.addn_ui_clkout2" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.No_Controller')) > 0 ) && ( spirit:decode(id('PARAM_VALUE.ADDN_UI_CLKOUT2_FREQ_HZ')) != "NONE" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>addn_ui_clkout3</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.addn_ui_clkout3" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.No_Controller')) > 0 ) && ( spirit:decode(id('PARAM_VALUE.ADDN_UI_CLKOUT3_FREQ_HZ')) != "NONE" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>addn_ui_clkout4</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.addn_ui_clkout4" xilinx:dependency="( spirit:decode(id('PARAM_VALUE.No_Controller')) > 0 ) && ( spirit:decode(id('PARAM_VALUE.ADDN_UI_CLKOUT4_FREQ_HZ')) != "NONE" )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>c0_ddr4_mcs_lmb_ce</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_mcs_lmb_ce" xilinx:dependency="(( C0.ControllerType == "DDR4_SDRAM" ) and ( spirit:decode(id('PARAM_VALUE.C0.DDR4_MCS_ECC')) = true ) )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>c0_ddr4_mcs_lmb_ue</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + <spirit:vendorExtensions> + <xilinx:portInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c0_ddr4_mcs_lmb_ue" xilinx:dependency="(( C0.ControllerType == "DDR4_SDRAM" ) and ( spirit:decode(id('PARAM_VALUE.C0.DDR4_MCS_ECC')) = true ) )">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:portInfo> + </spirit:vendorExtensions> + </spirit:port> + <spirit:port> + <spirit:name>sys_rst</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rdDataEn</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">0</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic_vector</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rdDataEnd</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">0</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic_vector</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>per_rd_done</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">0</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic_vector</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rmw_rd_done</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">0</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic_vector</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>wrDataEn</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">0</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic_vector</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>mc_ACT_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">7</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic_vector</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>mcCasSlot</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">1</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic_vector</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>mcCasSlot2</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">0</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic_vector</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>mcRdCAS</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">0</spirit:left> + <spirit:right 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<spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic_vector</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>winRmw</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">0</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic_vector</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>gt_data_ready</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>winRank</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">1</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic_vector</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>tCWL</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">5</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic_vector</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>wrData</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">511</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic_vector</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>wrDataMask</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">63</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic_vector</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rdData</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">511</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>std_logic_vector</spirit:typeName> + <spirit:viewNameRef>xilinx_elaborateports</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>mc_ADR</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">135</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + 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spirit:id="MODELPARAM_VALUE.C0.DDR4_SPEED_GRADE">093E</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_MEM_DENSITY</spirit:name> + <spirit:displayName>MEM DENSITY</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY">4GB</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_MEM_DENSITY_MB</spirit:name> + <spirit:displayName>MEM DENSITY MB</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_MB">4096</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_MEM_DENSITY_GB</spirit:name> + <spirit:displayName>MEM DENSITY GB</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_GB">4</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_COMP_DENSITY</spirit:name> + <spirit:displayName>COMP DENSITY</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_COMP_DENSITY">4Gb</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_MEM_COMP_WIDTH</spirit:name> + <spirit:displayName>MEM COMP WIDTH</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_COMP_WIDTH">8</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_DATABITS_PER_STROBE</spirit:name> + <spirit:displayName>DATABITS PER STROBE</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DATABITS_PER_STROBE">8</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_MODEL_SPEED_GRADE</spirit:name> + <spirit:displayName>MODEL SPEED GRADE</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MODEL_SPEED_GRADE">DDR4_938_Timing</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_RANK_WIDTH</spirit:name> + <spirit:displayName>RANK WIDTH</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_RANK_WIDTH">1</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_IO_VOLTAGE</spirit:name> + <spirit:displayName>IO VOLTAGE</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_IO_VOLTAGE">1.2V</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_MIN_PERIOD</spirit:name> + <spirit:displayName>MIN PERIOD</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MIN_PERIOD">938</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_MAX_PERIOD</spirit:name> + <spirit:displayName>MAX PERIOD</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MAX_PERIOD">1600</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_MR0</spirit:name> + <spirit:displayName>Mode register_0 value</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MR0">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_MR2</spirit:name> + <spirit:displayName>Mode register_2 value</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MR2">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_nAL</spirit:name> + <spirit:displayName>Additive Latency in number of clock</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_nAL">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_BURST_MODE</spirit:name> + <spirit:displayName>Burst Mode</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_BURST_MODE">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_BURST_TYPE</spirit:name> + <spirit:displayName>Burst Type</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_BURST_TYPE">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_CL</spirit:name> + <spirit:displayName>Cas Latency</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CL">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_CWL</spirit:name> + <spirit:displayName>Cas Write Latency</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CWL">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_OUTPUT_DRV</spirit:name> + <spirit:displayName>Output drive Strength</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_OUTPUT_DRV">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_RTT_NOM</spirit:name> + <spirit:displayName>RTT Nominal</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_RTT_NOM">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_RTT_WR</spirit:name> + <spirit:displayName>RTT WR</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_RTT_WR">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_MEM</spirit:name> + <spirit:displayName>Memory Name</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_DBAW</spirit:name> + <spirit:displayName>DBAW</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DBAW">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tCK</spirit:name> + <spirit:displayName>tCK</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tCK">1500</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_Configuration</spirit:name> + <spirit:displayName>Configuration</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_Configuration">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tCKE</spirit:name> + <spirit:displayName>tCKE</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tCKE">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tFAW</spirit:name> + <spirit:displayName>tFAW</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tFAW">14</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tFAW_dlr</spirit:name> + <spirit:displayName>tFAW_dlr</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tFAW_dlr">16</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tMRD</spirit:name> + <spirit:displayName>tMRD</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tMRD">2</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tRAS</spirit:name> + <spirit:displayName>tRAS</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRAS">22</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tRCD</spirit:name> + <spirit:displayName>tRCD</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRCD">10</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tREFI</spirit:name> + <spirit:displayName>tREFI</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tREFI">5200</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tRFC</spirit:name> + <spirit:displayName>tRFC</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRFC">174</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tRFC_dlr</spirit:name> + <spirit:displayName>tRFC_dlr</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRFC_dlr">60</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tRP</spirit:name> + <spirit:displayName>tRP</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRP">10</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tWR</spirit:name> + <spirit:displayName>tWR</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tWR">10</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tRRD</spirit:name> + <spirit:displayName>tRRD</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRRD"/> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tRTP</spirit:name> + <spirit:displayName>tRTP</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRTP">5</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tRRD_S</spirit:name> + <spirit:displayName>tRRD_S</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRRD_S">3</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tRRD_L</spirit:name> + <spirit:displayName>tRRD_L</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRRD_L">4</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tRRD_dlr</spirit:name> + <spirit:displayName>tRRD_dlr</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tRRD_dlr">4</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tWTR</spirit:name> + <spirit:displayName>tWTR</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tWTR"/> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tWTR_S</spirit:name> + <spirit:displayName>tWTR_S</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tWTR_S">2</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tWTR_L</spirit:name> + <spirit:displayName>tWTR_L</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tWTR_L">5</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tXPR</spirit:name> + <spirit:displayName>tXPR</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tXPR">45</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tZQI</spirit:name> + <spirit:displayName>tZQI</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tZQI">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tZQCS</spirit:name> + <spirit:displayName>tZQCS</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tZQCS">128</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tZQINIT</spirit:name> + <spirit:displayName>tZQINIT</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tZQINIT">256</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_tCCD_3ds</spirit:name> + <spirit:displayName>tCCD_3ds</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_tCCD_3ds">5</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_CLKOUTPHY_MODE</spirit:name> + <spirit:displayName>CLKOUTPHY_MODE</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE">VCO</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_CLKOUT0_DIVIDE</spirit:name> + <spirit:displayName>CLKOUT0_DIVIDE</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE">6</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_CLKOUT1_DIVIDE</spirit:name> + <spirit:displayName>CLKOUT1_DIVIDE</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKOUT1_DIVIDE">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_CLKFBOUT_MULT</spirit:name> + <spirit:displayName>CLKFBOUT_MULT</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKFBOUT_MULT">10</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_DIVCLK_DIVIDE</spirit:name> + <spirit:displayName>DIVCLK DIVIDE</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>CAL_INPUT_CLK_PERIOD</spirit:name> + <spirit:displayName>Calculated Input Clock Period</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CAL_INPUT_CLK_PERIOD">10000</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_CLKIN_PERIOD</spirit:name> + <spirit:displayName>CLKIN_PERIOD</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CLKIN_PERIOD">10000</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_HR_MIN_FREQ</spirit:name> + <spirit:displayName>High Range Supported frequency</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_HR_MIN_FREQ">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_DCI_CASCADE_CUTOFF</spirit:name> + <spirit:displayName>DCI Cascade Cutoff</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_DCI_CASCADE_CUTOFF">938</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_IS_FASTER_SPEED_RAM</spirit:name> + <spirit:displayName>Is Faster Speed RAM</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM">No</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_AXI_ID_WIDTH</spirit:name> + <spirit:displayName>AXI ID Width</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AXI_ID_WIDTH">4</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_AXI_ADDR_WIDTH</spirit:name> + <spirit:displayName>AXI Address Width</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AXI_ADDR_WIDTH">32</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_AXI_DATA_WIDTH</spirit:name> + <spirit:displayName>AXI Data Width</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AXI_DATA_WIDTH">64</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_MEM_SIZE</spirit:name> + <spirit:displayName>Memory Size</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MEM_SIZE">4294967296</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_UI_CLOCK</spirit:name> + <spirit:displayName>DDR4 UI CLOCK</spirit:displayName> + <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_UI_CLOCK">166500000</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_CA_MIRROR</spirit:name> + <spirit:displayName>CA MIRROR</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_CA_MIRROR">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_IS_CUSTOM</spirit:name> + <spirit:displayName>IS CUSTOM</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_IS_CUSTOM">false</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_AUTO_AP_COL_A3</spirit:name> + <spirit:displayName>AUTO AP COL A3</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_AUTO_AP_COL_A3">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_MCS_ECC</spirit:name> + <spirit:displayName>MCS ECC</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_MCS_ECC">0</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.DDR4_Slot</spirit:name> + <spirit:displayName>Slot Type</spirit:displayName> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C0.DDR4_Slot">1</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter> + <spirit:name>C0.APP_DATA_WIDTH</spirit:name> + <spirit:displayName>APP Data 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