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-rw-r--r--projects/VU095/patches/rd_en.patch123
-rw-r--r--projects/VU095/patches/write.patch31
2 files changed, 154 insertions, 0 deletions
diff --git a/projects/VU095/patches/rd_en.patch b/projects/VU095/patches/rd_en.patch
new file mode 100644
index 0000000..5372b32
--- /dev/null
+++ b/projects/VU095/patches/rd_en.patch
@@ -0,0 +1,123 @@
+--- VU095.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_rd_en.sv
+@@ -114,55 +114,86 @@
+
+ reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn;
+ (* KEEP = "true" *) reg [RL+12 + 4*EXTRA_CMD_DELAY :0] rdEn_nxt;
+-reg [18:0] rsMask[0:7];
++reg [19:0] rsMask[0:15];
+
+-function [18:0] rs2mask;
++// RS probably stands for rank select.
++// TODO edit below in worst case.
++function [19:0] rs2mask;
+ input [3:0] diff;
+ input slot2;
+-case ({diff, slot2})
+- 5'b0_0000: rs2mask = 19'b000_0000_0000_0000_1111;
+- 5'b0_0001: rs2mask = 19'b000_0000_0000_0011_1100;
+- 5'b0_0010: rs2mask = 19'b000_0000_0000_0001_1110;
+- 5'b0_0011: rs2mask = 19'b000_0000_0000_0111_1000;
+- 5'b0_0100: rs2mask = 19'b000_0000_0000_0011_1100;
+- 5'b0_0101: rs2mask = 19'b000_0000_0000_1111_0000;
+- 5'b0_0110: rs2mask = 19'b000_0000_0000_0111_1000;
+- 5'b0_0111: rs2mask = 19'b000_0000_0001_1110_0000;
+- 5'b0_1000: rs2mask = 19'b000_0000_0000_1111_0000;
+- 5'b0_1001: rs2mask = 19'b000_0000_0011_1100_0000;
+- 5'b0_1010: rs2mask = 19'b000_0000_0001_1110_0000;
+- 5'b0_1011: rs2mask = 19'b000_0000_0111_1000_0000;
+- 5'b0_1100: rs2mask = 19'b000_0000_0011_1100_0000;
+- 5'b0_1101: rs2mask = 19'b000_0000_1111_0000_0000;
+- 5'b0_1110: rs2mask = 19'b000_0000_0111_1000_0000;
+- 5'b0_1111: rs2mask = 19'b000_0001_1110_0000_0000;
+- 5'b1_0000: rs2mask = 19'b000_0000_1111_0000_0000;
+- 5'b1_0001: rs2mask = 19'b000_0011_1100_0000_0000;
+- 5'b1_0010: rs2mask = 19'b000_0001_1110_0000_0000;
+- 5'b1_0011: rs2mask = 19'b000_0111_1000_0000_0000;
+- 5'b1_0100: rs2mask = 19'b000_0011_1100_0000_0000;
+- 5'b1_0101: rs2mask = 19'b000_1111_0000_0000_0000;
+- 5'b1_0110: rs2mask = 19'b000_0111_1000_0000_0000;
+- 5'b1_0111: rs2mask = 19'b001_1110_0000_0000_0000;
+- 5'b1_1000: rs2mask = 19'b000_1111_0000_0000_0000;
+- 5'b1_1001: rs2mask = 19'b011_1100_0000_0000_0000;
+- 5'b1_1010: rs2mask = 19'b001_1110_0000_0000_0000;
+- 5'b1_1011: rs2mask = 19'b111_1000_0000_0000_0000;
++ input slot1;
++case ({diff, slot2, slot1})
++6'b0_00000: rs2mask = 19'b000_0000_0000_0000_1111;
++ 6'b0_00001: rs2mask = 19'b000_0000_0000_0001_1110;
++ 6'b0_00010: rs2mask = 19'b000_0000_0000_0011_1100;
++ 6'b0_00011: rs2mask = 19'b000_0000_0000_0111_1000;
++ 6'b0_00100: rs2mask = 19'b000_0000_0000_0001_1110;
++ 6'b0_00101: rs2mask = 19'b000_0000_0000_0011_1100;
++ 6'b0_00110: rs2mask = 19'b000_0000_0000_0111_1000;
++ 6'b0_00111: rs2mask = 19'b000_0000_0000_1111_0000;
++ 6'b0_01000: rs2mask = 19'b000_0000_0000_0011_1100;
++ 6'b0_01001: rs2mask = 19'b000_0000_0000_0111_1000;
++ 6'b0_01010: rs2mask = 19'b000_0000_0000_1111_0000;
++ 6'b0_01011: rs2mask = 19'b000_0000_0001_1110_0000;
++ 6'b0_01100: rs2mask = 19'b000_0000_0000_0111_1000;
++ 6'b0_01101: rs2mask = 19'b000_0000_0000_1111_0000;
++ 6'b0_01110: rs2mask = 19'b000_0000_0001_1110_0000;
++ 6'b0_01111: rs2mask = 19'b000_0000_0011_1100_0000;
++ 6'b0_10000: rs2mask = 19'b000_0000_0000_1111_0000;
++ 6'b0_10001: rs2mask = 19'b000_0000_0001_1110_0000;
++ 6'b0_10010: rs2mask = 19'b000_0000_0011_1100_0000;
++ 6'b0_10011: rs2mask = 19'b000_0000_0111_1000_0000;
++ 6'b0_10100: rs2mask = 19'b000_0000_0001_1110_0000;
++ 6'b0_10101: rs2mask = 19'b000_0000_0011_1100_0000;
++ 6'b0_10110: rs2mask = 19'b000_0000_0111_1000_0000;
++ 6'b0_10111: rs2mask = 19'b000_0000_1111_0000_0000;
++ 6'b0_11000: rs2mask = 19'b000_0000_0011_1100_0000;
++ 6'b0_11001: rs2mask = 19'b000_0000_0111_1000_0000;
++ 6'b0_11010: rs2mask = 19'b000_0000_1111_0000_0000;
++ 6'b0_11011: rs2mask = 19'b000_0001_1110_0000_0000;
++ 6'b0_11100: rs2mask = 19'b000_0000_0111_1000_0000;
++ 6'b0_11101: rs2mask = 19'b000_0000_1111_0000_0000;
++ 6'b0_11110: rs2mask = 19'b000_0001_1110_0000_0000;
++ 6'b0_11111: rs2mask = 19'b000_0011_1100_0000_0000;
++ 6'b1_00000: rs2mask = 19'b000_0000_1111_0000_0000;
++ 6'b1_00001: rs2mask = 19'b000_0001_1110_0000_0000;
++ 6'b1_00010: rs2mask = 19'b000_0011_1100_0000_0000;
++ 6'b1_00011: rs2mask = 19'b000_0111_1000_0000_0000;
++ 6'b1_00100: rs2mask = 19'b000_0001_1110_0000_0000;
++ 6'b1_00101: rs2mask = 19'b000_0011_1100_0000_0000;
++ 6'b1_00110: rs2mask = 19'b000_0111_1000_0000_0000;
++ 6'b1_00111: rs2mask = 19'b000_1111_0000_0000_0000;
++ 6'b1_01000: rs2mask = 19'b000_0011_1100_0000_0000;
++ 6'b1_01001: rs2mask = 19'b000_0111_1000_0000_0000;
++ 6'b1_01010: rs2mask = 19'b000_1111_0000_0000_0000;
++ 6'b1_01011: rs2mask = 19'b001_1110_0000_0000_0000;
++ 6'b1_01100: rs2mask = 19'b000_0111_1000_0000_0000;
++ 6'b1_01101: rs2mask = 19'b000_1111_0000_0000_0000;
++ 6'b1_01110: rs2mask = 19'b001_1110_0000_0000_0000;
++ 6'b1_01111: rs2mask = 19'b011_1100_0000_0000_0000;
++ 6'b1_10000: rs2mask = 19'b000_1111_0000_0000_0000;
++ 6'b1_10001: rs2mask = 19'b001_1110_0000_0000_0000;
++ 6'b1_10010: rs2mask = 19'b011_1100_0000_0000_0000;
++ 6'b1_10011: rs2mask = 19'b111_1000_0000_0000_0000;
++ 6'b1_10100: rs2mask = 19'b001_1110_0000_0000_0000;
++ 6'b1_10101: rs2mask = 19'b011_1100_0000_0000_0000;
++ 6'b1_10110: rs2mask = 19'b111_1000_0000_0000_0000;
++ 6'b1_10111: rs2mask = 20'b1111_0000_0000_0000_0000;
+ default: rs2mask = 19'b000_0000_1000_0000_1111;
+ endcase
+ endfunction
+
+ always @(posedge clk) begin: blk1
+- reg [3:0] rsNdx;
+- for (rsNdx = 0; rsNdx <= 7; rsNdx = rsNdx + 1)
+- rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[2:1]] - (RL - 3), rsNdx[0]);
++ reg [4:0] rsNdx;
++ for (rsNdx = 0; rsNdx <= 15; rsNdx = rsNdx + 1)
++ rsMask[rsNdx] <= #TCQ rs2mask(mCL[rsNdx[3:2]] - (RL - 3), rsNdx[1], rsNdx[0]);
+ end
+
+ always @(*) if (rst) begin
+ rdEn_nxt = 'b0;
+ end else begin
+ rdEn_nxt = (rdEn >> 4)
+- | (rdCAS ? {rsMask[{winRank, casSlot[1]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}}
++ | (rdCAS ? {rsMask[{winRank, casSlot[1], casSlot[0]}], { (RL-6 + 4*EXTRA_CMD_DELAY) {1'b0}}}
+ : 'b0);
+ end
+
diff --git a/projects/VU095/patches/write.patch b/projects/VU095/patches/write.patch
new file mode 100644
index 0000000..9e40894
--- /dev/null
+++ b/projects/VU095/patches/write.patch
@@ -0,0 +1,31 @@
+--- VU095.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv
+@@ -157,9 +157,13 @@
+ // used in pushing new write CAS commands into the wrQ shift register. These values are
+ // calculated for both casslot0 and casslot2.
+ localparam FABRIC_CASSLOT0 = ( ALL_WR_LATENCY / 4 ) - 2;
++localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2;
+ localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2;
++localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2;
+ localparam OFFSET_CASSLOT0 = ( ALL_WR_LATENCY ) % 4;
++localparam OFFSET_CASSLOT1 = ( ALL_WR_LATENCY + 1 ) % 4;
+ localparam OFFSET_CASSLOT2 = ( ALL_WR_LATENCY + 2 ) % 4;
++localparam OFFSET_CASSLOT3 = ( ALL_WR_LATENCY + 3 ) % 4;
+
+ integer i;
+
+@@ -192,10 +196,12 @@
+ // Output enable shift register fabric load cycle for cal and mc. mccasSlot2 is timing critical.
+ reg [3:0] oe_0_mux_cal;
+ wire [3:0] oe_0_mux_cal_nxt = calDone ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2;
+-wire [3:0] oe_fabric = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal;
++wire [3:0] oe_fabric = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) :
++ (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal);
+
+ // tCK offset for mc. mccasSlot2 is timing critical.
+-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0;
++wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) :
++ (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0);
+
+ // Output enable shift register load value for cal and mc. mcwrCAS and tck_offset are timing critical.
+ wire [DBAW+4:0] wrQ_cal_load_value = {winBuf, calRank, OFFSET_CASSLOT2[1:0], 1'b1};
+
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