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Diffstat (limited to 'projects/XUPVVH/XUPVVH.ip_user_files/ip/instr_blk_mem')
4 files changed, 215 insertions, 0 deletions
diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ip/instr_blk_mem/instr_blk_mem.veo b/projects/XUPVVH/XUPVVH.ip_user_files/ip/instr_blk_mem/instr_blk_mem.veo new file mode 100755 index 0000000..85923e5 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ip/instr_blk_mem/instr_blk_mem.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +instr_blk_mem your_instance_name ( + .clka(clka), // input wire clka + .ena(ena), // input wire ena + .wea(wea), // input wire [0 : 0] wea + .addra(addra), // input wire [10 : 0] addra + .dina(dina), // input wire [63 : 0] dina + .douta(douta) // output wire [63 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file instr_blk_mem.v when simulating +// the core, instr_blk_mem. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ip/instr_blk_mem/instr_blk_mem.vho b/projects/XUPVVH/XUPVVH.ip_user_files/ip/instr_blk_mem/instr_blk_mem.vho new file mode 100755 index 0000000..7705c50 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ip/instr_blk_mem/instr_blk_mem.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT instr_blk_mem + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : instr_blk_mem + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file instr_blk_mem.vhd when simulating +-- the core, instr_blk_mem. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.v b/projects/XUPVVH/XUPVVH.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.v new file mode 100644 index 0000000..8f8eedc --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 +// Date : Sun Oct 18 14:26:40 2020 +// Host : jalapeno running 64-bit Ubuntu 18.04.5 LTS +// Command : write_verilog -force -mode synth_stub +// /home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem_stub.v +// Design : instr_blk_mem +// Purpose : Stub declaration of top-level module interface +// Device : xcvu37p-fsvh2892-2-e +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2019.2" *) +module instr_blk_mem(clka, ena, wea, addra, dina, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[10:0],dina[63:0],douta[63:0]" */; + input clka; + input ena; + input [0:0]wea; + input [10:0]addra; + input [63:0]dina; + output [63:0]douta; +endmodule diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.vhdl b/projects/XUPVVH/XUPVVH.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.vhdl new file mode 100644 index 0000000..bd87178 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ip/instr_blk_mem/instr_blk_mem_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 +-- Date : Sun Oct 18 14:26:40 2020 +-- Host : jalapeno running 64-bit Ubuntu 18.04.5 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/ataberk/SoftMC_DDR4/projects/XUPVVH/XUPVVH.srcs/sources_1/ip/instr_blk_mem/instr_blk_mem_stub.vhdl +-- Design : instr_blk_mem +-- Purpose : Stub declaration of top-level module interface +-- Device : xcvu37p-fsvh2892-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity instr_blk_mem is + Port ( + clka : in STD_LOGIC; + ena : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + +end instr_blk_mem; + +architecture stub of instr_blk_mem is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[10:0],dina[63:0],douta[63:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2019.2"; +begin +end; |