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Diffstat (limited to 'projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog')
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diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/axi_infrastructure_header.vh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/axi_infrastructure_header.vh new file mode 100755 index 0000000..d3d4a0e --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/axi_infrastructure_header.vh @@ -0,0 +1,138 @@ +// (c) Copyright 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Generic Functions used by AXI Infrastructure Modules +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// Global Parameters: +// +// Functions: +// +// Tasks: +//-------------------------------------------------------------------------- +/////////////////////////////////////////////////////////////////////////////// +// BEGIN Global Parameters +/////////////////////////////////////////////////////////////////////////////// +localparam G_AXI_AWADDR_INDEX = 0; +localparam G_AXI_AWADDR_WIDTH = C_AXI_ADDR_WIDTH; +localparam G_AXI_AWPROT_INDEX = G_AXI_AWADDR_INDEX + G_AXI_AWADDR_WIDTH; +localparam G_AXI_AWPROT_WIDTH = 3; +localparam G_AXI_AWSIZE_INDEX = G_AXI_AWPROT_INDEX + G_AXI_AWPROT_WIDTH; +localparam G_AXI_AWSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3; +localparam G_AXI_AWBURST_INDEX = G_AXI_AWSIZE_INDEX + G_AXI_AWSIZE_WIDTH; +localparam G_AXI_AWBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2; +localparam G_AXI_AWCACHE_INDEX = G_AXI_AWBURST_INDEX + G_AXI_AWBURST_WIDTH; +localparam G_AXI_AWCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4; +localparam G_AXI_AWLEN_INDEX = G_AXI_AWCACHE_INDEX + G_AXI_AWCACHE_WIDTH; +localparam G_AXI_AWLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8; +localparam G_AXI_AWLOCK_INDEX = G_AXI_AWLEN_INDEX + G_AXI_AWLEN_WIDTH; +localparam G_AXI_AWLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1; +localparam G_AXI_AWID_INDEX = G_AXI_AWLOCK_INDEX + G_AXI_AWLOCK_WIDTH; +localparam G_AXI_AWID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_AWQOS_INDEX = G_AXI_AWID_INDEX + G_AXI_AWID_WIDTH; +localparam G_AXI_AWQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4; +localparam G_AXI_AWREGION_INDEX = G_AXI_AWQOS_INDEX + G_AXI_AWQOS_WIDTH; +localparam G_AXI_AWREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4; +localparam G_AXI_AWUSER_INDEX = G_AXI_AWREGION_INDEX + G_AXI_AWREGION_WIDTH; +localparam G_AXI_AWUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_AWUSER_WIDTH; +localparam G_AXI_AWPAYLOAD_WIDTH = G_AXI_AWUSER_INDEX + G_AXI_AWUSER_WIDTH; +localparam G_AXI_ARADDR_INDEX = 0; +localparam G_AXI_ARADDR_WIDTH = C_AXI_ADDR_WIDTH; +localparam G_AXI_ARPROT_INDEX = G_AXI_ARADDR_INDEX + G_AXI_ARADDR_WIDTH; +localparam G_AXI_ARPROT_WIDTH = 3; +localparam G_AXI_ARSIZE_INDEX = G_AXI_ARPROT_INDEX + G_AXI_ARPROT_WIDTH; +localparam G_AXI_ARSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3; +localparam G_AXI_ARBURST_INDEX = G_AXI_ARSIZE_INDEX + G_AXI_ARSIZE_WIDTH; +localparam G_AXI_ARBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2; +localparam G_AXI_ARCACHE_INDEX = G_AXI_ARBURST_INDEX + G_AXI_ARBURST_WIDTH; +localparam G_AXI_ARCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4; +localparam G_AXI_ARLEN_INDEX = G_AXI_ARCACHE_INDEX + G_AXI_ARCACHE_WIDTH; +localparam G_AXI_ARLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8; +localparam G_AXI_ARLOCK_INDEX = G_AXI_ARLEN_INDEX + G_AXI_ARLEN_WIDTH; +localparam G_AXI_ARLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1; +localparam G_AXI_ARID_INDEX = G_AXI_ARLOCK_INDEX + G_AXI_ARLOCK_WIDTH; +localparam G_AXI_ARID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_ARQOS_INDEX = G_AXI_ARID_INDEX + G_AXI_ARID_WIDTH; +localparam G_AXI_ARQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4; +localparam G_AXI_ARREGION_INDEX = G_AXI_ARQOS_INDEX + G_AXI_ARQOS_WIDTH; +localparam G_AXI_ARREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4; +localparam G_AXI_ARUSER_INDEX = G_AXI_ARREGION_INDEX + G_AXI_ARREGION_WIDTH; +localparam G_AXI_ARUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_ARUSER_WIDTH; +localparam G_AXI_ARPAYLOAD_WIDTH = G_AXI_ARUSER_INDEX + G_AXI_ARUSER_WIDTH; +// Write channel widths +localparam G_AXI_WDATA_INDEX = 0; +localparam G_AXI_WDATA_WIDTH = C_AXI_DATA_WIDTH; +localparam G_AXI_WSTRB_INDEX = G_AXI_WDATA_INDEX + G_AXI_WDATA_WIDTH; +localparam G_AXI_WSTRB_WIDTH = C_AXI_DATA_WIDTH / 8; +localparam G_AXI_WLAST_INDEX = G_AXI_WSTRB_INDEX + G_AXI_WSTRB_WIDTH; +localparam G_AXI_WLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1; +localparam G_AXI_WID_INDEX = G_AXI_WLAST_INDEX + G_AXI_WLAST_WIDTH; +localparam G_AXI_WID_WIDTH = (C_AXI_PROTOCOL != 1) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_WUSER_INDEX = G_AXI_WID_INDEX + G_AXI_WID_WIDTH; +localparam G_AXI_WUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_WUSER_WIDTH; +localparam G_AXI_WPAYLOAD_WIDTH = G_AXI_WUSER_INDEX + G_AXI_WUSER_WIDTH; +// Write Response channel Widths +localparam G_AXI_BRESP_INDEX = 0; +localparam G_AXI_BRESP_WIDTH = 2; +localparam G_AXI_BID_INDEX = G_AXI_BRESP_INDEX + G_AXI_BRESP_WIDTH; +localparam G_AXI_BID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_BUSER_INDEX = G_AXI_BID_INDEX + G_AXI_BID_WIDTH; +localparam G_AXI_BUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_BUSER_WIDTH; +localparam G_AXI_BPAYLOAD_WIDTH = G_AXI_BUSER_INDEX + G_AXI_BUSER_WIDTH; +// Read channel widths +localparam G_AXI_RDATA_INDEX = 0; +localparam G_AXI_RDATA_WIDTH = C_AXI_DATA_WIDTH; +localparam G_AXI_RRESP_INDEX = G_AXI_RDATA_INDEX + G_AXI_RDATA_WIDTH; +localparam G_AXI_RRESP_WIDTH = 2; +localparam G_AXI_RLAST_INDEX = G_AXI_RRESP_INDEX + G_AXI_RRESP_WIDTH; +localparam G_AXI_RLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1; +localparam G_AXI_RID_INDEX = G_AXI_RLAST_INDEX + G_AXI_RLAST_WIDTH; +localparam G_AXI_RID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_RUSER_INDEX = G_AXI_RID_INDEX + G_AXI_RID_WIDTH; +localparam G_AXI_RUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_RUSER_WIDTH; +localparam G_AXI_RPAYLOAD_WIDTH = G_AXI_RUSER_INDEX + G_AXI_RUSER_WIDTH; diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/axidma_fifo.vh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/axidma_fifo.vh new file mode 100755 index 0000000..2311783 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/axidma_fifo.vh @@ -0,0 +1,1287 @@ +`ifndef AXIDMA_FIFO_VH +`define AXIDMA_FIFO_VH +`include "xdma_axi4mm_axi_bridge.vh" +//----------------------------------------------------------------------------- +// $Id: +//----------------------------------------------------------------------------- +// axi_bridge.vh +//----------------------------------------------------------------------------- +// (c) Copyright 2010 - 2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// Filename: axi_bridge.vh +// +// Description: +// +// This file needs to be included in all modules so that all the modules can commonly +// reference state_transitions +// +// +// VHDL-Standard: VHDL'93 +//----------------------------------------------------------------------------- +// Structure: +// Include file +// +//----------------------------------------------------------------------------- +// Revision: v1.05.a +// Date: 06/28/12 +// +//----------------------------------------------------------------------------- + + + + //signal arid_dependencySM_cs : arid_dependencySM_STATES; + //signal arid_dependencySM_ns : arid_dependencySM_STATES; + module xdma_v4_1_4_BufferMem + #( + parameter TCQ = 1, + parameter BUF_DATAWIDTH = 256, + parameter BUF_WE = BUF_DATAWIDTH/8, + parameter BUF_DEPTH = 512, + parameter BUF_PTR = (BUF_DEPTH <=2) ? 1: + (BUF_DEPTH <=4) ? 2: + (BUF_DEPTH <=8) ? 3: + (BUF_DEPTH <=16) ? 4: + (BUF_DEPTH <=32) ? 5: + (BUF_DEPTH <=64) ? 6: + (BUF_DEPTH <=128) ? 7: + (BUF_DEPTH <=256) ? 8: + (BUF_DEPTH <=512) ? 9: + (BUF_DEPTH <=1024) ? 10 : -1, + parameter NO_OUTPUT_REG = 1 + ) + ( + input clkin, + input reset_n, + input wrEn, + input [BUF_DATAWIDTH-1:0] DataIn, + input [BUF_DATAWIDTH/8-1:0] EccIn, + input [BUF_PTR-1:0] AddrIn, + input [BUF_PTR-1:0] AddrOut, + input rdEn, + output [BUF_DATAWIDTH-1:0] DataOut, + output [BUF_DATAWIDTH/8-1:0] EccOut + ); + reg [BUF_DATAWIDTH-1:0] DataMem [BUF_DEPTH-1:0]; + reg [BUF_DATAWIDTH/8-1:0] EccMem [BUF_DEPTH-1:0]; + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + end + else if (wrEn) begin + DataMem[AddrIn] <= DataIn; + EccMem[AddrIn] <= EccIn; + end + end + //wire [BUF_DATAWIDTH-1:0] BuftoMem; + if(NO_OUTPUT_REG) begin: nooutput + assign DataOut = DataMem[AddrOut]; + assign EccOut = EccMem[AddrOut]; + end + else begin: outputStage + reg [BUF_DATAWIDTH-1:0] BufDout; + reg [BUF_DATAWIDTH/8-1:0] BufEccout; + `XSRREG_AXIMM(clkin, reset_n, BufDout, rdEn ?DataMem[AddrOut]: BufDout, {BUF_DATAWIDTH{1'b0}}) + `XSRREG_AXIMM(clkin, reset_n, BufEccout, rdEn ?EccMem[AddrOut] : BufEccout, {(BUF_DATAWIDTH/8){1'b0}}) + assign DataOut = BufDout; + assign EccOut = BufEccout; + + end + + endmodule // BufferMem + + module xdma_v4_1_4_GenericFIFO1R2W + #(parameter BUF_DATAWIDTH = 256, + parameter BUF_WE = BUF_DATAWIDTH/8, + parameter BUF_DEPTH = 512, + parameter BUF_PTR = (BUF_DEPTH <=2) ? 1: + (BUF_DEPTH <=4) ? 2: + (BUF_DEPTH <=8) ? 3: + (BUF_DEPTH <=16) ? 4: + (BUF_DEPTH <=32) ? 5: + (BUF_DEPTH <=64) ? 6: + (BUF_DEPTH <=128) ? 7: + (BUF_DEPTH <=256) ? 8: + (BUF_DEPTH <=512) ? 9: + (BUF_DEPTH <=1024) ? 10 : -1, + parameter AE_THRESHOLD = BUF_DEPTH >> 2, + parameter AF_THRESHOLD = BUF_DEPTH - 2 + ) + ( + input clkin, + input reset_n, + input sync_reset_n, + input WrEn0, + input WrEn1, + input [BUF_DATAWIDTH-1:0] DataIn0, + input [BUF_DATAWIDTH-1:0] DataIn1, + output [BUF_DATAWIDTH-1:0] DataOut, + input RdEn, + output almost_empty, + output almost_full, + output empty, + output full0, + output full1 + ); +(* ram_style = "DISTRIBUTED" *) + reg [BUF_DATAWIDTH-1:0] MemArray [BUF_DEPTH-1:0]; +(* max_fanout = 128 *) reg [BUF_PTR-1:0] WrPtr; +(* max_fanout = 128 *) reg [BUF_PTR-1:0] WrPtrp1; +(* max_fanout = 128 *) reg [BUF_PTR-1:0] RdPtr; + reg [BUF_PTR:0] FifoCntr; + reg almost_empty_ff; + reg almost_full_ff; + reg empty_ff; + reg full_ff0; + reg full_ff1; + assign RdDeQ = RdEn; + assign DataOut = MemArray[RdPtr]; + assign almost_empty = almost_empty_ff; + assign almost_full = almost_full_ff; + assign empty = empty_ff; + assign full0 = full_ff0; + assign full1 = full_ff1; + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n || ~sync_reset_n) begin + WrPtr <= 'd0; + WrPtrp1 <= 'd1; + end + else if (WrEn0 && WrEn1) begin + WrPtr <= WrPtr + 'd2; + WrPtrp1 <= WrPtr + 'd3; + end + else if (WrEn0 || WrEn1) begin + WrPtr <= WrPtr + 'd1; + WrPtrp1 <= WrPtr + 'd2; + end + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n || ~sync_reset_n) begin + RdPtr <= 'd0; + end + else if (RdEn) begin + RdPtr <= RdPtr + 'd1; + end + end + + always @ (posedge clkin) begin + if (WrEn0 && WrEn1) + begin + MemArray[WrPtr] <= DataIn0; + MemArray[WrPtrp1] <= DataIn1; + end + else if (WrEn0) + MemArray[WrPtr] <= DataIn0; + else if (WrEn1) + MemArray[WrPtr] <= DataIn1; + end + + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n || ~sync_reset_n) + FifoCntr <= 'd0; + else if (WrEn0 && WrEn1 && ~RdDeQ) + FifoCntr <= FifoCntr +'d2; + else if (((WrEn0 || WrEn1) && ~RdDeQ) || + ((WrEn0 && WrEn1) && RdDeQ)) + FifoCntr <= FifoCntr +'d1; + else if (~(WrEn0 || WrEn1) && RdDeQ) + FifoCntr <= FifoCntr -'d1; + else + FifoCntr <= FifoCntr; + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n || ~sync_reset_n) + empty_ff <= 1'b1; + else if((FifoCntr==0) || ((FifoCntr==1) && RdEn)) + empty_ff <= 1'b1; + else if(FifoCntr>0) + empty_ff <= 1'b0; + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n || ~sync_reset_n) + almost_empty_ff <= 1'b1; + else if(FifoCntr>(AE_THRESHOLD)) + almost_empty_ff <= 1'b0; + else if(FifoCntr<=(AE_THRESHOLD)) + almost_empty_ff <= 1'b1; + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n || ~sync_reset_n) + full_ff0 <= 1'b0; + else if ((FifoCntr==(BUF_DEPTH)) || + ((FifoCntr==(BUF_DEPTH-1)) && (WrEn0 || WrEn1)) || + ((FifoCntr==(BUF_DEPTH-2)) && (WrEn0 && WrEn1))) + full_ff0 <= 1'b1; + else if(FifoCntr<BUF_DEPTH) + full_ff0 <= 1'b0; + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n || ~sync_reset_n) + full_ff1 <= 1'b0; + else if ((FifoCntr==(BUF_DEPTH-1)) || + ((FifoCntr==(BUF_DEPTH-2)) && (WrEn0 || WrEn1)) || + ((FifoCntr==(BUF_DEPTH-3)) && (WrEn0 && WrEn1))) + full_ff1 <= 1'b1; + else if(FifoCntr<BUF_DEPTH-1) + full_ff1 <= 1'b0; + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n || ~sync_reset_n) + almost_full_ff <= 1'b0; + else if(FifoCntr>(AF_THRESHOLD)) + almost_full_ff <= 1'b1; + else if(FifoCntr<=(AF_THRESHOLD)) + almost_full_ff <= 1'b0; + end + endmodule + module xdma_v4_1_4_GenericFIFO + #(parameter BUF_DATAWIDTH = 256, + parameter BUF_WE = BUF_DATAWIDTH/8, + parameter BUF_DEPTH = 512, + parameter BUF_PTR = (BUF_DEPTH <=2) ? 1: + (BUF_DEPTH <=4) ? 2: + (BUF_DEPTH <=8) ? 3: + (BUF_DEPTH <=16) ? 4: + (BUF_DEPTH <=32) ? 5: + (BUF_DEPTH <=64) ? 6: + (BUF_DEPTH <=128) ? 7: + (BUF_DEPTH <=256) ? 8: + (BUF_DEPTH <=512) ? 9: + (BUF_DEPTH <=1024) ? 10 : -1, + parameter AE_THRESHOLD = BUF_DEPTH >> 2, + parameter AF_THRESHOLD = BUF_DEPTH - 2 + ) + ( + input clkin, + input reset_n, + input sync_reset_n, + input [BUF_DATAWIDTH-1:0] DataIn, + output [BUF_DATAWIDTH-1:0] DataOut, + input WrEn, + input RdEn, + output almost_empty, + output almost_full, + output empty, + output full + ); +(* ram_style = "DISTRIBUTED" *) + reg [BUF_DATAWIDTH-1:0] MemArray [BUF_DEPTH-1:0]; +(* max_fanout = 128 *) reg [BUF_PTR-1:0] WrPtr; +(* max_fanout = 128 *) reg [BUF_PTR-1:0] RdPtr; + reg [BUF_PTR:0] FifoCntrWr; + reg [BUF_PTR:0] FifoCntrRd; + wire WriteQ, RdDeQ; + reg almost_empty_ff; + reg almost_full_ff; + reg empty_ff; + reg full_ff; + assign WriteQ = WrEn; + assign RdDeQ = RdEn; + assign DataOut = MemArray[RdPtr]; + assign almost_empty = almost_empty_ff; + assign almost_full = almost_full_ff; + assign empty = empty_ff; + assign full = full_ff; + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) + WrPtr <= 'd0; + else if (~sync_reset_n) + WrPtr <= 'd0; + else if (WrEn) begin + WrPtr <= WrPtr + 'd1; + end + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) + RdPtr <= 'd0; + else if (~sync_reset_n) + RdPtr <= 'd0; + else if (RdEn) begin + RdPtr <= RdPtr + 'd1; + end + end + + always @ (posedge clkin) begin + if (WrEn) + MemArray[WrPtr] <= DataIn; + end + + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) + FifoCntrWr <= 'd0; + else if (~sync_reset_n) + FifoCntrWr <= 'd0; + else if ((WrEn & RdDeQ) | (~WrEn & ~RdDeQ))begin + FifoCntrWr <= FifoCntrWr; + end + else if (WrEn) begin + FifoCntrWr <= FifoCntrWr +'d1; + end + else begin + FifoCntrWr <= FifoCntrWr -'d1; + end + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) + FifoCntrRd <= 'd0; + else if (~sync_reset_n) + FifoCntrRd <= 'd0; + else if ((RdEn & WriteQ) | (~RdEn & ~WriteQ)) begin + FifoCntrRd <= FifoCntrRd; + end + else if (WriteQ) begin + FifoCntrRd <= FifoCntrRd +'d1; + end + else begin + FifoCntrRd <= FifoCntrRd -'d1; + end + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) + empty_ff <= 1'b1; + else if (~sync_reset_n) + empty_ff <= 1'b1; + else if((FifoCntrRd==0) || ((FifoCntrRd==1) && RdEn)) + empty_ff <= 1'b1; + else if(FifoCntrRd>0) + empty_ff <= 1'b0; + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) + almost_empty_ff <= 1'b1; + else if (~sync_reset_n) + almost_empty_ff <= 1'b1; + else if(FifoCntrRd>(AE_THRESHOLD)) + almost_empty_ff <= 1'b0; + else if(FifoCntrRd<=(AE_THRESHOLD)) + almost_empty_ff <= 1'b1; + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) + full_ff <= 1'b0; + else if (~sync_reset_n) + full_ff <= 1'b0; + else if((FifoCntrWr==(BUF_DEPTH)) || ((FifoCntrWr==(BUF_DEPTH-1)) && WriteQ)) + full_ff <= 1'b1; + else if(FifoCntrWr<BUF_DEPTH) + full_ff <= 1'b0; + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) + almost_full_ff <= 1'b0; + else if (~sync_reset_n) + almost_full_ff <= 1'b0; + else if(FifoCntrWr>(AF_THRESHOLD)) + almost_full_ff <= 1'b1; + else if(FifoCntrWr<=(AF_THRESHOLD)) + almost_full_ff <= 1'b0; + end + endmodule + + module xdma_v4_1_4_GenericFIFOAsyncNoHead + #(parameter BUF_DATAWIDTH = 256, + parameter BUF_WE = BUF_DATAWIDTH/8, + parameter BUF_DEPTH = 512, + parameter BUF_PTR = (BUF_DEPTH <=2) ? 1: + (BUF_DEPTH <=4) ? 2: + (BUF_DEPTH <=8) ? 3: + (BUF_DEPTH <=16) ? 4: + (BUF_DEPTH <=32) ? 5: + (BUF_DEPTH <=64) ? 6: + (BUF_DEPTH <=128) ? 7: + (BUF_DEPTH <=256) ? 8: + (BUF_DEPTH <=512) ? 9: + (BUF_DEPTH <=1024) ? 10 : -1 + ) + ( + input clkin, + input reset_n, + input clkout, + input reseto_n, + input [BUF_DATAWIDTH-1:0] DataIn, + output [BUF_DATAWIDTH-1:0] DataOut, + input WrEn, + input RdEn, + output almost_empty, + output almost_full, + output empty, + output full + ); +(* ram_style = "DISTRIBUTED" *) + reg [BUF_DATAWIDTH-1:0] MemArray [BUF_DEPTH-1:0]; +(* max_fanout = 128 *) reg [BUF_PTR-1:0] WrPtr; +(* max_fanout = 128 *) reg [BUF_PTR-1:0] RdPtr; + reg [BUF_PTR:0] FifoCntrWr; + reg [BUF_PTR:0] FifoCntrRd; + wire WriteQ, RdDeQ; + reg almost_empty_ff; + reg almost_full_ff; + reg empty_ff; + reg full_ff; + assign WriteQ = WrEn; + assign RdDeQ = RdEn; + + assign DataOut = MemArray[RdPtr]; + + assign almost_empty = almost_empty_ff; + assign almost_full = almost_full_ff; + assign empty = empty_ff; + assign full = full_ff; + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + WrPtr <= 'd0; + end + else if (WrEn) begin + WrPtr <= WrPtr + 'd1; + end + end + + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + RdPtr <= 'd0; + end else if (RdEn) begin + RdPtr <= RdPtr + 'd1; + end + end + + always @ (posedge clkin) begin + if (WrEn) + MemArray[WrPtr] <= DataIn; + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + FifoCntrWr <= 'd0; + end + else if ((WrEn & RdDeQ) | (~WrEn & ~RdDeQ))begin + FifoCntrWr <= FifoCntrWr; + end + else if (WrEn) begin + FifoCntrWr <= FifoCntrWr +'d1; + end + else begin + FifoCntrWr <= FifoCntrWr -'d1; + end + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + FifoCntrRd <= 'd0; + end + else if ((RdEn & WriteQ) | (~RdEn & ~WriteQ)) begin + FifoCntrRd <= FifoCntrRd; + end + else if (WriteQ) begin + FifoCntrRd <= FifoCntrRd +'d1; + end + else begin + FifoCntrRd <= FifoCntrRd -'d1; + end + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + almost_empty_ff <= 1'b1; + empty_ff <= 1'b1; + end + else begin + if((FifoCntrRd==0) || ((FifoCntrRd==1) && RdEn)) begin + empty_ff <= 1'b1; + end + else if(FifoCntrRd>0) begin + empty_ff <= 1'b0; + end + + if((FifoCntrRd==0) || ((FifoCntrRd==1) && RdEn)) begin + almost_empty_ff <= 1'b1; + end + else if(FifoCntrRd>(BUF_DEPTH>>2)) begin + almost_empty_ff <= 1'b0; + end + else if(FifoCntrRd<=(BUF_DEPTH>>2)) begin + almost_empty_ff <= 1'b1; + end + end + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + almost_full_ff <= 1'b0; + full_ff <= 1'b0; + end + else begin + if((FifoCntrWr==(BUF_DEPTH)) || ((FifoCntrWr==(BUF_DEPTH-1)) && WriteQ)) begin + full_ff <= 1'b1; + end + else if (FifoCntrWr<BUF_DEPTH) begin + full_ff <= 1'b0; + end + + if((FifoCntrWr==(BUF_DEPTH)) || ((FifoCntrWr==(BUF_DEPTH-1)) && WriteQ)) begin + almost_full_ff <= 1'b1; + end + else if(FifoCntrWr>(BUF_DEPTH-2)) begin + almost_full_ff <= 1'b1; + end + else if(FifoCntrWr<=(BUF_DEPTH-2)) begin + almost_full_ff <= 1'b0; + end + end + end + endmodule + + module xdma_v4_1_4_GenericFIFOAsync + #(parameter BUF_DATAWIDTH = 256, + parameter BUF_WE = BUF_DATAWIDTH/8, + parameter BUF_DEPTH = 512, + parameter BUF_PTR = (BUF_DEPTH <=2) ? 1: + (BUF_DEPTH <=4) ? 2: + (BUF_DEPTH <=8) ? 3: + (BUF_DEPTH <=16) ? 4: + (BUF_DEPTH <=32) ? 5: + (BUF_DEPTH <=64) ? 6: + (BUF_DEPTH <=128) ? 7: + (BUF_DEPTH <=256) ? 8: + (BUF_DEPTH <=512) ? 9: + (BUF_DEPTH <=1024) ? 10 : -1, + parameter AE_THRESHOLD = BUF_DEPTH >> 2, + parameter AF_THRESHOLD = BUF_DEPTH - 2 + ) + ( + input clkin, + input reset_n, + input clkout, + input reseto_n, + input [BUF_DATAWIDTH-1:0] DataIn, + output [BUF_DATAWIDTH-1:0] DataOut, + input WrEn, + input RdEn, + output almost_empty, + output almost_full, + output empty, + output full + ); + +(* ram_style = "DISTRIBUTED" *) + reg [BUF_DATAWIDTH-1:0] MemArray [BUF_DEPTH-1:0]; +(* max_fanout = 128 *) reg [BUF_PTR-1:0] WrPtr; +(* max_fanout = 128 *) reg [BUF_PTR-1:0] RdPtr; + reg [BUF_PTR:0] FifoCntrWr; + reg [BUF_PTR:0] FifoCntrRd; + wire WriteQ, RdDeQ; + reg almost_empty_ff; + reg almost_full_ff; + reg empty_ff; + reg full_ff; + assign WriteQ = WrEn; + assign RdDeQ = RdEn; + + reg [BUF_DATAWIDTH-1:0] Head; + + assign almost_empty = almost_empty_ff; + assign almost_full = almost_full_ff; + assign empty = empty_ff; + assign full = full_ff; + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + WrPtr <= 'd0; + end + else if (WrEn) begin + WrPtr <= WrPtr + 'd1; + end + end + + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + RdPtr <= 'd0; + end + else if ((RdEn && (FifoCntrRd>1) ) || + (WrEn && (FifoCntrRd==0) ) || + (RdEn && WrEn && (FifoCntrRd==1)))begin + RdPtr <= RdPtr + 'd1; + end + end + + always @(posedge clkin) begin + if (WrEn) + MemArray[WrPtr] <= DataIn; + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + FifoCntrWr <= 'd0; + end + else if ((WrEn & RdDeQ) | (~WrEn & ~RdDeQ))begin + FifoCntrWr <= FifoCntrWr; + end + else if (WrEn) begin + FifoCntrWr <= FifoCntrWr +'d1; + end + else begin + FifoCntrWr <= FifoCntrWr -'d1; + end + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + FifoCntrRd <= 'd0; + end + else if ((RdEn & WriteQ) | (~RdEn & ~WriteQ)) begin + FifoCntrRd <= FifoCntrRd; + end + else if (WriteQ) begin + FifoCntrRd <= FifoCntrRd +'d1; + end + else begin + FifoCntrRd <= FifoCntrRd -'d1; + end + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + almost_empty_ff <= 1'b1; + empty_ff <= 1'b1; + end + else begin + if((FifoCntrRd==0) || ((FifoCntrRd==1) && RdEn)) begin + empty_ff <= 1'b1; + end + else if(FifoCntrRd>0) begin + empty_ff <= 1'b0; + end + + if((FifoCntrRd==0) || ((FifoCntrRd==1) && RdEn)) begin + almost_empty_ff <= 1'b1; + end + else if(FifoCntrRd>(AE_THRESHOLD)) begin + almost_empty_ff <= 1'b0; + end + else if(FifoCntrRd<=(AE_THRESHOLD)) begin + almost_empty_ff <= 1'b1; + end + end + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + almost_full_ff <= 1'b0; + full_ff <= 1'b0; + end + else begin + if((FifoCntrWr==(BUF_DEPTH)) || ((FifoCntrWr==(BUF_DEPTH-1)) && WriteQ)) begin + full_ff <= 1'b1; + end + else if (FifoCntrWr<BUF_DEPTH) begin + full_ff <= 1'b0; + end + + if((FifoCntrWr==(BUF_DEPTH)) || ((FifoCntrWr==(BUF_DEPTH-1)) && WriteQ)) begin + almost_full_ff <= 1'b1; + end + else if(FifoCntrWr>(AF_THRESHOLD)) begin + almost_full_ff <= 1'b1; + end + else if(FifoCntrWr<=(AF_THRESHOLD)) begin + almost_full_ff <= 1'b0; + end + end + end + + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + Head <= 1'b0; + end + else begin + if ((WrEn && (FifoCntrRd == 0)) || (WrEn && RdEn && (FifoCntrRd == 1))) + Head <= DataIn; + else if (RdEn || (FifoCntrRd == 0)) + Head <= MemArray[RdPtr]; + end + end + assign DataOut = Head; + + endmodule + + module xdma_v4_1_4_GenericFIFOHead + #(parameter BUF_DATAWIDTH = 256, + parameter BUF_WE = BUF_DATAWIDTH/8, + parameter BUF_DEPTH = 512, + parameter BUF_PTR = (BUF_DEPTH <=2) ? 1: + (BUF_DEPTH <=4) ? 2: + (BUF_DEPTH <=8) ? 3: + (BUF_DEPTH <=16) ? 4: + (BUF_DEPTH <=32) ? 5: + (BUF_DEPTH <=64) ? 6: + (BUF_DEPTH <=128) ? 7: + (BUF_DEPTH <=256) ? 8: + (BUF_DEPTH <=512) ? 9: + (BUF_DEPTH <=1024) ? 10 : -1, + parameter AE_THRESHOLD = BUF_DEPTH >> 2, + parameter AF_THRESHOLD = BUF_DEPTH - 2 + ) + ( + input clkin, + input reset_n, + input sync_reset_n, + input [BUF_DATAWIDTH-1:0] DataIn, + output [BUF_DATAWIDTH-1:0] DataOut, + input WrEn, + input WrAlloc, + input RdEn, + output almost_empty, + output almost_full, + output empty, + output full + ); + +(* ram_style = "DISTRIBUTED" *) + reg [BUF_DATAWIDTH-1:0] MemArray [BUF_DEPTH-1:0]; +(* max_fanout = 128 *) reg [BUF_PTR-1:0] WrPtr; +(* max_fanout = 128 *) reg [BUF_PTR-1:0] RdPtr; + reg [BUF_PTR:0] FifoCntrWr; + reg [BUF_PTR:0] FifoCntrRd; + wire WriteQ, RdDeQ; + reg almost_empty_ff; + reg almost_full_ff; + reg empty_ff; + reg full_ff; + assign WriteQ = WrEn; + assign RdDeQ = RdEn; + + reg [BUF_DATAWIDTH-1:0] Head; + + assign almost_empty = almost_empty_ff; + assign almost_full = almost_full_ff; + assign empty = empty_ff; + assign full = full_ff; + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + WrPtr <= 'd0; + end + else if (~sync_reset_n) + WrPtr <= 'd0; + else if (WrEn) begin + WrPtr <= WrPtr + 'd1; + end + end + + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + RdPtr <= 'd0; + end + else if (~sync_reset_n) + RdPtr <= 'd0; + else if ((RdEn && (FifoCntrRd>1) ) || + (WrEn && (FifoCntrRd==0) ) || + (RdEn && WrEn && (FifoCntrRd==1)))begin + RdPtr <= RdPtr + 'd1; + end + end + + always @(posedge clkin) begin + if (WrEn) + MemArray[WrPtr] <= DataIn; + end + + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + FifoCntrWr <= 'd0; + end + else if (~sync_reset_n) + FifoCntrWr <= 'd0; + else if ((WrAlloc & RdDeQ) | (~WrAlloc & ~RdDeQ))begin + FifoCntrWr <= FifoCntrWr; + end + else if (WrAlloc) begin + FifoCntrWr <= FifoCntrWr +'d1; + end + else begin + FifoCntrWr <= FifoCntrWr -'d1; + end + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + FifoCntrRd <= 'd0; + end + else if (~sync_reset_n) + FifoCntrRd <= 'd0; + else if ((RdEn & WriteQ) | (~RdEn & ~WriteQ)) begin + FifoCntrRd <= FifoCntrRd; + end + else if (WriteQ) begin + FifoCntrRd <= FifoCntrRd +'d1; + end + else begin + FifoCntrRd <= FifoCntrRd -'d1; + end + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + almost_empty_ff <= 1'b1; + empty_ff <= 1'b1; + end + else if (~sync_reset_n) begin + almost_empty_ff <= 1'b1; + empty_ff <= 1'b1; + end + else begin + if((FifoCntrRd==0) || ((FifoCntrRd==1) && RdEn)) begin + empty_ff <= 1'b1; + end + else if(FifoCntrRd>0) begin + empty_ff <= 1'b0; + end + + if((FifoCntrRd==0) || ((FifoCntrRd==1) && RdEn)) begin + almost_empty_ff <= 1'b1; + end + else if(FifoCntrRd>(AE_THRESHOLD)) begin + almost_empty_ff <= 1'b0; + end + else if(FifoCntrRd<=(AE_THRESHOLD)) begin + almost_empty_ff <= 1'b1; + end + end + end + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + almost_full_ff <= 1'b0; + full_ff <= 1'b0; + end + else if (~sync_reset_n) begin + almost_full_ff <= 1'b0; + full_ff <= 1'b0; + end + else begin + if((FifoCntrWr==(BUF_DEPTH)) || ((FifoCntrWr==(BUF_DEPTH-1)) && WriteQ)) begin + full_ff <= 1'b1; + end + else if (FifoCntrWr<BUF_DEPTH) begin + full_ff <= 1'b0; + end + + if((FifoCntrWr==(BUF_DEPTH)) || ((FifoCntrWr==(BUF_DEPTH-1)) && WriteQ)) begin + almost_full_ff <= 1'b1; + end + else if((FifoCntrWr>AF_THRESHOLD) || ((FifoCntrWr == AF_THRESHOLD) && WriteQ)) begin + almost_full_ff <= 1'b1; + end + else if(FifoCntrWr<=(AF_THRESHOLD)) begin + almost_full_ff <= 1'b0; + end + end + end + + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + Head <= 1'b0; + end + else if (~sync_reset_n) begin + Head <= 1'b0; + end + else begin + if ((WrEn && (FifoCntrRd == 0)) || (WrEn && RdEn && (FifoCntrRd == 1))) + Head <= DataIn; + else if (RdEn || (FifoCntrRd == 0)) + Head <= MemArray[RdPtr]; + end + end + assign DataOut = Head; + + endmodule + + module xdma_v4_1_4_GenericFIFOHead2 + #(parameter BUF_DATAWIDTH = 256, + parameter BUF_WE = BUF_DATAWIDTH/8, + parameter BUF_DEPTH = 512, + parameter BUF_PTR = (BUF_DEPTH <=2) ? 1: + (BUF_DEPTH <=4) ? 2: + (BUF_DEPTH <=8) ? 3: + (BUF_DEPTH <=16) ? 4: + (BUF_DEPTH <=32) ? 5: + (BUF_DEPTH <=64) ? 6: + (BUF_DEPTH <=128) ? 7: + (BUF_DEPTH <=256) ? 8: + (BUF_DEPTH <=512) ? 9: + (BUF_DEPTH <=1024) ? 10 : -1, + parameter AE_THRESHOLD = BUF_DEPTH >> 2, + parameter AF_THRESHOLD = BUF_DEPTH - 2 + ) + ( + input clkin, + input reset_n, + input sync_reset_n, + input [BUF_DATAWIDTH-1:0] DataIn, + output [BUF_DATAWIDTH-1:0] DataOut, + input WrEn, + input RdEn, + output almost_empty, + output almost_full, + output empty, + output full + ); + +(* ram_style = "DISTRIBUTED" *) + reg [BUF_DATAWIDTH-1:0] MemArray [BUF_DEPTH-1:0]; +(* max_fanout = 128 *) reg [BUF_PTR-1:0] WrPtr; +(* max_fanout = 128 *) reg [BUF_PTR-1:0] RdPtr; + reg [BUF_PTR:0] FifoCntrWr; + reg [BUF_PTR:0] FifoCntrRd; + wire WriteQ, RdDeQ; + reg almost_empty_ff; + reg almost_full_ff; + reg empty_ff; + reg full_ff; + assign WriteQ = WrEn; + assign RdDeQ = RdEn; + + reg [BUF_DATAWIDTH-1:0] Head; + + assign almost_empty = almost_empty_ff; + assign almost_full = almost_full_ff; + assign empty = empty_ff; + assign full = full_ff; + + `XLREG_XDMA (clkin, reset_n) + begin + if (~reset_n) + WrPtr <= 'd0; + else if (~sync_reset_n) + WrPtr <= 'd0; + else if (WrEn && (BUF_DEPTH > 1)) begin + WrPtr <= WrPtr + 'd1; + end + end + + `XLREG_XDMA (clkin, reset_n) + begin + if (~reset_n) + RdPtr <= 'd0; + else if (~sync_reset_n) begin + RdPtr <= 'd0; + end + else if (BUF_DEPTH > 1) + begin + if ((RdEn && (FifoCntrRd>1) ) || + (WrEn && (FifoCntrRd==0) ) || + (RdEn && WrEn && (FifoCntrRd==1)))begin + RdPtr <= RdPtr + 'd1; + end + end + end + + always @(posedge clkin) begin + if (WrEn) + MemArray[WrPtr] <= DataIn; + end + + `XLREG_XDMA (clkin, reset_n) + begin + if (~reset_n) + FifoCntrWr <= 'd0; + else if (~sync_reset_n) + FifoCntrWr <= 'd0; + else if ((WrEn & RdDeQ) | (~WrEn & ~RdDeQ))begin + FifoCntrWr <= FifoCntrWr; + end + else if (WrEn) begin + FifoCntrWr <= FifoCntrWr +'d1; + end + else begin + FifoCntrWr <= FifoCntrWr -'d1; + end + end + `XLREG_XDMA (clkin, reset_n) + begin + if (~reset_n) begin + FifoCntrRd <= 'd0; + end + else if (~sync_reset_n) begin + FifoCntrRd <= 'd0; + end + else if ((RdEn & WriteQ) | (~RdEn & ~WriteQ)) begin + FifoCntrRd <= FifoCntrRd; + end + else if (WriteQ) begin + FifoCntrRd <= FifoCntrRd +'d1; + end + else begin + FifoCntrRd <= FifoCntrRd -'d1; + end + end + `XLREG_XDMA (clkin, reset_n) + begin + if (~reset_n) begin + almost_empty_ff <= 1'b1; + empty_ff <= 1'b1; + end + else if (~sync_reset_n) begin + almost_empty_ff <= 1'b1; + empty_ff <= 1'b1; + end + else begin + if(((FifoCntrRd==0) && ~WrEn) || ((FifoCntrRd==1) && RdEn && ~WrEn)) begin + empty_ff <= 1'b1; + end + else begin + empty_ff <= 1'b0; + end + + if((FifoCntrRd==0) || ((FifoCntrRd==1) && RdEn && ~WrEn)) begin + almost_empty_ff <= 1'b1; + end + else if(FifoCntrRd>(AE_THRESHOLD)) begin + almost_empty_ff <= 1'b0; + end + else if(FifoCntrRd<=(AE_THRESHOLD)) begin + almost_empty_ff <= 1'b1; + end + end + end + + `XLREG_XDMA (clkin, reset_n) + begin + if (~reset_n) begin + almost_full_ff <= 1'b0; + full_ff <= 1'b0; + end + else if (~sync_reset_n) begin + almost_full_ff <= 1'b0; + full_ff <= 1'b0; + end + else begin + if(((FifoCntrWr==(BUF_DEPTH+1)) && (~RdEn || WriteQ)) || ((FifoCntrWr==BUF_DEPTH) && WriteQ && ~RdEn)) begin + full_ff <= 1'b1; + end + else + begin + full_ff <= 1'b0; + end + + if((FifoCntrWr>(BUF_DEPTH)) || ((FifoCntrWr==BUF_DEPTH) && WriteQ)) begin + almost_full_ff <= 1'b1; + end + else if((FifoCntrWr>AF_THRESHOLD) || ((FifoCntrWr == AF_THRESHOLD) && WriteQ)) begin + almost_full_ff <= 1'b1; + end + else if(FifoCntrWr<=(AF_THRESHOLD)) begin + almost_full_ff <= 1'b0; + end + end + end + + `XLREG_XDMA(clkin, reset_n) begin + if (~reset_n) begin + Head <= 1'b0; + end + else if (~sync_reset_n) begin + Head <= 1'b0; + end + else begin + if ((WrEn && (FifoCntrRd == 0)) || (WrEn && RdEn && (FifoCntrRd == 1))) + Head <= DataIn; + else if (RdEn || (FifoCntrRd == 0)) + Head <= MemArray[RdPtr]; + end + end + assign DataOut = Head; + + endmodule + +/* +module xdma_v4_1_4_GenericBRAMFIFOHead #( + parameter TCQ = 0, + parameter BUF_DATAWIDTH = 256, + parameter BUF_WE = BUF_DATAWIDTH/8, + parameter BUF_DEPTH = 512, + parameter BUF_PTR = (BUF_DEPTH <=2) ? 1: + (BUF_DEPTH <=4) ? 2: + (BUF_DEPTH <=8) ? 3: + (BUF_DEPTH <=16) ? 4: + (BUF_DEPTH <=32) ? 5: + (BUF_DEPTH <=64) ? 6: + (BUF_DEPTH <=128) ? 7: + (BUF_DEPTH <=256) ? 8: + (BUF_DEPTH <=512) ? 9: + (BUF_DEPTH <=1024) ? 10 : -1, + parameter AE_THRESHOLD = BUF_DEPTH >> 2, + parameter AF_THRESHOLD = BUF_DEPTH - 2 + ) + ( + input clk, + input rst, + input srst, + input [BUF_DATAWIDTH-1:0] DataIn, + output [BUF_DATAWIDTH-1:0] DataOut, + input WrEn, + input RdEn, + output almost_empty, + output almost_full, + output empty, + output full + ); + +(* ram_style = "BLOCK" *) +reg [BUF_DATAWIDTH-1:0] MemArray [BUF_DEPTH-1:0]; + +reg [BUF_PTR-1:0] WrPtr; +reg [BUF_PTR-1:0] WrPtr_nxt; + +reg [BUF_PTR-1:0] RdPtr_nxt; +reg [BUF_PTR-1:0] RdPtr; + +reg [BUF_PTR:0] FifoCntr_nxt; +reg [BUF_PTR:0] FifoCntr; + +reg almost_empty_nxt; +reg almost_empty_ff; +reg almost_full_nxt; +reg almost_full_ff; +reg empty_nxt; +reg empty_ff; +reg full_nxt; +reg full_ff; + +wire [BUF_DATAWIDTH-1:0] Head_nxt; +reg [BUF_DATAWIDTH-1:0] Head; + +assign almost_empty = almost_empty_ff; +assign almost_full = almost_full_ff; +assign empty = empty_ff; +assign full = full_ff; + +always @(*) begin + WrPtr_nxt = WrPtr; + if (srst) + WrPtr_nxt = 'h0; + else if (WrEn) + WrPtr_nxt = WrPtr + 'd1; +end +`XSRREG_XDMA(clk, ~rst, WrPtr, WrPtr_nxt, 'h0) + +always @(*) begin + RdPtr_nxt = RdPtr; + if (srst) begin + RdPtr_nxt = 'h0; + end + else if ((RdEn && (FifoCntr > 1) ) || + (WrEn && (FifoCntr == 0) ) || + (RdEn && WrEn && (FifoCntr == 1)))begin + RdPtr_nxt = RdPtr + 'd1; + end + end +`XSRREG_XDMA(clk, ~rst, RdPtr, RdPtr_nxt, 'h0) + +always @(posedge clk) begin + if (WrEn) + MemArray[WrPtr] <= DataIn; +end + +always @(*) begin + FifoCntr_nxt = FifoCntr; + if (srst) + FifoCntr_nxt = 'd0; + else if ((RdEn & WrEn) | (~RdEn & ~WrEn)) + FifoCntr_nxt = FifoCntr; + else if (WrEn) + FifoCntr_nxt = FifoCntr +'d1; + else + FifoCntr_nxt = FifoCntr -'d1; +end +`XSRREG_XDMA(clk, ~rst, FifoCntr, FifoCntr_nxt, 'h0) + +always @(*) begin + almost_empty_nxt = almost_empty_ff; + empty_nxt = empty_ff; + + if (srst) begin + almost_empty_nxt= 1'b1; + empty_nxt = 1'b1; + end + else begin + if((FifoCntr==0) || ((FifoCntr==1) && RdEn)) + empty_nxt = 1'b1; + else if(FifoCntr > 0) + empty_nxt = 1'b0; + + if((FifoCntr==0) || ((FifoCntr==1) && RdEn)) + almost_empty_nxt = 1'b1; + else if(FifoCntr > AE_THRESHOLD) + almost_empty_nxt = 1'b0; + else if(FifoCntr <= AE_THRESHOLD) + almost_empty_nxt = 1'b1; + end +end +`XSRREG_XDMA(clk, ~rst, almost_empty_ff, almost_empty_nxt, 'h0) +`XSRREG_XDMA(clk, ~rst, empty_ff, empty_nxt, 'h0) + + +always @(*) begin + full_nxt = full_ff; + almost_full_nxt = almost_full_ff; + if (srst) begin + almost_full_nxt = 1'b0; + full_nxt = 1'b0; + end + else begin + if((FifoCntr==(BUF_DEPTH)) || ((FifoCntr==(BUF_DEPTH-1)) && WrEn)) + full_nxt = 1'b1; + else if (FifoCntr<BUF_DEPTH) + full_nxt = 1'b0; + + if((FifoCntr==(BUF_DEPTH)) || ((FifoCntr==(BUF_DEPTH-1)) && WrEn)) + almost_full_nxt = 1'b1; + else if(FifoCntr > AF_THRESHOLD) + almost_full_nxt = 1'b1; + else if(FifoCntr <= AF_THRESHOLD) + almost_full_nxt = 1'b0; + end +end +`XSRREG_XDMA(clk, ~rst, almost_full_ff, almost_full_nxt, 'h0) +`XSRREG_XDMA(clk, ~rst, full_ff, full_nxt, 'h0) + +assign Head_nxt = (srst) ? 'h0 : + ((WrEn && (FifoCntr == 0)) || (WrEn && RdEn && (FifoCntr == 1))) ? DataIn : + (RdEn || (FifoCntr == 0)) ? MemArray[RdPtr] : + Head; + +`XSRREG_XDMA(clk, ~rst, Head, Head_nxt, 'h0) +assign DataOut = Head; + +endmodule +*/ +`endif // AXI_BRIDGE_VH diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_defines.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_defines.svh new file mode 100755 index 0000000..e28c67b --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_defines.svh @@ -0,0 +1,386 @@ +`ifndef DMA_DEFINES_SVH +`define DMA_DEFINES_SVH + +`include "dma_defines.vh" +`include "pcie_dma_attr_defines.svh" + +// Interface Includes at bottom of file (use some structures defined in this file) + +`define IF_MI_CONVERSION_M \ + always_comb begin \ + ifc.wadr = wadr;\ + ifc.wen = wen;\ + ifc.wpar = wpar;\ + ifc.wdat = wdat;\ + ifc.ren = ren;\ + ifc.radr = radr;\ + rpar = ifc.rpar;\ + rdat = ifc.rdat;\ + rsbe = ifc.rsbe;\ + rdbe = ifc.rdbe;\ + end + +`define IF_MI_CONVERSION_S \ + always_comb begin \ + wadr = ifc.wadr;\ + wen = ifc.wen;\ + wpar = ifc.wpar;\ + wdat = ifc.wdat;\ + ren = ifc.ren;\ + radr = ifc.radr;\ + ifc.rpar = rpar;\ + ifc.rdat = rdat;\ + ifc.rsbe = rsbe;\ + ifc.rdbe = rdbe;\ + end + +typedef struct packed { + logic spl; + logic [`ADR_WIDTH-1:0] adr; + logic [`RID_WIDTH-1:0] rid; + logic [`LEN_WIDTH-1:0] byte_len; // byte length + logic [`DID_WIDTH-1:0] did; + logic [7:0] fnc; // function +} rrq_t; + +// Descriptor Sideband Info (Context RAM to DSC_CPLI_RAM) +typedef struct packed { + logic wbi; // Do writeback/interrupt on descriptor completion + logic wbi_chk; // Check status before writeback/interrupt + logic [`QID_WIDTH-1:0] qid; // Q ID + logic [3:0] qst; + logic [7:0] fnc; + logic [15:0] cidx; +} dsc_sbi_t; // 10 + 4 + 8 + 16 = 54 + +typedef struct packed { + logic sop; + logic eop; + logic wbk; + logic [4:0] err; + logic [3:0] errc; + //logic [`DAT_WIDTH/32-1:0] wen; // dword write enable + logic [`RID_WIDTH-1:0] rid; + logic [`DID_WIDTH-1:0] did; + logic [5:0] lba; // Last beat length adjustment (AXI ST C2H) + logic [`DAT_WIDTH/8-1:0] par; + logic [`DAT_WIDTH-1:0] dat; +} rcp_t; + +typedef struct packed { + logic err; + logic [`ADR_WIDTH-1:0] adr; + logic [`RID_WIDTH-1:0] rid; + logic [`LEN_WIDTH-1:0] byte_len; // byte length + logic [5:0] aln; // Source alignment + logic eop; + logic eod; + logic eor; +} wrq_t; + +typedef struct packed { + logic [`DAT_WIDTH/8-1:0] par; + logic [`DAT_WIDTH-1:0] dat; +} wpl_t; + +typedef struct packed { + logic [`RID_WIDTH-1:0] rid; + logic [4:0] err; +} wcp_t; + +typedef struct packed { + logic [31:0] dat; +} wbrq_t; + +typedef struct packed { + logic [3:0] be; + logic rd; + logic wr; + logic [31:0] dat; + logic [31:0] adr; + logic [7:0] func; +} trq_t; + +typedef struct packed { + logic vld; + logic [31:0] dat; +} tcp_t; + +typedef struct packed { + logic run; + logic c2h_wbk_ena; + logic noninc; + logic [`ADR_WIDTH-1:0] cdc_wbk_adr; +} creg_t; + +typedef struct packed { + logic [63:0] par; // 136:73 Parity filled later + logic [5:0] seq1; // 72:67 Sequence Num 1 + logic [5:0] seq0; // 66:61 Sequence Num 0 + logic [23:0] tph; // 60:45 TPH St Tag + // 44:43 TPH Ind Tag + // 42:39 TPH Type + // 38:37 TPH Present + logic disc; // 36 Discontinue + logic [3:0] eop1_ptr; // 35:32 EOP 1 Ptr + logic [3:0] eop0_ptr; // 31:28 EOP 0 Ptr + logic eop1; // 27 EOP 1 + logic eop0; // 26 EOP 0 + logic [1:0] sop1_ptr; // 25:24 SOP 1 Ptr + logic [1:0] sop0_ptr; // 23:22 SOP 0 Ptr + logic sop1; // 21 SOP 1 + logic sop0; // 20 SOP 0 + logic [3:0] adr; // 19:16 Address offset - Address aligned mode only + logic [3:0] lbe1; + logic [3:0] lbe0; + logic [3:0] fbe1; + logic [3:0] fbe0; +} rq_usr_straddle_t; + +typedef struct packed { + logic [76:0] rsv; + logic [31:0] par; // 59:28 + logic [3:0] seq; // 27:24 + logic [11:0] tph; // 23:12 + logic dis; // 11 + logic [2:0] adr; // 10:8 + logic [3:0] lbe; // 7:4 + logic [3:0] fbe; // 3:0 +} rq_usr_nostraddle_t; + +typedef union packed { + rq_usr_straddle_t rqu_str; + rq_usr_nostraddle_t rqu_nstr; +} rq_usr_t; + +typedef struct packed { + logic [12:0] pcie_mrrs; + logic [12:0] pcie_mps; + logic [12:0] axi_mrrs; + logic [12:0] axi_mps; +} cfg_dma_t; + +typedef struct packed { + logic ecrc; + logic [2:0] attr; + logic [2:0] tc; + logic rid_en; + logic [15:0] cpl_id; + logic [7:0] tag; + logic [15:0] req_id; + logic poison; + logic [3:0] req; + logic [10:0] len; + logic [63:0] adr; +} rq_hdr_fields_t; + +typedef struct packed { + logic [23:0] dw3_misc; + logic [7:0] tag; + logic [16:0] dw2_misc; + logic [3:0] req; + logic [10:0] len; + logic [63:0] adr; +} rq_hdr_compact_t; + +typedef struct packed { + logic [31:0] dw3; + logic [31:0] dw2; + logic [31:0] dw1; + logic [31:0] dw0; +} rq_hdr_dwords_t; + +typedef union packed { + rq_hdr_fields_t rqh_f; + rq_hdr_compact_t rqh_c; + rq_hdr_dwords_t rqh_d; +} rq_hdr_t; + +typedef struct packed { + logic tlast; + logic [`MULTQ_C2H_TUSER_WIDTH-1:0] tuser; + logic [`DAT_WIDTH/8-1:0] tkeep; + logic [`DAT_WIDTH/8-1:0] tparity; + logic [`DAT_WIDTH-1:0] tdata; +} dma_s_axis_t; + +typedef struct packed { + logic [`DID_WIDTH-1:0] waddr; + logic [`DID_WIDTH-1:0] raddr; + logic [`DAT_WIDTH/8-1:0] wen; +} dat_bram_cmd_t; + +typedef struct packed { + logic [`DAT_WIDTH-1:0] dat; + logic [`DAT_WIDTH/8-1:0] parity; // Even parity +}dat_bram_dat_t; + + +typedef struct packed { + + logic tlast; + logic [`MULTQ_H2C_TUSER_WIDTH-1:0] tuser; + logic [`DAT_WIDTH/8-1:0] tkeep; + logic [`DAT_WIDTH/8-1:0] tparity; + logic [`DAT_WIDTH-1:0] tdata; +} dma_m_axis_t; + + +// Descriptor Completion Memory Interface +typedef struct packed { + logic [`DAT_WIDTH-1:0] rdat; + logic rbe; +}dsc_cpl_bram_out_t; + +typedef struct packed { + logic wen; + logic [`DSC_DID_WIDTH-1:0] waddr; + logic [`DAT_WIDTH-1:0] wdat; + logic [`DSC_RID_WIDTH-1:0] raddr; +}dsc_cpl_bram_in_t; + +// XDMA Descriptor Memory Interface +//typedef struct packed { + //logic [255:0] rdat; + //logic rbe; +//}dsc_bram_out_t; + +typedef struct packed { + logic wen; + logic [`DSC_DID_WIDTH-1:0] waddr; + logic [255:0] wdat; + logic [`DSC_RID_WIDTH-1:0] raddr; +}dsc_bram_in_t; + + +// +typedef struct packed { + logic [7:0] func; + //logic [3:0] be; +} dma_axil_user_t; + +// Descriptor Completion +typedef struct packed { + logic [63:0] wadr; + logic [63:0] radr; + logic [27:0] len; + logic eop; + logic cpl; + logic stp; +} dcp_t; + +// Descriptor In (user descriptors -> dma) +typedef struct packed { + logic [`QID_WIDTH-1:0] qid; // Q ID + logic [1:0] chn; // Channel + logic [3:0] qst; // Q status + logic [2:0] fmt; // Format + logic [255:0] dsc; + logic [3:0] vld; +} dma_dsc_in_t; + +// Descriptor In Credits (dma credits -> user) +typedef struct packed { + logic vld; + logic [8:0] num; + logic [`QID_WIDTH-1:0] qid; +} dma_dsc_in_crd_t; + +// Descriptor Out (dma descriptors -> user) +typedef struct packed { + logic wbi; + logic wbi_chk; + logic [15:0] cidx; + logic [`QID_WIDTH-1:0] qid; // Q ID + logic [1:0] chn; // Channel + logic [3:0] qst; // Q status + logic [2:0] siz; // Format + logic dir; // Direction + logic [3:0] vld; + logic [255:0] dsc; +} dma_dsc_block_t; + +typedef struct packed { + logic wbi; + logic wbi_chk; + logic [15:0] cidx; + logic [`QID_WIDTH-1:0] qid; // Q ID + logic [1:0] chn; // Channel + logic [3:0] qst; // Q status + logic [2:0] siz; // Format + logic dir; // Direction + logic [255:0] dsc; +} dma_dsc_t; + +// Descriptor Out Credits (user credits -> dma) +typedef struct packed { + logic vld; + logic [8:0] num; + logic [`QID_WIDTH-1:0] qid; + logic [1:0] chn; + logic clr; +} dma_dsc_out_crd_t; + + +// Interface Conversion + +`define PCIE_CC_TO_DMA_CC_IF(pcie_cc, dma_cc) \ +assign pcie_cc.axis_cc_tvalid = dma_cc.tvalid; \ +assign pcie_cc.axis_cc_tdata = 'h0 | dma_cc.tdata; \ +assign pcie_cc.axis_cc_tuser = 'h0 | dma_cc.tuser; \ +assign pcie_cc.axis_cc_tkeep = 'h0 | dma_cc.tkeep; \ +assign pcie_cc.axis_cc_tlast = dma_cc.tlast; \ +assign dma_cc.tready = 'h0 | pcie_cc.axis_cc_tready; + +`define PCIE_CQ_TO_DMA_CQ_IF(pcie_cq, dma_cq) \ +assign dma_cq.tvalid = | pcie_cq.axis_cq_tvalid; \ +assign dma_cq.tdata = 'h0 | pcie_cq.axis_cq_tdata; \ +assign dma_cq.tuser = 'h0 | pcie_cq.axis_cq_tuser; \ +assign dma_cq.tkeep = 'h0 | pcie_cq.axis_cq_tkeep; \ +assign dma_cq.tlast = | pcie_cq.axis_cq_tlast; \ +assign pcie_cq.axis_cq_tready = 'h0 | dma_cq.tready; + +`define PCIE_RC_TO_DMA_RC_IF(pcie_rc, dma_rc) \ +assign dma_rc.tvalid = | pcie_rc.axis_rc_tvalid; \ +assign dma_rc.tdata = 'h0 | pcie_rc.axis_rc_tdata; \ +assign dma_rc.tuser = 'h0 | pcie_rc.axis_rc_tuser; \ +assign dma_rc.tkeep = 'h0 | pcie_rc.axis_rc_tkeep; \ +assign dma_rc.tlast = | pcie_rc.axis_rc_tlast; \ +assign pcie_rc.axis_rc_tready = 'h0 | dma_rc.tready; + +`define PCIE_RQ_TO_DMA_RQ_IF(pcie_rq, dma_rq) \ +assign pcie_rq.axis_rq_tvalid = dma_rq.tvalid; \ +assign pcie_rq.axis_rq_tdata = 'h0 | dma_rq.tdata; \ +assign pcie_rq.axis_rq_tuser = 'h0 | dma_rq.tuser; \ +assign pcie_rq.axis_rq_tkeep = 'h0 | dma_rq.tkeep; \ +assign pcie_rq.axis_rq_tlast = dma_rq.tlast; \ +assign dma_rq.tready = 'h0 | pcie_rq.axis_rq_tready; + +`include "dma_pcie_axis_cc_if.svh" +`include "dma_pcie_axis_cq_if.svh" +`include "dma_pcie_axis_rc_if.svh" +`include "dma_pcie_axis_rq_if.svh" +//`include "dma_pcie_c2h_axis_if.svh" +`include "dma_pcie_c2h_crdt_if.svh" +`include "dma_pcie_dsc_in_if.svh" +`include "dma_pcie_dsc_out_if.svh" +`include "dma_pcie_fabric_input_if.svh" +`include "dma_pcie_fabric_output_if.svh" +`include "dma_pcie_gic_if.svh" +//`include "dma_pcie_h2c_axis_if.svh" +`include "dma_pcie_h2c_crdt_if.svh" +`include "dma_pcie_mi_16Bx2048_4Bwe_ram_if.svh" +`include "dma_pcie_mi_2Bx2048_ram_if.svh" +`include "dma_pcie_mi_4Bx2048_4Bwe_ram_if.svh" +`include "dma_pcie_mi_64Bx128_32Bwe_ram_if.svh" +`include "dma_pcie_mi_64Bx256_32Bwe_ram_if.svh" +`include "dma_pcie_mi_64Bx512_32Bwe_ram_if.svh" +`include "dma_pcie_mi_64Bx1024_32Bwe_ram_if.svh" +`include "dma_pcie_mi_8Bx2048_4Bwe_ram_if.svh" +`include "dma_pcie_mi_dsc_cpld_if.svh" +`include "dma_pcie_mi_dsc_cpli_if.svh" +`include "dma_pcie_misc_input_if.svh" +`include "dma_pcie_misc_output_if.svh" +`endif + + diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_defines.vh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_defines.vh new file mode 100755 index 0000000..7323a0b --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_defines.vh @@ -0,0 +1,33 @@ +`ifndef DMA_DEFINES_VH +`define DMA_DEFINES_VH + +`include "dma_soft_defines.vh" + +`define CPLI_WIDTH 80 + +`define DAT_WIDTH 512 +`define ADR_WIDTH 64 +`define ALN_WIDTH 4 // Bits used for subbeat dword alignment +`define LEN_WIDTH 28 +`define RID_WIDTH 10 +`define DID_WIDTH 10 +`define QID_WIDTH 8 // Support for 128 H2C and 128 C2H queues +`define DSC_RID_WIDTH 16 +`define DSC_DID_WIDTH 16 + +`define H2C_TAR_ID 0 +`define C2H_TAR_ID 1 +`define IRQ_TAR_ID 2 +`define CFG_TAR_ID 3 +`define DSC_H2C_TAR_ID 4 +`define DSC_C2H_TAR_ID 5 +`define DSC_TAR_ID 6 +//`define MSIX_TAR_ID 8 +//`define PF1_MSIX_TAR_ID 9 + +`define MSIX_PBA_OFFSET 12'hfe0 + +`define MULTQ_C2H_TUSER_WIDTH 64 +`define MULTQ_H2C_TUSER_WIDTH 64 + +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_cc_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_cc_if.svh new file mode 100755 index 0000000..a1e6b25 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_cc_if.svh @@ -0,0 +1,35 @@ +`ifndef iF_AXIS_CC_PCIE_DMA_PORT_VS +`define iF_AXIS_CC_PCIE_DMA_PORT_VS +interface dma_pcie_axis_cc_if#(DATA_WIDTH = 512, USER_WIDTH = 81)(); + + wire [DATA_WIDTH-1:0] tdata; + wire [USER_WIDTH-1:0] tuser; + wire tlast; + wire [DATA_WIDTH/32-1:0] tkeep; + wire tvalid; + wire tready; + + modport s ( + + input tdata + ,input tuser + ,input tlast + ,input tkeep + ,input tvalid + ,output tready + + ); + + modport m ( + + output tdata + ,output tuser + ,output tlast + ,output tkeep + ,output tvalid + ,input tready + + ); + +endinterface : dma_pcie_axis_cc_if +`endif // iF_AXIS_CC_PCIE_PORT_VS diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_cq_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_cq_if.svh new file mode 100755 index 0000000..f92954b --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_cq_if.svh @@ -0,0 +1,35 @@ +`ifndef IF_AXIS_CQ_PCIE_DMA_PORT_SV +`define IF_AXIS_CQ_PCIE_DMA_PORT_SV +interface dma_pcie_axis_cq_if#(DATA_WIDTH = 512, USER_WIDTH = 183)(); + + wire [DATA_WIDTH-1:0] tdata; + wire [USER_WIDTH-1:0] tuser; + wire tlast; + wire [DATA_WIDTH/32-1:0] tkeep; + wire tvalid; + wire [21:0] tready; + + modport m ( + + output tdata + ,output tuser + ,output tlast + ,output tkeep + ,output tvalid + ,input tready + + ); + + modport s ( + + input tdata + ,input tuser + ,input tlast + ,input tkeep + ,input tvalid + ,output tready + + ); + +endinterface : dma_pcie_axis_cq_if +`endif // IF_AXIS_CQ_PCIE_DMA_PORT_SV diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_rc_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_rc_if.svh new file mode 100755 index 0000000..20a2184 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_rc_if.svh @@ -0,0 +1,35 @@ +`ifndef IF_AXIS_RC_PCIE_DMA_PORT_VS +`define IF_AXIS_RC_PCIE_DMA_PORT_VS +interface dma_pcie_axis_rc_if#(DATA_WIDTH = 512, USER_WIDTH = 161)(); + + wire [DATA_WIDTH-1:0] tdata; + wire tlast; + wire [USER_WIDTH-1:0] tuser; + wire [DATA_WIDTH/32-1:0] tkeep; + wire tvalid; + wire [21:0] tready; + + modport m ( + + output tdata + ,output tlast + ,output tuser + ,output tkeep + ,output tvalid + ,input tready + + ); + + modport s ( + + input tdata + ,input tlast + ,input tuser + ,input tkeep + ,input tvalid + ,output tready + + ); + +endinterface : dma_pcie_axis_rc_if +`endif // PCIE4_IF_AXIS_RC_PCIE_PORT diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_rq_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_rq_if.svh new file mode 100755 index 0000000..bad7df2 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_axis_rq_if.svh @@ -0,0 +1,35 @@ +`ifndef IF_AXIS_RQ_PCIE_DMA_PORT_SV +`define IF_AXIS_RQ_PCIE_DMA_PORT_SV +interface dma_pcie_axis_rq_if#(DATA_WIDTH = 512, USER_WIDTH = 137)(); + + wire [DATA_WIDTH-1:0] tdata; + wire tlast; + wire [USER_WIDTH-1:0] tuser; + wire [DATA_WIDTH/32-1:0] tkeep; + wire tvalid; + wire tready; + + modport s ( + + input tdata + ,input tlast + ,input tuser + ,input tkeep + ,input tvalid + ,output tready + + ); + + modport m ( + + output tdata + ,output tlast + ,output tuser + ,output tkeep + ,output tvalid + ,input tready + + ); + +endinterface : dma_pcie_axis_rq_if +`endif // IF_AXIS_RQ_PCIE_DMA_PORT_SV diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_c2h_crdt_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_c2h_crdt_if.svh new file mode 100755 index 0000000..17ae106 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_c2h_crdt_if.svh @@ -0,0 +1,42 @@ +`ifndef IF_PCIE_DMA_C2H_CRDT_SV +`define IF_PCIE_DMA_C2H_CRDT_SV +interface dma_pcie_c2h_crdt_if #(); + logic [511:0] tdata; + logic [512/8-1:0] tparity; + logic tlast; + logic [512/8-1:0] tkeep; + logic [127:0] tusr; + logic tvalid; + logic [1:0] tch; + + logic crdt; + logic [1:0] crdt_ch; + + modport m ( + output tdata, + output tparity, + output tlast, + output tkeep, + output tusr, + output tvalid, + output tch, + + input crdt, + input crdt_ch + ); + + modport s ( + input tdata, + input tparity, + input tlast, + input tkeep, + input tusr, + input tvalid, + input tch, + + output crdt, + output crdt_ch + ); + +endinterface : dma_pcie_c2h_crdt_if +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_dsc_in_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_dsc_in_if.svh new file mode 100755 index 0000000..edf83d7 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_dsc_in_if.svh @@ -0,0 +1,20 @@ +`ifndef IF_PCIE_DMA_DSC_IN_SV +`define IF_PCIE_DMA_DSC_IN_SV +`include "dma_defines.svh" + +interface dma_pcie_dsc_in_if(); + dma_dsc_in_crd_t crd; + dma_dsc_block_t dsc; + +modport snk ( +input dsc, +output crd +); + +modport src ( +input dsc, +output crd +); + +endinterface : dma_pcie_dsc_in_if +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_dsc_out_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_dsc_out_if.svh new file mode 100755 index 0000000..858c743 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_dsc_out_if.svh @@ -0,0 +1,28 @@ +`ifndef DMA_PCIE_DSC_OUT_IF_SV +`define DMA_PCIE_DSC_OUT_IF_SV +`include "dma_defines.svh" + +interface dma_pcie_dsc_out_if(); + dma_dsc_out_crd_t crd; + dma_dsc_block_t dsc; + +modport snk ( + output crd, + input dsc +); + +modport src ( + input crd, + output dsc +); + +modport outputs ( + output dsc +); + +modport inputs ( + input crd +); + +endinterface : dma_pcie_dsc_out_if +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_fabric_input_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_fabric_input_if.svh new file mode 100755 index 0000000..099083d --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_fabric_input_if.svh @@ -0,0 +1,29 @@ +`ifndef IF_PCIE_DMA_FABRIC_INPUT_SV +`define IF_PCIE_DMA_FABRIC_INPUT_SV +interface dma_pcie_fabric_input_if(); +logic usr_irq_clr; +logic usr_irq_set; +logic [4:0] usr_irq_vec; +logic [7:0] usr_irq_fnc; +logic flr_done_vld; +logic [7:0] flr_done_fnc; + +modport s ( +input usr_irq_clr, +input usr_irq_set, +input usr_irq_vec, +input usr_irq_fnc, +input flr_done_vld, +input flr_done_fnc +); + +modport m ( +output usr_irq_clr, +output usr_irq_set, +output usr_irq_vec, +output usr_irq_fnc, +output flr_done_vld, +output flr_done_fnc +); +endinterface : dma_pcie_fabric_input_if +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_fabric_output_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_fabric_output_if.svh new file mode 100755 index 0000000..20c1727 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_fabric_output_if.svh @@ -0,0 +1,64 @@ +`ifndef IF_PCIE_DMA_FABRIC_OUTPUT_SV +`define IF_PCIE_DMA_FABRIC_OUTPUT_SV +interface dma_pcie_fabric_output_if(); +logic c2h_dsc_avail_inc_vld; +logic [1:0] c2h_dsc_avail_inc_chn; +logic [7:0] c2h_dsc_avail_inc_qid; +logic [1:0] c2h_dsc_avail_inc_state; +logic [15:0] c2h_dsc_avail_inc_num; +logic s_axis_c2h_tstat_vld; +logic [1:0] s_axis_c2h_tstat_chn; +logic [4:0] s_axis_c2h_tstat_qid; +logic [7:0] s_axis_c2h_tstat; +logic [3:0][7:0] c2h_sts; +logic [3:0][7:0] h2c_sts; +logic flr_set; +logic flr_clr; +logic [7:0] flr_fnc; +logic [4:0] usr_irq_rvec; +logic [7:0] usr_irq_rfnc; +logic usr_irq_fail; +logic usr_irq_sent; + +modport m ( +output c2h_dsc_avail_inc_vld, +output c2h_dsc_avail_inc_chn, +output c2h_dsc_avail_inc_qid, +output c2h_dsc_avail_inc_state, +output c2h_dsc_avail_inc_num, +output s_axis_c2h_tstat_vld, +output s_axis_c2h_tstat_chn, +output s_axis_c2h_tstat_qid, +output s_axis_c2h_tstat, +output c2h_sts, +output h2c_sts, +output flr_set, +output flr_clr, +output flr_fnc, +output usr_irq_rvec, +output usr_irq_rfnc, +output usr_irq_fail, +output usr_irq_sent +); +modport s ( +input c2h_dsc_avail_inc_vld, +input c2h_dsc_avail_inc_chn, +input c2h_dsc_avail_inc_qid, +input c2h_dsc_avail_inc_state, +input c2h_dsc_avail_inc_num, +input s_axis_c2h_tstat_vld, +input s_axis_c2h_tstat_chn, +input s_axis_c2h_tstat_qid, +input s_axis_c2h_tstat, +input c2h_sts, +input h2c_sts, +input flr_set, +input flr_clr, +input flr_fnc, +input usr_irq_rvec, +input usr_irq_rfnc, +input usr_irq_fail, +input usr_irq_sent +); +endinterface : dma_pcie_fabric_output_if +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_gic_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_gic_if.svh new file mode 100755 index 0000000..0b425ef --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_gic_if.svh @@ -0,0 +1,13 @@ +`ifndef IF_PCIE_DMA_GIC_SV +`define IF_PCIE_DMA_GIC_SV +interface dma_pcie_gic_if(); + logic [6:0] interrupt; +modport m ( + output interrupt +); +modport s ( + input interrupt +); + +endinterface : dma_pcie_gic_if +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_h2c_crdt_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_h2c_crdt_if.svh new file mode 100755 index 0000000..602c637 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_h2c_crdt_if.svh @@ -0,0 +1,42 @@ +`ifndef IF_PCIE_DMA_H2C_CRDT_SV +`define IF_PCIE_DMA_H2C_CRDT_SV +interface dma_pcie_h2c_crdt_if #(); + logic [511:0] tdata; + logic [512/8-1:0] tparity; + logic tlast; + logic [512/8-1:0] tkeep; + logic [63:0] tusr; + logic tvalid; + logic [1:0] tch; + + logic crdt; + logic [1:0] crdt_ch; + + modport m ( + output tdata, + output tparity, + output tlast, + output tkeep, + output tusr, + output tvalid, + output tch, + + input crdt, + input crdt_ch + ); + + modport s ( + input tdata, + input tparity, + input tlast, + input tkeep, + input tusr, + input tvalid, + input tch, + + output crdt, + output crdt_ch + ); + +endinterface : dma_pcie_h2c_crdt_if +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_16Bx2048_4Bwe_ram_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_16Bx2048_4Bwe_ram_if.svh new file mode 100755 index 0000000..7b7a560 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_16Bx2048_4Bwe_ram_if.svh @@ -0,0 +1,43 @@ +`ifndef DMA_PCIE_MI_16BX2048_4BWE_RAM_IF_SV +`define DMA_PCIE_MI_16BX2048_4BWE_RAM_IF_SV + + +interface dma_pcie_mi_16Bx2048_4Bwe_ram_if(); + logic [11:0] wadr; // 1024 H2C Qs, 1024 C2H Qs + logic [3:0] wen; + logic [7:0] wpar; + logic [127:0] wdat; // 15:8 func, 3:0 = sts, 63:32 = produce index, 127:64 = base address + logic ren; + logic [11:0] radr; + logic [7:0] rpar; + logic [127:0] rdat; + logic rsbe; + logic rdbe; + + modport m ( + output wadr, + output wen, + output wpar, + output wdat, + output ren, + output radr, + input rpar, + input rdat, + input rsbe, + input rdbe + ); + modport s ( + input wadr, + input wen, + input wpar, + input wdat, + input ren, + input radr, + output rpar, + output rdat, + output rsbe, + output rdbe + ); +endinterface + +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_2Bx2048_ram_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_2Bx2048_ram_if.svh new file mode 100755 index 0000000..44b2c5b --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_2Bx2048_ram_if.svh @@ -0,0 +1,40 @@ +`ifndef DMA_PCIE_MI_2BX2048_RAM_IF_SV +`define DMA_PCIE_MI_2BX2048_RAM_IF_SV +interface dma_pcie_mi_2Bx2048_ram_if(); + logic [11:0] wadr; + logic wen; + logic [1:0] wpar; + logic [15:0] wdat; + logic ren; + logic [11:0] radr; + logic [1:0] rpar; + logic [15:0] rdat; + logic rsbe; + logic rdbe; + + modport m ( + output wadr, + output wen, + output wpar, + output wdat, + output ren, + output radr, + input rpar, + input rdat, + input rsbe, + input rdbe + ); + modport s ( + input wadr, + input wen, + input wpar, + input wdat, + input ren, + input radr, + output rpar, + output rdat, + output rsbe, + output rdbe + ); +endinterface +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_4Bx2048_4Bwe_ram_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_4Bx2048_4Bwe_ram_if.svh new file mode 100755 index 0000000..8427aeb --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_4Bx2048_4Bwe_ram_if.svh @@ -0,0 +1,41 @@ +`ifndef DMA_PCIE_MI_4BX2048_4BWE_RAM_IF_SV +`define DMA_PCIE_MI_4BX2048_4BWE_RAM_IF_SV + +interface dma_pcie_mi_4Bx2048_4Bwe_ram_if(); + logic [11:0] wadr; + logic wen; + logic [7:0] wpar; + logic [31:0] wdat; // 31:16 = used credits. 15:0= consumer index + logic ren; + logic [11:0] radr; + logic [7:0] rpar; + logic [31:0] rdat; + logic rsbe; + logic rdbe; + + modport m ( + output wadr, + output wen, + output wpar, + output wdat, + output ren, + output radr, + input rpar, + input rdat, + input rsbe, + input rdbe + ); + modport s ( + input wadr, + input wen, + input wpar, + input wdat, + input ren, + input radr, + output rpar, + output rdat, + output rsbe, + output rdbe + ); +endinterface +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx1024_32Bwe_ram_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx1024_32Bwe_ram_if.svh new file mode 100755 index 0000000..c9eafff --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx1024_32Bwe_ram_if.svh @@ -0,0 +1,44 @@ +`ifndef DMA_PCIE_MI_64BX1024_32BWE_RAM_IF_SV +`define DMA_PCIE_MI_64BX1024_32BWE_RAM_IF_SV +interface dma_pcie_mi_64Bx1024_32Bwe_ram_if(); + logic [9:0] wadr; + logic [1:0] wen; + logic [63:0] wpar; + logic [511:0] wdat; + logic ren; + logic [9:0] radr; + + logic [63:0] rpar; + logic [511:0] rdat; + logic rsbe; + logic rdbe; + +modport m ( + output wadr, + output wen, + output wpar, + output wdat, + output ren, + output radr, + + input rpar, + input rdat, + input rsbe, + input rdbe +); + +modport s ( + input wadr, + input wen, + input wpar, + input wdat, + input ren, + input radr, + + output rpar, + output rdat, + output rsbe, + output rdbe +); +endinterface +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx128_32Bwe_ram_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx128_32Bwe_ram_if.svh new file mode 100755 index 0000000..3ad52dc --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx128_32Bwe_ram_if.svh @@ -0,0 +1,44 @@ +`ifndef DMA_PCIE_MI_64BX128_32BWE_RAM_IF_SV +`define DMA_PCIE_MI_64BX128_32BWE_RAM_IF_SV +interface dma_pcie_mi_64Bx128_32Bwe_ram_if(); + logic [6:0] wadr; + logic [1:0] wen; + logic [63:0] wpar; + logic [511:0] wdat; + logic ren; + logic [6:0] radr; + + logic [63:0] rpar; + logic [511:0] rdat; + logic rsbe; + logic rdbe; + +modport m ( + output wadr, + output wen, + output wpar, + output wdat, + output ren, + output radr, + + input rpar, + input rdat, + input rsbe, + input rdbe +); + +modport s ( + input wadr, + input wen, + input wpar, + input wdat, + input ren, + input radr, + + output rpar, + output rdat, + output rsbe, + output rdbe +); +endinterface +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx256_32Bwe_ram_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx256_32Bwe_ram_if.svh new file mode 100755 index 0000000..b947ffd --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx256_32Bwe_ram_if.svh @@ -0,0 +1,44 @@ +`ifndef DMA_PCIE_MI_64BX256_32BWE_RAM_IF_SV +`define DMA_PCIE_MI_64BX256_32BWE_RAM_IF_SV +interface dma_pcie_mi_64Bx256_32Bwe_ram_if(); + logic [8:0] wadr; // FIXME hack should be 8 bits + logic [1:0] wen; + logic [63:0] wpar; + logic [511:0] wdat; + logic ren; + logic [8:0] radr; // FIXME hack should be 8 bits + + logic [63:0] rpar; + logic [511:0] rdat; + logic rsbe; + logic rdbe; + +modport m ( + output wadr, + output wen, + output wpar, + output wdat, + output ren, + output radr, + + input rpar, + input rdat, + input rsbe, + input rdbe +); + +modport s ( + input wadr, + input wen, + input wpar, + input wdat, + input ren, + input radr, + + output rpar, + output rdat, + output rsbe, + output rdbe +); +endinterface +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx512_32Bwe_ram_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx512_32Bwe_ram_if.svh new file mode 100755 index 0000000..69b39a2 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx512_32Bwe_ram_if.svh @@ -0,0 +1,44 @@ +`ifndef DMA_PCIE_MI_64BX512_32BWE_RAM_IF_SV +`define DMA_PCIE_MI_64BX512_32BWE_RAM_IF_SV +interface dma_pcie_mi_64Bx512_32Bwe_ram_if(); + logic [8:0] wadr; + logic [1:0] wen; + logic [63:0] wpar; + logic [511:0] wdat; + logic ren; + logic [8:0] radr; + + logic [63:0] rpar; + logic [511:0] rdat; + logic rsbe; + logic rdbe; + +modport m ( + output wadr, + output wen, + output wpar, + output wdat, + output ren, + output radr, + + input rpar, + input rdat, + input rsbe, + input rdbe +); + +modport s ( + input wadr, + input wen, + input wpar, + input wdat, + input ren, + input radr, + + output rpar, + output rdat, + output rsbe, + output rdbe +); +endinterface +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_8Bx2048_4Bwe_ram_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_8Bx2048_4Bwe_ram_if.svh new file mode 100755 index 0000000..f1ecfdf --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_8Bx2048_4Bwe_ram_if.svh @@ -0,0 +1,41 @@ +`ifndef DMA_PCIE_MI_8BX2048_4BWE_RAM_IF_SV +`define DMA_PCIE_MI_8BX2048_4BWE_RAM_IF_SV + +interface dma_pcie_mi_8Bx2048_4Bwe_ram_if(); + logic [11:0] wadr; // 1024 H2C Qs, 1024 C2H Qs + logic [1:0] wen; + logic [7:0] wpar; + logic [63:0] wdat; // 63:0 writeback base address + logic ren; + logic [11:0] radr; + logic [7:0] rpar; + logic [127:0] rdat; + logic rsbe; + logic rdbe; + + modport m ( + output wadr, + output wen, + output wpar, + output wdat, + output ren, + output radr, + input rpar, + input rdat, + input rsbe, + input rdbe + ); + modport s ( + input wadr, + input wen, + input wpar, + input wdat, + input ren, + input radr, + output rpar, + output rdat, + output rsbe, + output rdbe + ); +endinterface +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_dsc_cpld_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_dsc_cpld_if.svh new file mode 100755 index 0000000..970ab49 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_dsc_cpld_if.svh @@ -0,0 +1,71 @@ +`ifndef DMA_PCIE_MI_DSC_CPLD_IF_SV +`define DMA_PCIE_MI_DSC_CPLD_IF_SV +interface dma_pcie_mi_dsc_cpld_if(); + logic [9:0] wadr; // 10 bits for MULTQ C2H + logic [7:0] wen; + logic [63:0] wpar; + logic [511:0] wdat; + logic ren; + logic [9:0] radr; // 10 bits for MULTQ C2H + logic [63:0] rpar; + logic [511:0] rdat; + logic rsbe; + logic rdbe; + + modport m ( + output wadr, + output wen, + output wpar, + output wdat, + output ren, + output radr, + input rpar, + input rdat, + input rsbe, + input rdbe + ); + modport s ( + input wadr, + input wen, + input wpar, + input wdat, + input ren, + input radr, + output rpar, + output rdat, + output rsbe, + output rdbe + ); + modport s_outputs ( + output wadr, + output wen, + output wpar, + output wdat, + output ren, + output radr + ); + + modport m_outputs ( + output rpar, + output rdat, + output rsbe, + output rdbe + ); + + modport s_inputs ( + input wadr, + input wen, + input wpar, + input wdat, + input ren, + input radr + ); + + modport m_inputs ( + input rpar, + input rdat, + input rsbe, + input rdbe + ); +endinterface +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_dsc_cpli_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_dsc_cpli_if.svh new file mode 100755 index 0000000..4a9cd1c --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_dsc_cpli_if.svh @@ -0,0 +1,41 @@ +`ifndef DMA_PCIE_MI_DSC_CPLI_IF_SV +`define DMA_PCIE_MI_DSC_CPLI_IF_SV +`include "dma_defines.vh" +interface dma_pcie_mi_dsc_cpli_if(); + logic [9:0] wadr; // 10 bits for MULTQ C2H + logic [7:0] wen; + logic [3:0] wpar; + logic [`CPLI_WIDTH-1:0] wdat; + logic ren; + logic [9:0] radr; // 10 bits for MULTQ C2H + logic [3:0] rpar; + logic [`CPLI_WIDTH-1:0] rdat; + logic rsbe; + logic rdbe; + + modport m ( + output wadr, + output wen, + output wpar, + output wdat, + output ren, + output radr, + input rpar, + input rdat, + input rsbe, + input rdbe + ); + modport s ( + input wadr, + input wen, + input wpar, + input wdat, + input ren, + input radr, + output rpar, + output rdat, + output rsbe, + output rdbe + ); +endinterface +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_misc_input_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_misc_input_if.svh new file mode 100755 index 0000000..edd0354 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_misc_input_if.svh @@ -0,0 +1,157 @@ +`ifndef IF_PCIE_DMA_MISC_INPUT_SV +`define IF_PCIE_DMA_MISC_INPUT_SV + +interface dma_pcie_misc_input_if(); +logic cfg_interrupt_msi_mask_update; +logic cfg_err_cor_out; +logic cfg_err_fatal_out; +logic cfg_err_nonfatal_out; +logic cfg_ext_read_received; +logic cfg_ext_write_received; +logic cfg_hot_reset_out; +logic cfg_interrupt_msi_enable; +logic cfg_interrupt_msi_fail; +logic cfg_interrupt_msi_sent; +logic cfg_interrupt_msix_fail; +logic cfg_interrupt_msix_sent; +logic cfg_interrupt_sent; +logic cfg_local_error; +logic cfg_mgmt_read_write_done; +logic cfg_msg_received; +logic cfg_msg_transmit_done; +logic cfg_per_function_update_done; +logic cfg_phy_link_down; +logic pcie_rq_seq_num_vld0; +logic pcie_rq_seq_num_vld1; +logic [15:0] cfg_function_status; +logic [15:0] cfg_per_func_status_data; +logic [3:0] cfg_interrupt_msix_enable; +logic [3:0] cfg_interrupt_msix_mask; +logic [1:0] cfg_phy_link_status; +logic [251:0]cfg_vf_flr_in_process; +logic [2:0] cfg_current_speed; +logic [2:0] cfg_max_payload; +logic [2:0] cfg_max_read_req; +logic [31:0] cfg_ext_write_data; +logic [31:0] cfg_mgmt_read_data; +logic [3:0] cfg_ext_write_byte_enable; +logic [3:0] cfg_flr_in_process; +logic [3:0] cfg_negotiated_width; +logic [5:0] pcie_cq_np_req_count; +logic [3:0] pcie_rq_seq_num0; +logic [3:0] pcie_rq_seq_num1; +logic [3:0] pcie_tfc_nph_av; +logic [4:0] cfg_msg_received_type; +logic [5:0] cfg_interrupt_msix_vf_enable; +logic [5:0] cfg_interrupt_msix_vf_mask; +logic [5:0] cfg_ltssm_state; +logic cfg_pl_status_change; +logic [7:0] cfg_ext_function_number; +logic [7:0] cfg_msg_received_data; +logic [7:0] cfg_fc_nph; +logic [9:0] cfg_ext_register_number; + +modport s ( +input cfg_interrupt_msi_mask_update, +input cfg_err_cor_out, +input cfg_err_fatal_out, +input cfg_err_nonfatal_out, +input cfg_ext_read_received, +input cfg_ext_write_received, +input cfg_hot_reset_out, +input cfg_interrupt_msi_enable, +input cfg_interrupt_msi_fail, +input cfg_interrupt_msi_sent, +input cfg_interrupt_msix_fail, +input cfg_interrupt_msix_sent, +input cfg_interrupt_sent, +input cfg_local_error, +input cfg_mgmt_read_write_done, +input cfg_msg_received, +input cfg_msg_transmit_done, +input cfg_per_function_update_done, +input cfg_phy_link_down, +input pcie_cq_np_req_count, +input pcie_rq_seq_num_vld0, +input pcie_rq_seq_num_vld1, +input cfg_function_status, +input cfg_per_func_status_data, +input cfg_interrupt_msix_enable, +input cfg_interrupt_msix_mask, +input cfg_phy_link_status, +input cfg_vf_flr_in_process, +input cfg_current_speed, +input cfg_max_payload, +input cfg_max_read_req, +input cfg_ext_write_data, +input cfg_mgmt_read_data, +input cfg_ext_write_byte_enable, +input cfg_flr_in_process, +input cfg_negotiated_width, +input pcie_rq_seq_num0, +input pcie_rq_seq_num1, +input pcie_tfc_nph_av, +input cfg_msg_received_type, +input cfg_interrupt_msix_vf_enable, +input cfg_interrupt_msix_vf_mask, +input cfg_ltssm_state, +input cfg_pl_status_change, +input cfg_ext_function_number, +input cfg_msg_received_data, +input cfg_fc_nph, +input cfg_ext_register_number +); + +modport m ( +output cfg_interrupt_msi_mask_update, +output cfg_err_cor_out, +output cfg_err_fatal_out, +output cfg_err_nonfatal_out, +output cfg_ext_read_received, +output cfg_ext_write_received, +output cfg_hot_reset_out, +output cfg_interrupt_msi_enable, +output cfg_interrupt_msi_fail, +output cfg_interrupt_msi_sent, +output cfg_interrupt_msix_fail, +output cfg_interrupt_msix_sent, +output cfg_interrupt_sent, +output cfg_local_error, +output cfg_mgmt_read_write_done, +output cfg_msg_received, +output cfg_msg_transmit_done, +output cfg_per_function_update_done, +output cfg_phy_link_down, +output pcie_cq_np_req_count, +output pcie_rq_seq_num_vld0, +output pcie_rq_seq_num_vld1, +output cfg_function_status, +output cfg_per_func_status_data, +output cfg_interrupt_msix_enable, +output cfg_interrupt_msix_mask, +output cfg_phy_link_status, +output cfg_vf_flr_in_process, +output cfg_current_speed, +output cfg_max_payload, +output cfg_max_read_req, +output cfg_ext_write_data, +output cfg_mgmt_read_data, +output cfg_ext_write_byte_enable, +output cfg_flr_in_process, +output cfg_negotiated_width, +output pcie_rq_seq_num0, +output pcie_rq_seq_num1, +output pcie_tfc_nph_av, +output cfg_msg_received_type, +output cfg_interrupt_msix_vf_enable, +output cfg_interrupt_msix_vf_mask, +output cfg_ltssm_state, +output cfg_pl_status_change, +output cfg_ext_function_number, +output cfg_msg_received_data, +output cfg_fc_nph, +output cfg_ext_register_number +); +endinterface : dma_pcie_misc_input_if + +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_misc_output_if.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_misc_output_if.svh new file mode 100755 index 0000000..4ed65b9 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_pcie_misc_output_if.svh @@ -0,0 +1,158 @@ +`ifndef IF_PCIE_DMA_MISC_OUTPUT_SV +`define IF_PCIE_DMA_MISC_OUTPUT_SV + +interface dma_pcie_misc_output_if(); +logic [2:0] cfg_fc_sel; +logic [1:0] pcie_cq_np_req; +logic [18:0] cfg_mgmt_addr; +logic cfg_mgmt_write; +logic [31:0] cfg_mgmt_write_data; +logic [3:0] cfg_mgmt_byte_enable; +logic cfg_mgmt_read; +logic [7:0] cfg_mgmt_function_number; +logic cfg_mgmt_type1_cfg_reg_access; +logic [7:0] cfg_ds_port_number; +logic [7:0] cfg_ds_bus_number; +logic [4:0] cfg_ds_device_number; +logic [2:0] cfg_ds_function_number; +logic [2:0] cfg_per_func_status_control; +logic [6:0] cfg_per_function_number; +logic cfg_per_function_output_request; +logic cfg_per_function_logic_request; +logic cfg_msg_transmit; +logic [2:0] cfg_msg_transmit_type; +logic [31:0] cfg_msg_transmit_data; +//logic [15:0] cfg_subsys_id; +//logic [15:0] cfg_subsys_vend_id; +//logic [15:0] cfg_vend_id; +logic [63:0] cfg_dsn; +logic cfg_err_cor_in; +logic cfg_err_uncor_in; +logic cfg_link_training_enable; +logic [31:0] cfg_ext_read_data; +logic cfg_ext_read_data_valid; +logic [3:0] cfg_flr_done; +logic cfg_vf_flr_done; +logic [7:0] cfg_vf_flr_func_num; +logic cfg_config_space_enable; +logic cfg_hot_reset_in; +logic [31:0] cfg_interrupt_msi_int; +logic [31:0] cfg_interrupt_msi_pending_status; +logic cfg_interrupt_msi_pending_status_data_enable; +logic [3:0] cfg_interrupt_msi_pending_status_function_num; +logic [2:0] cfg_interrupt_msi_attr; +logic cfg_interrupt_msi_tph_present; +logic [1:0] cfg_interrupt_msi_tph_type; +logic [8:0] cfg_interrupt_msi_tph_st_tag; +logic [3:0] cfg_interrupt_msi_function_number; +logic cfg_interrupt_msix_int; +logic [31:0] cfg_interrupt_msix_data; +logic [255:0] cfg_interrupt_msix_address; +logic [3:0] cfg_interrupt_int; +logic [3:0] cfg_interrupt_pending; + +modport m ( +output cfg_fc_sel, +output pcie_cq_np_req, +output cfg_mgmt_addr, +output cfg_mgmt_write, +output cfg_mgmt_write_data, +output cfg_mgmt_byte_enable, +output cfg_mgmt_read, +output cfg_mgmt_function_number, +output cfg_mgmt_type1_cfg_reg_access, +output cfg_ds_port_number, +output cfg_ds_bus_number, +output cfg_ds_device_number, +output cfg_ds_function_number, +output cfg_per_function_output_request, +output cfg_per_function_logic_request, +output cfg_per_func_status_control, +output cfg_per_function_number, +output cfg_msg_transmit, +output cfg_msg_transmit_type, +output cfg_msg_transmit_data, +//output cfg_rev_id, +//output cfg_subsys_id, +//output cfg_subsys_vend_id, +//output cfg_vend_id, +output cfg_dsn, +output cfg_err_cor_in, +output cfg_err_uncor_in, +output cfg_link_training_enable, +output cfg_ext_read_data, +output cfg_ext_read_data_valid, +output cfg_flr_done, +output cfg_vf_flr_done, +output cfg_vf_flr_func_num, +output cfg_config_space_enable, +output cfg_hot_reset_in, +output cfg_interrupt_msi_int, +output cfg_interrupt_msi_pending_status, +output cfg_interrupt_msi_pending_status_data_enable, +output cfg_interrupt_msi_pending_status_function_num, +output cfg_interrupt_msi_attr, +output cfg_interrupt_msi_tph_present, +output cfg_interrupt_msi_tph_type, +output cfg_interrupt_msi_tph_st_tag, +output cfg_interrupt_msi_function_number, +output cfg_interrupt_msix_int, +output cfg_interrupt_msix_data, +output cfg_interrupt_msix_address, +output cfg_interrupt_int, +output cfg_interrupt_pending +); + +modport s ( +input cfg_fc_sel, +input pcie_cq_np_req, +input cfg_mgmt_addr, +input cfg_mgmt_write, +input cfg_mgmt_write_data, +input cfg_mgmt_byte_enable, +input cfg_mgmt_read, +input cfg_mgmt_function_number, +input cfg_mgmt_type1_cfg_reg_access, +input cfg_ds_port_number, +input cfg_ds_bus_number, +input cfg_ds_device_number, +input cfg_ds_function_number, +input cfg_per_func_status_control, +input cfg_per_function_number, +input cfg_per_function_output_request, +input cfg_per_function_logic_request, +input cfg_msg_transmit, +input cfg_msg_transmit_type, +input cfg_msg_transmit_data, +//input cfg_rev_id, +//input cfg_subsys_id, +//input cfg_subsys_vend_id, +//input cfg_vend_id, +input cfg_dsn, +input cfg_err_cor_in, +input cfg_err_uncor_in, +input cfg_link_training_enable, +input cfg_ext_read_data, +input cfg_ext_read_data_valid, +input cfg_flr_done, +input cfg_vf_flr_done, +input cfg_vf_flr_func_num, +input cfg_config_space_enable, +input cfg_hot_reset_in, +input cfg_interrupt_msi_int, +input cfg_interrupt_msi_pending_status, +input cfg_interrupt_msi_pending_status_data_enable, +input cfg_interrupt_msi_pending_status_function_num, +input cfg_interrupt_msi_attr, +input cfg_interrupt_msi_tph_present, +input cfg_interrupt_msi_tph_type, +input cfg_interrupt_msi_tph_st_tag, +input cfg_interrupt_msi_function_number, +input cfg_interrupt_msix_int, +input cfg_interrupt_msix_data, +input cfg_interrupt_msix_address, +input cfg_interrupt_int, +input cfg_interrupt_pending +); +endinterface : dma_pcie_misc_output_if +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_soft_defines.vh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_soft_defines.vh new file mode 100755 index 0000000..d91f492 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/dma_soft_defines.vh @@ -0,0 +1,6 @@ +`ifndef DMA_SOFT_DEFINES_VH +`define DMA_SOFT_DEFINES_VH + +`define SOFT_IP + +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/pcie_dma_attr_defines.svh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/pcie_dma_attr_defines.svh new file mode 100755 index 0000000..ceae6f7 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/pcie_dma_attr_defines.svh @@ -0,0 +1,67 @@ +`ifndef PCIE_DMA_ATTR_DEFINES_VH +`define PCIE_DMA_ATTR_DEFINES_VH + +// DMA PF Attributes +typedef struct packed { + logic [3:0] ch_alloc; + logic [1:0] multq_chbits; + logic [5:0] multq_maxq; + logic [2:0] multq_bits; + logic [5:0] vfmaxq; + logic [2:0] multq_vfqbits; + logic [7:0] num_vfs; + logic [7:0] firstvf_offset; +} attr_dma_pf_t; + +// DMA PCIeBAR to AXIBAR Attributes +typedef struct packed { + logic [63:12] bar; + logic sec; + logic [3:0] cache; + logic [7:0] len; + logic [31:0] bar_vf; + logic sec_vf; + logic [3:0] cache_vf; + logic [7:0] len_vf; +} attr_dma_pciebar2axibar_pf_t; + +// DMA AXIBAR to PCIeBAR Attributes +typedef struct packed { + logic [63:0] base; + logic as; + logic [7:0] highaddr; + logic [63:0] bar; +} attr_dma_axibar2pciebar_t; + +// DMA General Attributes +typedef struct packed { + logic [63:0] axi_slv_brdg_base_addr; + logic [63:0] axi_slv_multq_base_addr; + logic [63:0] axi_slv_xdma_base_addr; + logic enable; + logic bypass_msix; + logic [2:0] data_width; + logic metering_enable; + logic [5:0] mask50; + logic root_port; + logic msi_rx_decode_en; + logic pcie_if_parity_check; + logic [31:0] slvlite_base0; + logic [31:0] slvlite_base1; + logic [2:0] barlite0; + logic [2:0] barlite1; + logic [2:0] axibar_num; + logic [2:0] pciebar_num; + logic [3:0] ch_en; + logic [3:0][1:0] ch_pfid; + logic [3:0] ch_multq; + logic [3:0] ch_stream; + logic [3:0] ch_c2h_axi_dsc; + logic [3:0] ch_h2c_axi_dsc; + logic [3:0] ch_multq_ll; + logic [3:0][5:0] ch_multq_max; + logic cq_rcfg_en; + logic [255:0] spare; +} attr_dma_t; + +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/pciedmacoredefines.vh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/pciedmacoredefines.vh new file mode 100755 index 0000000..73acaf8 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/pciedmacoredefines.vh @@ -0,0 +1,453 @@ +/***************************************************************************** +** (c) Copyright 2007-2013 Xilinx, Inc. All rights reserved. +** +** This file contains confidential and proprietary information +** of Xilinx, Inc. and is protected under U.S. and +** international copyright and other intellectual property +** laws. +** +** DISCLAIMER +** This disclaimer is not a license and does not grant any +** rights to the materials distributed herewith. Except as +** otherwise provided in a valid license issued to you by +** Xilinx, and to the maximum extent permitted by applicable +** law: (1) THESE MATERIALS ARE MADE AVAILABLE AS IS AND +** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +** (2) Xilinx shall not be liable (whether in contract or tort, +** including negligence, or under any other theory of +** liability) for any loss or damage of any kind or nature +** related to, arising under or in connection with these +** materials, including for any direct, or any indirect, +** special, incidental, or consequential loss or damage +** (including loss of data, profits, goodwill, or any type of +** loss or damage suffered as a result of any action brought +** by a third party) even if such damage or loss was +** reasonably foreseeable or Xilinx had been advised of the +** possibility of the same. +** +** CRITICAL APPLICATIONS +** Xilinx products are not designed or intended to be fail- +** safe, or for use in any application requiring fail-safe +** performance, such as life-support or safety devices or +** systems, Class III medical devices, nuclear facilities, +** applications related to the deployment of airbags, or any +** other applications that could lead to death, personal +** injury, or severe property or environmental damage +** (individually and collectively, ; Critical; +** Applications). Customer assumes the sole risk and +** liability of any use of Xilinx products in Critical +** Applications, subject only to applicable laws and +** regulations governing limitations on product liability. +** +** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +** PART OF THIS FILE AT ALL TIMES. +****************************************************************************** +** +** Project:PCI Express Gen4 +** Author: Siva Prasad +** Date:$DateTime: 2014/08/05 13:55:49 $ +** Description: PCIE core common defines and Macros +** Revision: $Revision: #22 $ +** Changed By: $Author: dpan $ +** +*****************************************************************************/ +`timescale 1ps/1ps + +`ifdef PCIEDMACOREDEFINES_VH +`else + `define PCIEDMACOREDEFINES_VH +// Default is asynchronous reset flops +// X REG with async clear and sync load (reset), and enable +`define XPLREG_EN(clk,reset_n,load,q,d,rstval,ldval,en) \ +`ifndef SYNC_FF \ +`XPLREG_ASYNC_EN(clk,reset_n,load,q,d,rstval,ldval,en) \ +`else \ +`XPLREG_SYNC_EN(clk,reset_n,load,q,d,rstval,ldval,en) \ +`endif + + +`define XPLREG_SYNC_EN(clk,reset_n,load,q,d,rstval,ldval,en) \ +always @(posedge clk) \ +begin \ + if (reset_n == 1'b0) \ + q <= #(TCQ) rstval; \ + else if (load == 1'b1) \ + q <= #(TCQ) ldval; \ + else \ +`ifdef FOURVALCLKPROP \ + q <= #(TCQ) (en & clk) ? d : q; \ +`else \ + q <= #(TCQ) en ? d : q; \ +`endif \ +end + +`define XPLREG_ASYNC_EN(clk,reset_n,load,q,d,rstval,ldval,en) \ +always @(posedge clk or negedge reset_n) \ +begin \ + if (reset_n == 1'b0) \ + q <= #(TCQ) rstval; \ + else if (load == 1'b1) \ + q <= #(TCQ) ldval; \ + else \ +`ifdef FOURVALCLKPROP \ + q <= #(TCQ) (en & clk) ? d : q; \ +`else \ + q <= #(TCQ) en ? d : q; \ +`endif \ +end + +// X REG with async clear and sync load (reset) +`define XPLREG(clk,reset_n,load,q,d,rstval,ldval) \ +`ifndef SYNC_FF \ +`XPLREG_ASYNC(clk,reset_n,load,q,d,rstval,ldval) \ +`else \ +`XPLREG_SYNC(clk,reset_n,load,q,d,rstval,ldval) \ +`endif +`define XPLREG_SYNC(clk,reset_n,load,q,d,rstval,ldval) \ +always @(posedge clk) \ +begin \ + if (reset_n == 1'b0) \ + q <= #(TCQ) rstval; \ + else if (load == 1'b1) \ + q <= #(TCQ) ldval; \ + else \ +`ifdef FOURVALCLKPROP \ + q <= #(TCQ) clk ? d : q; \ +`else \ + q <= #(TCQ) d; \ +`endif \ +end +`define XPLREG_ASYNC(clk,reset_n,load,q,d,rstval,ldval) \ +always @(posedge clk or negedge reset_n) \ +begin \ + if (reset_n == 1'b0) \ + q <= #(TCQ) rstval; \ + else if (load == 1'b1) \ + q <= #(TCQ) ldval; \ + else \ +`ifdef FOURVALCLKPROP \ + q <= #(TCQ) clk ? d : q; \ +`else \ + q <= #(TCQ) d; \ +`endif \ +end + +`define XPREG(clk, reset_n, q,d,rstval) \ + `ifndef SYNC_FF \ +`XPREG_ASYNC(clk, reset_n, q,d,rstval) \ + `else \ +`XPREG_SYNC(clk, reset_n, q,d,rstval) \ + `endif +`define XPREG_SYNC(clk, reset_n, q,d,rstval) \ + always @(posedge clk) \ + begin \ + if (reset_n == 1'b0) \ + q <= #(TCQ) rstval; \ + else \ + `ifdef FOURVALCLKPROP \ + q <= #(TCQ) clk ? d : q; \ + `else \ + q <= #(TCQ) d; \ + `endif \ + end +`define XPREG_ASYNC(clk, reset_n, q,d,rstval) \ + always @(posedge clk or negedge reset_n ) \ + begin \ + if (reset_n == 1'b0) \ + q <= #(TCQ) rstval; \ + else \ + `ifdef FOURVALCLKPROP \ + q <= #(TCQ) clk ? d : q; \ + `else \ + q <= #(TCQ) d; \ + `endif \ + end + +`define XPREG_EN(clk, reset_n, q, d, rstval, en) \ + `ifndef SYNC_FF \ +`XPREG_ASYNC_EN(clk, reset_n, q, d, rstval, en) \ + `else \ +`XPREG_SYNC_EN(clk, reset_n, q, d, rstval, en) \ + `endif +`define XPREG_SYNC_EN(clk, reset_n, q, d, rstval, en) \ + always @(posedge clk) \ + begin \ + if (reset_n == 1'b0) \ + q <= #(TCQ) rstval; \ + else \ + `ifdef FOURVALCLKPROP \ + q <= #(TCQ) (en & clk) ? d : q; \ + `else \ + q <= #(TCQ) en ? d : q; \ + `endif \ + end +`define XPREG_ASYNC_EN(clk, reset_n, q, d, rstval, en) \ + always @(posedge clk or negedge reset_n) \ + begin \ + if (reset_n == 1'b0) \ + q <= #(TCQ) rstval; \ + else \ + `ifdef FOURVALCLKPROP \ + q <= #(TCQ) (en & clk) ? d : q; \ + `else \ + q <= #(TCQ) en ? d : q; \ + `endif \ + end + +`define XPREG_NORESET(clk,q,d) \ + always @(posedge clk) \ + begin \ + `ifdef FOURVALCLKPROP \ + q <= #(TCQ) clk? d : q; \ + `else \ + q <= #(TCQ) d; \ + `endif \ + end + +`define XARREG(clk, reset_n, q,d,rstval) \ +`ifndef SYNC_FF \ +`XARREG_ASYNC(clk, reset_n, q,d,rstval) \ +`else \ +`XARREG_SYNC(clk, reset_n, q,d,rstval) \ +`endif +`define XARREG_SYNC(clk, reset_n, q,d,rstval) \ + always @(posedge clk) \ + begin \ + if (reset_n == 1'b0) \ + q <= #(TCQ) rstval; \ + else \ + `ifdef FOURVALCLKPROP \ + q <= #(TCQ) clk ? d : q; \ + `else \ + q <= #(TCQ) d; \ + `endif \ + end +`define XARREG_ASYNC(clk, reset_n, q,d,rstval) \ + always @(posedge clk or negedge reset_n ) \ + begin \ + if (reset_n == 1'b0) \ + q <= #(TCQ) rstval; \ + else \ + `ifdef FOURVALCLKPROP \ + q <= #(TCQ) clk ? d : q; \ + `else \ + q <= #(TCQ) d; \ + `endif \ + end + +`define XARREG_EN(clk, reset_n, q, d, rstval, en) \ +`ifndef SYNC_FF \ +`XARREG_ASYNC_EN(clk, reset_n, q, d, rstval, en) \ +`else \ +`XARREG_SYNC_EN(clk, reset_n, q, d, rstval, en) \ +`endif +`define XARREG_SYNC_EN(clk, reset_n, q, d, rstval, en) \ + always @(posedge clk) \ + begin \ + if (reset_n == 1'b0) \ + q <= #(TCQ) rstval; \ + else \ + `ifdef FOURVALCLKPROP \ + q <= #(TCQ) ((en & clk) ? d : q); \ + `else \ + q <= #(TCQ) (en ? d : q); \ + `endif \ + end +`define XARREG_ASYNC_EN(clk, reset_n, q, d, rstval, en) \ + always @(posedge clk or negedge reset_n) \ + begin \ + if (reset_n == 1'b0) \ + q <= #(TCQ) rstval; \ + else \ + `ifdef FOURVALCLKPROP \ + q <= #(TCQ) ((en & clk) ? d : q); \ + `else \ + q <= #(TCQ) (en ? d : q); \ + `endif \ + end + +`define XSRREG(clk, reset_n, q,d,rstval) \ +`ifndef SYNC_FF \ +`XSRREG_ASYNC(clk, reset_n, q,d,rstval) \ +`else \ +`XSRREG_SYNC(clk, reset_n, q,d,rstval) \ +`endif +`define XSRREG_ASYNC(clk, reset_n, q,d,rstval) \ + always @(posedge clk or negedge reset_n) \ + begin \ + if (reset_n == 1'b0) \ + q <= #(TCQ) rstval; \ + else \ + `ifdef FOURVALCLKPROP \ + q <= #(TCQ) clk ? d : q; \ + `else \ + q <= #(TCQ) d; \ + `endif \ + end +`define XSRREG_SYNC(clk, reset_n, q,d,rstval) \ + always @(posedge clk) \ + begin \ + if (reset_n == 1'b0) \ + q <= #(TCQ) rstval; \ + else \ + `ifdef FOURVALCLKPROP \ + q <= #(TCQ) clk ? d : q; \ + `else \ + q <= #(TCQ) d; \ + `endif \ + end + +`define XSRREG_EN(clk, reset_n, q,d,rstval, en) \ +`ifndef SYNC_FF \ +`XSRREG_ASYNC_EN(clk, reset_n, q,d,rstval, en) \ +`else \ +`XSRREG_SYNC_EN(clk, reset_n, q,d,rstval, en) \ +`endif +`define XSRREG_SYNC_EN(clk, reset_n, q,d,rstval, en) \ + always @(posedge clk) \ + begin \ + if (reset_n == 1'b0) \ + q <= #(TCQ) rstval; \ + else \ + `ifdef FOURVALCLKPROP \ + q <= #(TCQ) ((en & clk) ? d : q); \ + `else \ + q <= #(TCQ) (en ? d : q); \ + `endif \ + end +`define XSRREG_ASYNC_EN(clk, reset_n, q,d,rstval, en) \ + always @(posedge clk or negedge reset_n) \ + begin \ + if (reset_n == 1'b0) \ + q <= #(TCQ) rstval; \ + else \ + `ifdef FOURVALCLKPROP \ + q <= #(TCQ) ((en & clk) ? d : q); \ + `else \ + q <= #(TCQ) (en ? d : q); \ + `endif \ + end + +`define XLREG(clk, reset_n) \ + `ifndef SYNC_FF \ +`XLREGS_ASYNC(clk, reset_n) \ + `else \ +`XLREGS_SYNC(clk, reset_n) \ + `endif +`define XLREGS_SYNC(clk, reset_n) \ + always @(posedge clk) +`define XLREGS_ASYNC(clk, reset_n) \ + always @(posedge clk or negedge reset_n) + +// Define for legacy FFs with arguments for edges +`define XLREG_EDGE(clkedge,clk,rstedge,rst) \ + `ifndef SYNC_FF \ +`XLREG_ASYNC_EDGE(clkedge,clk,rstedge,rst) \ + `else \ +`XLREG_SYNC_EDGE(clkedge,clk,rstedge,rst) \ + `endif +`define XLREG_SYNC_EDGE(clkedge,clk,rstedge,rst) \ + always @(clkedge clk) +`define XLREG_ASYNC_EDGE(clkedge,clk,rstedge,rst) \ + always @(clkedge clk or rstedge rst) + +// Define for legacy FFs with no reset and arguments for edges +`define XLREG_EDGE_NORESET(clkedge,clk) \ + always @(clkedge clk) \ + +//General defines +`define byte0 7:0 +`define byte1 15:8 +`define byte2 23:16 +`define byte3 31:24 +`define byte4 39:32 +`define byte5 47:40 +`define byte6 55:48 +`define byte7 63:56 +`define byte8 71:64 +`define byte9 79:72 +`define byte10 87:80 +`define byte11 95:88 +`define byte12 103:96 +`define byte13 111:104 +`define byte14 119:112 +`define byte15 127:120 +`define byte16 135:128 +`define byte17 143:136 +`define byte18 151:144 +`define byte19 159:152 +`define byte20 167:160 +`define byte21 175:168 +`define byte22 183:176 +`define byte23 191:184 +`define byte24 199:192 +`define byte25 207:200 +`define byte26 215:208 +`define byte27 223:216 +`define byte28 231:224 +`define byte29 239:232 +`define byte30 247:240 +`define byte31 255:248 + +`define dw0b0 7:0 +`define dw0b1 15:8 +`define dw0b2 23:16 +`define dw0b3 31:24 +`define dw0b012 23:0 +`define dw0b123 31:8 +`define dw1b0 39:32 +`define dw1b1 47:40 +`define dw1b2 55:48 +`define dw1b3 63:56 +`define dw1b012 55:32 +`define dw1b123 63:40 +`define dw2b0 71:64 +`define dw2b1 79:72 +`define dw2b2 87:80 +`define dw2b3 95:88 +`define dw2b012 87:64 +`define dw2b123 95:72 +`define dw3b0 103:96 +`define dw3b1 111:104 +`define dw3b2 119:112 +`define dw3b3 127:120 +`define dw3b012 119:96 +`define dw3b123 127:104 +`define dw4b0 135:128 +`define dw4b1 143:136 +`define dw4b2 151:144 +`define dw4b3 159:152 +`define dw4b012 151:128 +`define dw4b123 159:136 +`define dw5b0 167:160 +`define dw5b1 175:168 +`define dw5b2 183:176 +`define dw5b3 191:184 +`define dw5b012 183:160 +`define dw5b123 191:168 +`define dw6b0 199:192 +`define dw6b1 207:200 +`define dw6b2 215:208 +`define dw6b3 223:216 +`define dw6b123 223:200 +`define dw6b012 215:192 +`define dw7b0 231:224 +`define dw7b1 239:232 +`define dw7b2 247:240 +`define dw7b3 255:248 +`define dw7b012 247:224 +`define dw7b123 255:232 + +`define dw0 31:0 +`define dw1 63:32 +`define dw2 95:64 +`define dw3 127:96 +`define dw4 159:128 +`define dw5 191:160 +`define dw6 223:192 +`define dw7 255:224 + +`endif diff --git a/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/xdma_axi4mm_axi_bridge.vh b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/xdma_axi4mm_axi_bridge.vh new file mode 100755 index 0000000..41a7a99 --- /dev/null +++ b/projects/XUPVVH/XUPVVH.ip_user_files/ipstatic/hdl/verilog/xdma_axi4mm_axi_bridge.vh @@ -0,0 +1,202 @@ +`ifndef AXI_BRIDGE_VH +`define AXI_BRIDGE_VH +`include "pciedmacoredefines.vh" +//----------------------------------------------------------------------------- +// $Id: +//----------------------------------------------------------------------------- +// axi_bridge.vh +//----------------------------------------------------------------------------- +// (c) Copyright 2010 - 2016 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// Filename: axi_bridge.vh +// +// Description: +// +// This file needs to be included in all modules so that all the modules can commonly +// reference state_transitions +// +// +// VHDL-Standard: VHDL'93 +//----------------------------------------------------------------------------- +// Structure: +// Include file +// +//----------------------------------------------------------------------------- +// Revision: v1.05.a +// Date: 06/28/12 +// +//----------------------------------------------------------------------------- + +`timescale 1 ps / 1 ps +`define XSRREG_AXIMM(clk, reset_n, q,d,rstval) \ +`ifdef SOFT_IP \ +`XSRREG_SYNC (clk, reset_n, q,d,rstval) \ +`else \ +`XSRREG_ASYNC (clk, reset_n, q,d,rstval) \ +`endif + +`define XSRREG_EN_AXIMM(clk, reset_n, q,d,rstval, en) \ +`ifdef SOFT_IP \ +`XSRREG_SYNC_EN(clk, reset_n, q,d,rstval, en) \ +`else \ +`XSRREG_ASYNC_EN(clk, reset_n, q,d,rstval, en) \ +`endif + +`define XSRREG_XDMA(clk, reset_n, q,d,rstval) \ +`ifdef SOFT_IP \ +`XSRREG_SYNC (clk, reset_n, q,d,rstval) \ +`else \ +`XSRREG_ASYNC (clk, reset_n, q,d,rstval) \ +`endif + +`define XSRREG_EN_XDMA(clk, reset_n, q,d,rstval, en) \ +`ifdef SOFT_IP \ +`XSRREG_SYNC_EN(clk, reset_n, q,d,rstval, en) \ +`else \ +`XSRREG_ASYNC_EN(clk, reset_n, q,d,rstval, en) \ +`endif + +`define XLREG_AXIMM(clk, reset_n) \ +`ifdef SOFT_IP \ +`XLREGS_SYNC(clk, reset_n) \ +`else \ +`XLREGS_ASYNC(clk, reset_n) \ +`endif + +`define XLREG_XDMA(clk, reset_n) \ +`ifdef SOFT_IP \ +`XLREGS_SYNC(clk, reset_n) \ +`else \ +`XLREGS_ASYNC(clk, reset_n) \ +`endif + +`define XNRREG_AXIMM(clk,q,d) \ + always @(posedge clk) \ + begin \ + `ifdef FOURVALCLKPROP \ + q <= #(TCQ) clk? d : q; \ + `else \ + q <= #(TCQ) d; \ + `endif \ + end + +`define XNRREG_EN_AXIMM(clk,q,d,en) \ + always @(posedge clk) \ + begin \ + `ifdef FOURVALCLKPROP \ + q <= #(TCQ) ((en & clk) ? d : q); \ + `else \ + q <= #(TCQ) (en ? d : q); \ + `endif \ + end + +// AXI Defines +`define SIZE64 0 +`define SIZE128 1 +`define SIZE256 2 +`define SIZE512 3 +`define CQ_USER_FBELO 0 +`define CQ_USER_FBEHI 3 +`define CQ_USER_LBELO 4 +`define CQ_USER_LBEHI 7 +`define CQ_USER_LBELO_512 8 +`define CQ_USER_LBEHI_512 11 +`define CQ_USER_BELO 8 +`define CQ_USER_BEHI (CQ_USER_BELO +31) +`define CQ_USER_PARLO 53 +`define CQ_USER_PARLO_512 119 +`define CQ_USER_PARHI (CQ_USER_PARLO +31) +`define AXIS_MEM_READ 4'h0 +`define AXIS_MEM_WRITE 4'h1 +`define AXIS_IO_READ 4'h2 +`define AXIS_IO_WRITE 4'h3 +`define AXIS_IO_WRITE 4'h3 +`define AXIS_FETCH_ADD 4'h4 +`define AXIS_UCOND_SWAP 4'h5 +`define AXIS_COMP_SWAP 4'h6 +`define AXIS_READ_LCK 4'h7 +`define AXIS_CFGRD_TYPE0 4'h8 +`define AXIS_CFGRD_TYPE1 4'h9 +`define AXIS_CFGWR_TYPE0 4'ha +`define AXIS_CFGWR_TYPE1 4'hb +`define AXIS_MSG_GEN 4'hc +`define AXIS_MSG_VNDDEF 4'hd +`define AXIS_MSG_ATS 4'he +`define AXIS_RSVD 4'hf + + +`define AXIMM_RRESP_OK 2'b00 +`define AXIMM_RRESP_EXOK 2'b01 +`define AXIMM_RRESP_SLVERR 2'b10 +`define AXIMM_RRESP_DECERR 2'b11 +// typedef enum {IDLE_read_reqSM, CHECK_read_reqSM, SEND_REQ, WAIT_FOR_OPEN_SLOT} read_reqSM_STATES ; + // Add these to the State machines + //signal read_reqSM_cs : read_reqSM_STATES; + //signal read_reqSM_ns : read_reqSM_STATES; + +// typedef enum {IDLE_read_dataSM,WAIT_FOR_CPLE, LOAD_READ_COUNTERE, FIRST_BRAM_READE, STR_DATAE, STR_DONEE, WAIT_SLOT_CLRE} read_dataSM_STATES ; + // Add This to the appropriate file + //signal read_dataSM_cs : read_dataSM_STATES; + //signal read_dataSM_ns : read_dataSM_STATES; + //signal read_dataSM_cs_d : read_dataSM_STATES; + +// typedef enum {IDLE_arid_dependencySM, FIND_HISTORY_MATCH, SET_DEPENDENCY, CLEAR_DEPENDENCY} arid_dependencySM_STATES ; +// typedef enum {IDLE_write_reqSM, CHECK_write_reqSM, CHECK2, ONE_REQ_ACTIVE, TWO_REQ_ACTIVE} write_reqSM_STATES ; + + +// typedef enum {IDLE_write_dataSM, FIRST_DATA_WORD, DATA_STREAM, DONE_write_dataSM, WAIT_TLP_START, WAIT_STR_DONE, FIRST_DATA_WORD_2, DATA_STREAM_2, DONE_2} write_dataSM_STATES ; + +//function integer clog2; +// input [0:7] value; // Input value +// begin : dummy +// reg [0:7] value_int; +// value_int = value; +// for (clog2 = 0; value_int > 0; clog2 = clog2 + 1) +// value_int = value_int >> 1; +// end +//endfunction +`endif // AXI_BRIDGE_VH |