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Diffstat (limited to 'projects/XUSP3R/verilog/project.vh')
| -rw-r--r-- | projects/XUSP3R/verilog/project.vh | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/projects/XUSP3R/verilog/project.vh b/projects/XUSP3R/verilog/project.vh new file mode 100644 index 0000000..4df0b82 --- /dev/null +++ b/projects/XUSP3R/verilog/project.vh @@ -0,0 +1,21 @@ +`define XUPP3R_x8_1R_UDIMM// MIG does not support DM|DBI w/ RDIMMs. +`define DQ_WIDTH 64 + +// DIMM related - x8 double ranks +`ifdef XUPP3R_x8 +`define ODT_WIDTH 2 +`define CS_WIDTH 2 +`define CKE_WIDTH 2 +`define CK_WIDTH 1 +`elsif XUPP3R_x8_1R_UDIMM // Redundant here aswell. +`define ODT_WIDTH 1 +`define CS_WIDTH 1 +`define CKE_WIDTH 1 +`define CK_WIDTH 1 +`elsif XUPP3R_x4 +// DEFAULT CONFIGS USE BELOW +`define ODT_WIDTH 1 +`define CS_WIDTH 1 +`define CKE_WIDTH 1 +`define CK_WIDTH 1 +`endif
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