diff options
Diffstat (limited to 'sources/hdl/verilog/softmc_pipeline.v')
| -rw-r--r-- | sources/hdl/verilog/softmc_pipeline.v | 38 |
1 files changed, 21 insertions, 17 deletions
diff --git a/sources/hdl/verilog/softmc_pipeline.v b/sources/hdl/verilog/softmc_pipeline.v index 07c106e..43849f6 100644 --- a/sources/hdl/verilog/softmc_pipeline.v +++ b/sources/hdl/verilog/softmc_pipeline.v @@ -22,23 +22,25 @@ module softmc_pipeline( input ready_out, // ddr_pipeline <-> outer DDR module - output [3:0] ddr_write, - output [3:0] ddr_read, - output [3:0] ddr_pre, - output [3:0] ddr_act, - output [3:0] ddr_ref, - output [3:0] ddr_sre, - output [3:0] ddr_srx, - output [3:0] ddr_zq, - output [3:0] ddr_nop, - output [3:0] ddr_ap, - output [3:0] ddr_pall, - output [3:0] ddr_half_bl, - output [4*`BG_WIDTH-1:0] ddr_bg, - output [4*`BANK_WIDTH-1:0] ddr_bank, - output [4*`COL_WIDTH-1:0] ddr_col, - output [4*`ROW_WIDTH-1:0] ddr_row, - output [511:0] ddr_wdata + output [3:0] ddr_write, + output [3:0] ddr_read, + output [3:0] ddr_pre, + output [3:0] ddr_act, + output [3:0] ddr_ref, + output [3:0] ddr_sre, + output [3:0] ddr_srx, + output [3:0] ddr_zq, + output [3:0] ddr_nop, + output [3:0] ddr_ap, + output [3:0] ddr_pall, + output [3:0] ddr_half_bl, + output [3:0] ddr_rank, + output [4*`HBM_CH_WIDTH-1:0] hbm_ch, + output [4*`BG_WIDTH-1:0] ddr_bg, + output [4*`BANK_WIDTH-1:0] ddr_bank, + output [4*`COL_WIDTH-1:0] ddr_col, + output [4*`ROW_WIDTH-1:0] ddr_row, + output [511:0] ddr_wdata ); wire br_resolve; @@ -149,6 +151,8 @@ module softmc_pipeline( .ddr_ap(ddr_ap), .ddr_pall(ddr_pall), .ddr_half_bl(ddr_half_bl), + .hbm_ch(hbm_ch), + .ddr_rank(ddr_rank), .ddr_bg(ddr_bg), .ddr_bank(ddr_bank), .ddr_col(ddr_col), |