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// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
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// laws.
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axis_clock_converter:1.1
// IP Revision: 23
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
axis_clock_converter your_instance_name (
.s_axis_aresetn(s_axis_aresetn), // input wire s_axis_aresetn
.m_axis_aresetn(m_axis_aresetn), // input wire m_axis_aresetn
.s_axis_aclk(s_axis_aclk), // input wire s_axis_aclk
.s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid
.s_axis_tready(s_axis_tready), // output wire s_axis_tready
.s_axis_tdata(s_axis_tdata), // input wire [255 : 0] s_axis_tdata
.s_axis_tkeep(s_axis_tkeep), // input wire [31 : 0] s_axis_tkeep
.s_axis_tlast(s_axis_tlast), // input wire s_axis_tlast
.m_axis_aclk(m_axis_aclk), // input wire m_axis_aclk
.m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid
.m_axis_tready(m_axis_tready), // input wire m_axis_tready
.m_axis_tdata(m_axis_tdata), // output wire [255 : 0] m_axis_tdata
.m_axis_tkeep(m_axis_tkeep), // output wire [31 : 0] m_axis_tkeep
.m_axis_tlast(m_axis_tlast) // output wire m_axis_tlast
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file axis_clock_converter.v when simulating
// the core, axis_clock_converter. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
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