| Mode | Name | Size | |
|---|---|---|---|
| d--------- | axis_clock_converter | 217 | logstatsplain |
| d--------- | instr_blk_mem | 189 | logstatsplain |
| d--------- | instr_blk_mem_sim | 205 | logstatsplain |
| d--------- | phy_ddr4 | 169 | logstatsplain |
| d--------- | phy_ddr4_udimm | 193 | logstatsplain |
| d--------- | phy_rdimm_x8_dual | 205 | logstatsplain |
| d--------- | pr_read_mem | 181 | logstatsplain |
| d--------- | pr_ref_mem | 177 | logstatsplain |
| d--------- | rdback_fifo | 181 | logstatsplain |
| d--------- | scratchpad | 177 | logstatsplain |
| d--------- | xdma | 153 | logstatsplain |
| d--------- | zq_calib_mem | 185 | logstatsplain |
 |
index : dram-bender.git | |
| Experimental FPGA-based DRAM memory controller |
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