| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | README.txt | 2125 | logstatsplainblame |
| -rwxr-xr-x | custom_parts_ddr4_2016_4_and_above.csv | 2564 | logstatsplainblame |
| -rw-r--r-- | file_info.txt | 36708 | logstatsplainblame |
| -rw-r--r-- | glbl.v | 1762 | logstatsplainblame |
| -rwxr-xr-x | phy_ddr4.h | 15870 | logstatsplainblame |
| -rwxr-xr-x | phy_ddr4.sh | 16142 | logstatsplainblame |
| -rwxr-xr-x | phy_ddr4_sc.h | 2998 | logstatsplainblame |
| -rwxr-xr-x | sim_ddr_v2_0.h | 9286 | logstatsplainblame |
| -rw-r--r-- | simulate.do | 9 | logstatsplainblame |
 |
index : dram-bender.git | |
| Experimental FPGA-based DRAM memory controller |
| aboutsummaryrefslogtreecommitdiffstats |