| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | README.txt | 2097 | logstatsplainblame |
| -rw-r--r-- | file_info.txt | 39558 | logstatsplainblame |
| -rw-r--r-- | glbl.v | 1762 | logstatsplainblame |
| -rwxr-xr-x | phy_ddr4_udimm.h | 15889 | logstatsplainblame |
| -rwxr-xr-x | phy_ddr4_udimm.sh | 6252 | logstatsplainblame |
| -rwxr-xr-x | phy_ddr4_udimm_sc.h | 3058 | logstatsplainblame |
| -rw-r--r-- | run.f | 6848 | logstatsplainblame |
| -rwxr-xr-x | sim_ddr_v2_0.h | 9286 | logstatsplainblame |
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index : dram-bender.git | |
| Experimental FPGA-based DRAM memory controller |
| aboutsummaryrefslogtreecommitdiffstats |