vlog.prj « xsim « pr_read_mem « sim_scripts « U200.ip_user_files « U200 « projects - dram-bender.git - Experimental FPGA-based DRAM memory controller

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path: root/projects/U200/U200.ip_user_files/sim_scripts/pr_read_mem/xsim/vlog.prj

blob: 47ef91489596ad40773f2fd28a706b00f273eae7 (plain) (blame)

verilog xil_defaultlib  \
"../../../../U200.srcs/sources_1/ip/pr_read_mem/sim/pr_read_mem.v" \

verilog xil_defaultlib "glbl.v"

nosort