aboutsummaryrefslogtreecommitdiffstats
path: root/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/modelsim/simulate.do
blob: 13d9d23361cd165bb624ca06ca825c4340371865 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
onbreak {quit -f}
onerror {quit -f}

vsim -voptargs="+acc" -L xilinx_vip -L xpm -L fifo_generator_v13_2_5 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.rdback_fifo xil_defaultlib.glbl

do {wave.do}

view wave
view structure
view signals

do {rdback_fifo.udo}

run -all

quit -force