file_info.txt « xsim « rdback_fifo « sim_scripts « U200.ip_user_files « U200 « projects - dram-bender.git - Experimental FPGA-based DRAM memory controller

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1 2	`rdback_fifo.v,verilog,xil_defaultlib,../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, glbl.v,Verilog,xil_defaultlib,glbl.v`