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Experimental FPGA-based DRAM memory controller
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U200
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U200.ip_user_files
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sim_scripts
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rdback_fifo
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protoinst_files
Mode
Name
Size
-rw-r--r--
bd_9f2c.protoinst
88
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-rw-r--r--
bd_afa8.protoinst
88
log
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-rw-r--r--
bd_ba6a.protoinst
88
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plain
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