vlog.prj « xsim « rdback_fifo « sim_scripts « U200.ip_user_files « U200 « projects - dram-bender.git - Experimental FPGA-based DRAM memory controller

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path: root/projects/U200/U200.ip_user_files/sim_scripts/rdback_fifo/xsim/vlog.prj

blob: 094bca5aeffdf81a9ac089ff44a7ab799c1471b0 (plain) (blame)

verilog xil_defaultlib  \
"../../../../U200.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \

verilog xil_defaultlib "glbl.v"

nosort