blob: f20b0a896ee0b2d6149c3b09c23649bf32414c9c (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
|
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<!-- Nov 18 2020 -->
<!-- -->
<!-- This file is generated by the software with the Tcl write_mem_info command. -->
<!-- Do not edit this file. -->
<MemInfoSimulation Version="1" Minor="1">
<Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I">
<AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_64K_1_ADDR_SPACE" ECC="NONE" Begin="0" End="98303">
<BusBlock>
<BitLane MemType="lmb_bram_I_64K_1_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303">
<DataWidth MSB="31" LSB="0"/>
<AddressRange Begin="0" End="16383"/>
<Parity ON="false" NumBits="0"/>
<MemFile Name="bd_ba6a_lmb_bram_I_0.mem"/>
</BitLane>
</BusBlock>
</AddressSpace>
</Processor>
<Config>
<Option Name="Part" Val="xcu200-fsgd2104-2-e"/>
</Config>
<DRC>
<Rule Name="RDADDRCHANGE" Val="false"/>
</DRC>
</MemInfoSimulation>
|
