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Experimental FPGA-based DRAM memory controller
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U200
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U200.srcs
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sources_1
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ip
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phy_ddr4_udimm
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bd_0
Mode
Name
Size
-rw-r--r--
bd_ba6a.bd
12698
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stats
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-rw-r--r--
bd_ba6a.bxml
4893
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d---------
hdl
45
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d---------
ip
342
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