| Mode | Name | Size | |
|---|---|---|---|
| d--------- | axis_clock_converter | 104 | logstatsplain |
| d--------- | axis_clock_converter_1 | 104 | logstatsplain |
| d--------- | instr_blk_mem | 90 | logstatsplain |
| d--------- | instr_blk_mem_sim | 98 | logstatsplain |
| d--------- | phy_ddr4 | 203 | logstatsplain |
| d--------- | phy_ddr4_udimm | 215 | logstatsplain |
| d--------- | phy_rdimm_x8_dual | 221 | logstatsplain |
| d--------- | pr_read_mem | 86 | logstatsplain |
| d--------- | pr_ref_mem | 84 | logstatsplain |
| d--------- | rdback_fifo | 86 | logstatsplain |
| d--------- | scratchpad | 84 | logstatsplain |
| d--------- | xdma | 165 | logstatsplain |
| d--------- | zq_calib_mem | 88 | logstatsplain |
 |
index : dram-bender.git | |
| Experimental FPGA-based DRAM memory controller |
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