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Experimental FPGA-based DRAM memory controller
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U200
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Mode
Name
Size
-rw-r--r--
C1_RDIMM_X8_DUAL.xdc
31775
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plain
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-rw-r--r--
U200_C1_UDIMM.xdc
31949
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-rw-r--r--
U200_c1.xdc
29390
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blame