questa « behav « sim_1 « U50-HBM.sim « U50-HBM « projects - dram-bender.git - Experimental FPGA-based DRAM memory controller

Mode	Name	Size
-rw-r--r--	compile.log	5209	log stats plain blame
-rwxr-xr-x	compile.sh	680	log stats plain blame
-rw-r--r--	elaborate.log	5747	log stats plain blame
-rwxr-xr-x	elaborate.sh	675	log stats plain blame
-rw-r--r--	glbl.v	1762	log stats plain blame
-rwxr-xr-x	instr_blk_mem_sim.mif	35555	log stats plain blame
-rw-r--r--	modelsim.ini	159437	log stats plain blame
-rwxr-xr-x	pr_read.coe	919	log stats plain blame
-rwxr-xr-x	pr_read_mem.mif	1495	log stats plain blame
-rwxr-xr-x	pr_ref.coe	3295	log stats plain blame
-rwxr-xr-x	pr_ref_mem.mif	6110	log stats plain blame
-rwxr-xr-x	pr_zq.coe	2701	log stats plain blame
-rwxr-xr-x	program.coe	36163	log stats plain blame
-rwxr-xr-x	read.coe	1579	log stats plain blame
-rwxr-xr-x	ref.coe	6265	log stats plain blame
-rw-r--r--	sim_tb_top.udo	276	log stats plain blame
-rw-r--r--	sim_tb_top_compile.do	3483	log stats plain blame
-rw-r--r--	sim_tb_top_elaborate.do	518	log stats plain blame
-rw-r--r--	sim_tb_top_simulate.do	518	log stats plain blame
-rw-r--r--	sim_tb_top_wave.do	332	log stats plain blame
-rwxr-xr-x	simmem.coe	26196	log stats plain blame
-rw-r--r--	simulate.log	83983	log stats plain blame
-rwxr-xr-x	simulate.sh	704	log stats plain blame
-rw-r--r--	vsim.wlf	6643712	log stats plain blame
-rwxr-xr-x	xpm_internal_config_file_0.mem	838	log stats plain blame
-rwxr-xr-x	xpm_internal_config_file_1.mem	638	log stats plain blame
-rwxr-xr-x	xpm_internal_config_file_sim_0.mem	838	log stats plain blame
-rwxr-xr-x	xpm_internal_config_file_sim_1.mem	618	log stats plain blame
-rwxr-xr-x	zq.coe	5209	log stats plain blame
-rwxr-xr-x	zq_calib_mem.mif	5070	log stats plain blame