ip « sources_1 « U50-HBM.srcs « U50-HBM « projects - dram-bender.git - Experimental FPGA-based DRAM memory controller

Mode	Name	Size
d---------	axis_clock_converter	104	log stats plain
d---------	c_counter_binary_0	100	log stats plain
d---------	cdc_fifo	80	log stats plain
d---------	clk_wiz_0	82	log stats plain
d---------	cmd_fifo	80	log stats plain
d---------	hbm_0	74	log stats plain
d---------	instr_blk_mem	90	log stats plain
d---------	instr_blk_mem_sim	98	log stats plain
d---------	pr_read_mem	86	log stats plain
d---------	pr_ref_mem	84	log stats plain
d---------	rdback_fifo	86	log stats plain
d---------	scratchpad	84	log stats plain
d---------	wrdata_fifo	86	log stats plain
d---------	xdma	165	log stats plain
d---------	zq_calib_mem	88	log stats plain