| Mode | Name | Size | |
|---|---|---|---|
| d--------- | U50-HBM.hw | 70 | logstatsplain |
| d--------- | U50-HBM.ip_user_files | 108 | logstatsplain |
| d--------- | U50-HBM.sim / sim_1 / behav / questa | 32 | logstatsplain |
| d--------- | U50-HBM.srcs | 68 | logstatsplain |
| -rw-r--r-- | U50-HBM.xpr | 59875 | logstatsplainblame |
| d--------- | coe | 144 | logstatsplain |
| d--------- | constraints | 35 | logstatsplain |
| d--------- | verilog | 333 | logstatsplain |
 |
index : dram-bender.git | |
| Experimental FPGA-based DRAM memory controller |
| aboutsummaryrefslogtreecommitdiffstats |