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--- VU095.srcs/sources_1/ip/phy_ddr4/rtl/cal/ddr4_v2_2_cal_write.sv
@@ -157,9 +157,13 @@
// used in pushing new write CAS commands into the wrQ shift register. These values are
// calculated for both casslot0 and casslot2.
localparam FABRIC_CASSLOT0 = ( ALL_WR_LATENCY / 4 ) - 2;
+localparam FABRIC_CASSLOT1 = ( ( ALL_WR_LATENCY + 1 ) / 4 ) - 2;
localparam FABRIC_CASSLOT2 = ( ( ALL_WR_LATENCY + 2 ) / 4 ) - 2;
+localparam FABRIC_CASSLOT3 = ( ( ALL_WR_LATENCY + 3 ) / 4 ) - 2;
localparam OFFSET_CASSLOT0 = ( ALL_WR_LATENCY ) % 4;
+localparam OFFSET_CASSLOT1 = ( ALL_WR_LATENCY + 1 ) % 4;
localparam OFFSET_CASSLOT2 = ( ALL_WR_LATENCY + 2 ) % 4;
+localparam OFFSET_CASSLOT3 = ( ALL_WR_LATENCY + 3 ) % 4;
integer i;
@@ -192,10 +196,12 @@
// Output enable shift register fabric load cycle for cal and mc. mccasSlot2 is timing critical.
reg [3:0] oe_0_mux_cal;
wire [3:0] oe_0_mux_cal_nxt = calDone ? FABRIC_CASSLOT0 : FABRIC_CASSLOT2;
-wire [3:0] oe_fabric = mccasSlot2 ? FABRIC_CASSLOT2 : oe_0_mux_cal;
+wire [3:0] oe_fabric = mccasSlot2 ? (casSlot[0] ? FABRIC_CASSLOT3 : FABRIC_CASSLOT2) :
+ (casSlot[0] ? FABRIC_CASSLOT1 : oe_0_mux_cal);
// tCK offset for mc. mccasSlot2 is timing critical.
-wire [1:0] tck_offset = mccasSlot2 ? OFFSET_CASSLOT2 : OFFSET_CASSLOT0;
+wire [1:0] tck_offset = mccasSlot2 ? (casSlot[0] ? OFFSET_CASSLOT3 : OFFSET_CASSLOT2) :
+ (casSlot[0] ? OFFSET_CASSLOT1 : OFFSET_CASSLOT0);
// Output enable shift register load value for cal and mc. mcwrCAS and tck_offset are timing critical.
wire [DBAW+4:0] wrQ_cal_load_value = {winBuf, calRank, OFFSET_CASSLOT2[1:0], 1'b1};
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