project.vh « verilog « VU095 « projects - dram-bender.git - Experimental FPGA-based DRAM memory controller

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// `define ENABLE_DLL_TOGGLER
`define DQ_WIDTH 64
// DIMM related
`define ODT_WIDTH  1
`define CS_WIDTH   1
`define CKE_WIDTH  1
`define CK_WIDTH   1