aboutsummaryrefslogtreecommitdiffstats
path: root/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/axis_clock_converter/modelsim/simulate.do
blob: ccd294c605207116ba36ddd5ba2ae2cd4f8388d4 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
onbreak {quit -f}
onerror {quit -f}

vsim -voptargs="+acc" -t 1ps -L xpm -L axis_infrastructure_v1_1_0 -L axis_clock_converter_v1_1_21 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.axis_clock_converter xil_defaultlib.glbl

do {wave.do}

view wave
view structure
view signals

do {axis_clock_converter.udo}

run -all

quit -force