vlog.prj « xsim « instr_blk_mem « sim_scripts « XUPVVH.ip_user_files « XUPVVH « projects - dram-bender.git - Experimental FPGA-based DRAM memory controller

about summary refs log tree commit diff stats

path: root/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/instr_blk_mem/xsim/vlog.prj

blob: 418e20e4c4db53659b8b38c6dc81b441b1b2b431 (plain) (blame)

verilog xil_defaultlib  \
"../../../../XUPVVH.srcs/sources_1/ip/instr_blk_mem/sim/instr_blk_mem.v" \

verilog xil_defaultlib "glbl.v"

nosort