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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.2 (64-bit) -->
<!-- SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<!-- Nov 6 2019 -->
<!-- -->
<!-- This file is generated by the software with the Tcl write_mem_info command. -->
<!-- Do not edit this file. -->
<MemInfoSimulation Version="1" Minor="1">
<Processor Endianness="Little" InstPath="phy_ddr4_i/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I">
<AddressSpace Name="phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_microblaze_I.phy_ddr4_i_inst_u_ddr_cal_riu_mcs0_inst_lmb_bram_I_ADDR_SPACE" ECC="NONE" Begin="0" End="98303">
<BusBlock>
<BitLane MemType="lmb_bram_I_MEM_DEVICE" MemType_DataWidth="32" MemType_AddressDepth="98303">
<DataWidth MSB="31" LSB="0"/>
<AddressRange Begin="0" End="16383"/>
<Parity ON="false" NumBits="0"/>
<MemFile Name="bd_9f2c_lmb_bram_I_0.mem"/>
</BitLane>
</BusBlock>
</AddressSpace>
</Processor>
<Config>
<Option Name="Part" Val="xcvu37p-fsvh2892-2-e"/>
</Config>
<DRC>
<Rule Name="RDADDRCHANGE" Val="false"/>
</DRC>
</MemInfoSimulation>
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