file_info.txt « xsim « rdback_fifo « sim_scripts « XUPVVH.ip_user_files « XUPVVH « projects - dram-bender.git - Experimental FPGA-based DRAM memory controller

about summary refs log tree commit diff stats

path: root/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/file_info.txt

blob: 0b4b095ff8c77ad254677f632c8555a70ccdb1f7 (plain) (blame)

1 2	`rdback_fifo.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v, glbl.v,Verilog,xil_defaultlib,glbl.v`