vlog.prj « xsim « rdback_fifo « sim_scripts « XUPVVH.ip_user_files « XUPVVH « projects - dram-bender.git - Experimental FPGA-based DRAM memory controller

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path: root/projects/XUPVVH/XUPVVH.ip_user_files/sim_scripts/rdback_fifo/xsim/vlog.prj

blob: 6b0f840295a8e349dd1fd285ffbf17480911677b (plain) (blame)

verilog xil_defaultlib  \
"../../../../XUPVVH.srcs/sources_1/ip/rdback_fifo/sim/rdback_fifo.v" \

verilog xil_defaultlib "glbl.v"

nosort