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xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
xpm_memory.sv,systemverilog,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../tools/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_4,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
scratchpad.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
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