file_info.txt « xsim « scratchpad « sim_scripts « XUPVVH.ip_user_files « XUPVVH « projects - dram-bender.git - Experimental FPGA-based DRAM memory controller

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1 2	`scratchpad.v,verilog,xil_defaultlib,../../../../XUPVVH.srcs/sources_1/ip/scratchpad/sim/scratchpad.v, glbl.v,Verilog,xil_defaultlib,glbl.v`